ssc_i2s.h

#ifndef __SSC_I2S_H
#define __SSC_I2S_H
/*NB_REVISION*/
 
/*NB_COPYRIGHT*/
 
#include <predef.h>
#include <sim.h> /*on-chip register definitions*/
#include <pins.h>
#include <nbrtos.h>
#include <xdmac.h>
 
// class SSC_I2S : private Ssc {
//
//
// public:
//     inline void Reset() { SSC_CR = SSC_CR_SWRST; }
//     inline void EnableTx(bool enable) {
//         SSC_CR = (enable ? SSC_CR_TXEN : SSC_CR_TXDIS);
//     }
//     inline void EnableRx(bool enable) {
//         SSC_CR = (enable ? SSC_CR_RXEN : SSC_CR_RXDIS);
//     }
//     inline uint16_t SetClkDiv(uint16_t div) {
//         return SSC_CMR = div & SSC_CMR_DIV_Msk;
//     }
//
//     static Ssc *get() { return reinterpret_cast<SSC_I2S*>(SSC); }
//     Ssc &GetRegisers() { return *this; }
//
// } __attribute__((packed));
//
// static_assert( sizeof (SSC_I2S == sizeof(Ssc) );
//
 
typedef void (*SSC_BufferDoneFn_t)(void *buffer, bool valid);
/****************************************/
/*      SSC Configuration Enums         */
/****************************************/
enum clkSrc_t
{
    CLK_SRC_MCK, 
    CLK_SRC_RK,  
    CLK_SRC_TK   
};
 
enum startCond_t
{
    START_CONTINUOUS,
    START_SYNC_RX_TX,
    START_FRAME_LOW,
    START_FRAME_HIGH,
    START_FRAME_FALLING,
    START_FRAME_RISING,
    START_FRAME_LEVEL,
    START_FRAME_EDGE,
    START_CMP_0
};
 
enum clkGate_t
{
    CLK_GATE_CONTINUOUS, 
    CLK_GATE_FRAME_LOW,  
    CLK_GATE_FRAME_HIGH, 
};
 
enum dataValid_t
{
    DATA_VALID_RISING,  
    DATA_VALID_FALLING, 
};
 
enum frameEdge_t
{
    FRAME_SYNC_RISING, 
    FRAME_SYNC_FALLING 
};
 
enum clkOut_t
{
    CLK_OUT_INPUT,      
    CLK_OUT_CONTINUOUS, 
    CLK_OUT_TRANSFER    
};
 
enum frameSyncOut_t
{
    FRAME_SYNC_INPUT,    
    FRAME_SYNC_NEGATIVE, 
    FRAME_SYNC_POSITIVE, 
    FRAME_SYNC_LOW,      
    FRAME_SYNC_HIGH,     
    FRAME_SYNC_TOGGLE    
};
 
enum bitOrder_t
{
    LEAST_SIG_FIRST, 
    MOST_SIG_FIRST   
};
 
enum bufferDepletionBehavior_t
{
    DEPLETED_PAUSE,
    DEPLETED_REPEAT_LAST,
};
 
/****************************************/
/*      SSC Configuration Struct        */
/****************************************/
 
struct SSC_rxtx_cfg_t
{
    bool enable{false};
    uint8_t period{64};
    uint8_t startDly{1};
    startCond_t startCond{START_FRAME_EDGE};
    clkGate_t clkGate{CLK_GATE_CONTINUOUS};
    dataValid_t dataValid{DATA_VALID_RISING};
    clkOut_t clkOut{CLK_OUT_INPUT};
    clkSrc_t clkSrc{CLK_SRC_RK};
 
    uint8_t syncLen{0};
    frameEdge_t syncEdge{FRAME_SYNC_FALLING};
    bool syncDataEnabled{false};
    frameSyncOut_t syncOut{FRAME_SYNC_INPUT};
    uint8_t wordsPerFrame{1};
    bitOrder_t bitOrder{MOST_SIG_FIRST};
    bool lineIdleState{1};
    uint8_t bitsPerWord{24};
 
    bufferDepletionBehavior_t depletionBehavior{DEPLETED_PAUSE};
};
 
struct SSC_cfg_t
{
    uint16_t clkDiv{150};
 
    SSC_rxtx_cfg_t rx;
    SSC_rxtx_cfg_t tx;
};
 
extern const SSC_cfg_t SSC_I2S_SLAVE_24_TXRX_RK;
extern const SSC_cfg_t SSC_I2S_SLAVE_24_TXRX_TK;
extern const SSC_cfg_t SSC_I2S_SLAVE_24_TXRX_TKRK;
extern const SSC_cfg_t SSC_I2S_SLAVE_16_TXRX_RK;
extern const SSC_cfg_t SSC_I2S_SLAVE_16_TXRX_TK;
extern const SSC_cfg_t SSC_I2S_SLAVE_16_TXRX_TKRK;
extern const SSC_cfg_t SSC_I2S_SLAVE_8_TXRX_RK;
extern const SSC_cfg_t SSC_I2S_SLAVE_8_TXRX_TK;
extern const SSC_cfg_t SSC_I2S_SLAVE_8_TXRX_TKRK;
 
extern const SSC_cfg_t SSC_LJUST_SLAVE_24_TXRX_RK;
extern const SSC_cfg_t SSC_LJUST_SLAVE_24_TXRX_TK;
extern const SSC_cfg_t SSC_LJUST_SLAVE_24_TXRX_TKRK;
extern const SSC_cfg_t SSC_LJUST_SLAVE_16_TXRX_RK;
extern const SSC_cfg_t SSC_LJUST_SLAVE_16_TXRX_TK;
extern const SSC_cfg_t SSC_LJUST_SLAVE_16_TXRX_TKRK;
extern const SSC_cfg_t SSC_LJUST_SLAVE_8_TXRX_RK;
extern const SSC_cfg_t SSC_LJUST_SLAVE_8_TXRX_TK;
extern const SSC_cfg_t SSC_LJUST_SLAVE_8_TXRX_TKRK;
 
/****************************************/
/*      SSC Driver Context Object       */
/****************************************/
 
class SSCCtx_t
{
   public:
    enum ctxState_t
    {
        CTX_STATE_STOPPED,
        CTX_STATE_INIT,
        CTX_STATE_TX,
        CTX_STATE_RX,
        CTX_STATE_TXRX,
    };
 
   private:
    XdmaCh_t *txCh;
    XdmaCh_t *rxCh;
    OS_SEM txSem;
    OS_SEM rxSem;
    SSC_BufferDoneFn_t txBufDone;
    SSC_BufferDoneFn_t rxBufDone;
    uint32_t txReadyCount;
    uint32_t rxReadyCount;
    uint32_t nTxIrq;
    uint32_t nTxErr;
    uint32_t nTxPost;
    uint32_t nTxCall;
    uint32_t nTxStart;
    uint32_t nTxAdd;
 
    uint32_t nRxIrq;
    uint32_t nRxErr;
    uint32_t nRxPost;
    uint32_t nRxCall;
    uint32_t nRxStart;
    uint32_t nRxAdd;
 
    Desc0Ring TxRing;
    Desc0Ring RxRing;
    uint8_t rxByteWidth;
    uint8_t txByteWidth;
 
    ctxState_t state;
    void initBDs(bool loopRx, bool loopTx);
    void initHw_Pins(const SSC_cfg_t &cfg);
    void initHw_SSC(const SSC_cfg_t &cfg);
    void initHw_DMA(const SSC_cfg_t &cfg);
 
   public:
    int Init(const SSC_cfg_t &cfg);
    void Shutdown();
 
    int getCurrentConfig(SSC_cfg_t &cfg);
    ctxState_t getState();
 
    int TransmitBuffer(void *buffer, uint32_t bufferLen, bool waitIfNeeded);
    int ReadyReceiveBuffer(void *buffer, uint32_t bufferLen, bool waitIfNeeded);
 
    void RegisterTxBufferDoneCB(SSC_BufferDoneFn_t cb);
    void RegisterRxBufferDoneCB(SSC_BufferDoneFn_t cb);
 
    void TxIsr();
    void RxIsr();
 
    void dump();
};
 
extern SSCCtx_t ssc;
 
#endif /* ----- #ifndef __SSC_I2S_H  ----- */