SEMC Simple

Location: examples/PlatformSpecific/SOMRT1061/SEMC

SOMRT1061 Smart External Memory Controller (SEMC) Simple Example

Overview

This example demonstrates the basic usage of the Smart External Memory Controller (SEMC) on the SOMRT1061 platform. The SEMC provides an interface to external memory devices with configurable timing and bus width settings.

Supported Platforms

• SOMRT1061

Application Description

The main application (main.cpp) provides an interactive demonstration of SEMC functionality with the following features:

Key Components

• SEMC Configuration: Configures the external memory controller with 8-bit bus width, synchronous clock mode, and burst operation
• Clock Management: Sets up appropriate clock multiplexers and dividers for SEMC operation
• Interactive Testing: Command-line interface for testing memory operations

Configuration Parameters

The SEMC is configured with the following settings:

Bus Width: 8-bit
Clock Mode: Synchronous
Burst Mode: 16-word burst
Column Address Width: 4-bit
Address Multiplexing: Enabled

Timing Configuration

• Setup times and hold times are configured for reliable memory access
• Clock dividers are set to achieve proper SEMC frequency
• USB PLL bypass is utilized during memory operations

Test Constants

• Test Address Offset: 0xA5
• Test Data (16-bit): 0x5A5A
• Test Data (8-bit): 0x5A

Interactive Commands

The application provides a command-line interface with the following options:

Command	Function	Description
R	Read	Reads data from the test address offset and displays the result
W	Write	Writes test data to the test address offset
T	Test Variable	Writes 0xDEADBEEF to a test variable in external memory
F	Fast Read	Performs 4096 consecutive read operations for performance testing
C	Continuous Write	Performs 4096 consecutive write operations with incremental data

Memory Layout

The application uses a special memory section DATABUS_VAR_SECT for placing variables in external memory. The TestVar variable is specifically allocated to this section to demonstrate external memory usage.

Clock Configuration

The application configures several clock domains:

• SEMC Clock: Derived from USB1 PLL with appropriate dividers
• CPU Clock: System CPU frequency
• UART Clock: For serial communication
• USB PLL: Used as clock source with bypass capability

Usage

1. Compile and Flash: Build the application for SOMRT1061 and flash to the device
2. Serial Connection: Connect to the device via UART to see output and provide input
3. Interactive Testing: Use the command interface to test different memory operations
4. Monitor Output: Observe memory access results and frequency information

Expected Output

Upon startup, the application displays:

• Application name and version
• SEMC frequency information
• UART frequency information
• Interactive command prompt

Technical Notes

Memory Access Patterns

• Single byte operations for basic read/write testing
• Burst operations for performance evaluation
• Variable placement in external memory sections

Clock Management

• USB PLL bypass is enabled during memory operations to ensure stable timing
• Multiple data synchronization barriers (dsb) are used to ensure proper instruction ordering
• Clock frequencies are displayed for debugging and verification

Error Handling

The application includes basic system diagnostics and proper initialization sequences to ensure reliable operation.

Dependencies

• NetBurner RTOS libraries
• FSL (Freescale) clock management libraries
• SEMC hardware abstraction layer
• Standard C libraries for I/O operations

Development Notes

• Remove EnableSystemDiagnostics() call for production builds
• Adjust timing parameters based on specific external memory device requirements
• Consider memory access patterns for optimal performance
• Ensure proper pin configuration for SEMC signals