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edma_impl.h
1#ifndef __EDMA_IMPL_H
2#define __EDMA_IMPL_H
3#include <edma.h>
4
5inline
6void
7DmaTcd::
8SetMinorLinkCh(uint32_t linkCh)
9{
10 BITER_ELINKYES = CITER_ELINKYES
11 = (BITER_ELINKYES & DMA_BITER_ELINKYES_BITER_MASK)
12 | DMA_BITER_ELINKYES_ELINK(1) | DMA_BITER_ELINKYES_LINKCH(linkCh);
13}
14
15inline
16void
17DmaTcd::
18SetMajorLinkCh(uint32_t linkCh)
19{
20 CSR = (CSR & ~DMA_CSR_MAJORLINKCH_MASK)
21 | DMA_CSR_MAJORLINKCH(linkCh) | DMA_CSR_MAJORELINK(1);
22}
23
24inline
25void
26DmaTcd::
27ClrMajorLink()
28{
29 CSR = (CSR & ~(DMA_CSR_MAJORLINKCH_MASK | DMA_CSR_MAJORELINK_MASK));
30}
31
32inline bool DmaTcd::IsHwCh()
33{
34 return (((uint32_t)this) >= ((uint32_t)(DMA0->TCD)))
35 && (((uint32_t)this) < ((uint32_t)(DMA0->TCD+DMAMUX_CHCFG_COUNT)));
36}
37
38inline uint32_t DmaTcd::SrcAddr() const { return SADDR; }
39inline uint32_t DmaTcd::DestAddr() const { return DADDR; }
40inline DmaTcd::eSize DmaTcd::SrcSize() const
41 { return (eSize)((ATTR & DMA_ATTR_SSIZE_MASK) >> DMA_ATTR_SSIZE_SHIFT); }
42inline DmaTcd::eSize DmaTcd::DestSize() const
43 { return (eSize)((ATTR & DMA_ATTR_DSIZE_MASK) >> DMA_ATTR_DSIZE_SHIFT); }
44inline uint8_t DmaTcd::SrcRingBuf() const
45 { return ((ATTR & DMA_ATTR_SMOD_MASK) >> DMA_ATTR_SMOD_SHIFT); }
46inline uint8_t DmaTcd::DestRingBuf() const
47 { return ((ATTR & DMA_ATTR_DMOD_MASK) >> DMA_ATTR_DMOD_SHIFT); }
48inline uint32_t DmaTcd::TotalBytes() const { return MinorSize() * MajorCount(); }
49
50inline void DmaTcd::SetSrcAddr(void *src) { SADDR = (uint32_t)src; }
51inline void DmaTcd::SetDestAddr(void *dest) { DADDR = (uint32_t)dest; }
52inline void DmaTcd::SetSrcSize(eSize srcSize)
53 { ATTR = (ATTR & ~DMA_ATTR_SSIZE_MASK) | DMA_ATTR_SSIZE(srcSize); }
54inline void DmaTcd::SetDestSize(eSize destSize)
55 { ATTR = (ATTR & ~DMA_ATTR_DSIZE_MASK) | DMA_ATTR_DSIZE(destSize); }
56inline void DmaTcd::SetSrcRingBuf(uint8_t logLen)
57 { ATTR = (ATTR & ~DMA_ATTR_SMOD_MASK) | DMA_ATTR_SMOD(logLen); }
58inline void DmaTcd::SetDestRingBuf(uint8_t logLen)
59 { ATTR = (ATTR & ~DMA_ATTR_DMOD_MASK) | DMA_ATTR_DMOD(logLen); }
60
61inline DmaTcd *DmaTcd::NextTcd() const { return (DmaTcd *)DLAST_SGA; }
62
63inline bool DmaTcd::MajorIrqEnabled() const { return CSR & DMA_CSR_INTMAJOR_MASK; }
64inline bool DmaTcd::HalfMajorIrqEnabled() const { return CSR & DMA_CSR_INTHALF_MASK; }
65inline bool DmaTcd::IsActive() const { return CSR & DMA_CSR_ACTIVE_MASK; }
66inline bool DmaTcd::IsDone() const { return CSR & DMA_CSR_DONE_MASK; }
67inline bool DmaTcd::DisableReqEnabled() const { return CSR & DMA_CSR_DREQ_MASK; }
68
69inline void DmaTcd::ClrDone() { CSR &= ~DMA_CSR_DONE_MASK; }
70inline void DmaTcd::SetDisableRequest() { CSR |= DMA_CSR_DREQ_MASK; }
71inline void DmaTcd::ClrDisableRequest() { CSR &= ~DMA_CSR_DREQ_MASK; }
72
73
74inline void DmaTcd::EnableMajorIrq() { CSR |= DMA_CSR_INTMAJOR_MASK; }
75inline void DmaTcd::DisableMajorIrq() { CSR &= ~DMA_CSR_INTMAJOR_MASK; }
76inline void DmaTcd::EnableHalfMajorIrq() { CSR |= DMA_CSR_INTHALF_MASK; }
77inline void DmaTcd::DisableHalfMajorIrq() { CSR &= ~DMA_CSR_INTHALF_MASK; }
78
79
80inline DmaCh *DmaCh::GetCtx(uint32_t chId)
81{
82 return (chId > 32) ? NULL : (DmaCh*)(DMA0->TCD+chId);
83}
84
85inline uint32_t DmaCh::ChId() const
86 { return (((DMA_Type::_TCD_t*)this) - DMA0->TCD); }
87
88/* DMA Channel Mux config methods */
89inline void DmaCh::ResetSrcCfg()
90 { DMAMUX->CHCFG[ChId()] = 0; }
91
92inline dma_req_src_t DmaCh::GetReqSource()
93{
94 return (dma_req_src_t)((DMAMUX->CHCFG[ChId()]) & DMAMUX_CHCFG_SOURCE_MASK);
95}
96inline dma_req_src_t DmaCh::SetReqSource(dma_req_src_t src)
97{
98 DMAMUX->CHCFG[ChId()]
99 = (DMAMUX->CHCFG[ChId()] & ~DMAMUX_CHCFG_SOURCE_MASK)
100 | DMAMUX_CHCFG_SOURCE(src);
101 return GetReqSource();
102}
103
104inline bool DmaCh::IsTriggerable() { return (1ul << ChId()) & DMA_TRIGGERABLE_CHANNEL_MASK; }
105
106inline void DmaCh::EnableSource() { DMAMUX->CHCFG[ChId()] |= DMAMUX_CHCFG_ENBL_MASK; }
107inline void DmaCh::DisableSource() { DMAMUX->CHCFG[ChId()] &= ~DMAMUX_CHCFG_ENBL_MASK; }
108inline bool DmaCh::SourceEnabled() { return DMAMUX->CHCFG[ChId()] & DMAMUX_CHCFG_ENBL_MASK; }
109
110inline void DmaCh::EnableTrigger() { DMAMUX->CHCFG[ChId()] |= DMAMUX_CHCFG_TRIG_MASK; }
111inline void DmaCh::DisableTrigger() { DMAMUX->CHCFG[ChId()] &= ~DMAMUX_CHCFG_TRIG_MASK; }
112inline bool DmaCh::TriggerEnabled() { return DMAMUX->CHCFG[ChId()] & DMAMUX_CHCFG_TRIG_MASK; }
113
114inline void DmaCh::EnableAlwaysOn() { DMAMUX->CHCFG[ChId()] |= DMAMUX_CHCFG_A_ON_MASK; }
115inline void DmaCh::DisableAlwaysOn(){ DMAMUX->CHCFG[ChId()] &= ~DMAMUX_CHCFG_A_ON_MASK; }
116inline bool DmaCh::AlwaysOnEnabled(){ return DMAMUX->CHCFG[ChId()] & DMAMUX_CHCFG_A_ON_MASK; }
117
118/* DMA Channel Methods */
119inline bool DmaCh::HaveError() { return (DMA0->ES & (1ul << ChId())); }
120inline bool DmaCh::HaveIrq() { return (DMA0->INT & (1ul << ChId())); }
121inline bool DmaCh::ReqEnabled() { return (DMA0->ERQ & (1ul << ChId())); }
122inline bool DmaCh::ErrIrqEnabled() { return (DMA0->EEI & (1ul << ChId())); }
123inline bool DmaCh::ReqActive() { return (DMA0->HRS & (1ul << ChId())); }
124
125inline void DmaCh::EnableErrIrq() { DMA0->SEEI = DMA_SEEI_SEEI(ChId()); }
126inline void DmaCh::DisableErrIrq() { DMA0->CEEI = DMA_CEEI_CEEI(ChId()); }
127inline void DmaCh::EnableHwReq() { DMA0->SERQ = DMA_SERQ_SERQ(ChId()); }
128inline void DmaCh::DisableHwReq() { DMA0->CERQ = DMA_CERQ_CERQ(ChId()); }
129inline void DmaCh::EnableAsyncStopReq() { DMA0->EARS |= (1UL << ChId()); }
130inline void DmaCh::DisableAsyncStopReq() { DMA0->EARS &= ~(1UL << ChId()); }
131
132inline void DmaCh::ClrErr() { DMA0->CERR = DMA_CERR_CERR(ChId()); }
133inline void DmaCh::ClrIrq() { DMA0->CINT = DMA_CINT_CINT(ChId()); }
134inline void DmaCh::ForceStart() { DMA0->SSRT = DMA_SSRT_SSRT(ChId()); }
135
136inline uint32_t DmaCh::LastError() const { return sLastErr[ChId()]; }
137inline void DmaCh::ClrLastError() { sLastErr[ChId()] = 0; }
138
139/* DMA Channel Reference Methods*/
140//inline static DmaChRef DmaChRef::GetCtx(uint32_t chId) { return pRef->GetCtx(uint32_t chId); }
141inline DmaChRef::operator DmaTcd() const { return *pCh; }
142inline const DmaTcd & DmaChRef::operator=(const DmaTcd &rhs) const { return *pCh = rhs; }
143inline bool DmaChRef::IsValid() const { return (pCh != NULL); }
144inline bool DmaChRef::Alloc() { pCh = new DmaCh(); return (pCh != NULL); }
145inline void DmaChRef::Release() { if (pCh) delete pCh; pCh = NULL; }
146inline uint32_t DmaChRef::ChId() const { return pCh->ChId(); }
147inline DmaChRef::IsrCtx DmaChRef::RegisterIsr(DmaIsrFn isrFn, void *isrCtx) { return pCh->RegisterIsr(isrFn, isrCtx); }
148
149/* DMA Channel Mux config methods */
150inline void DmaChRef::ResetSrcCfg() const { pCh->ResetSrcCfg(); }
151
152inline dma_req_src_t DmaChRef::GetReqSource() const { return pCh->GetReqSource(); }
153inline dma_req_src_t DmaChRef::SetReqSource(dma_req_src_t src) const { return pCh->SetReqSource(src); }
154
155inline bool DmaChRef::IsTriggerable() const { return pCh->IsTriggerable(); }
156
157inline void DmaChRef::EnableSource() const { pCh->EnableSource(); }
158inline void DmaChRef::DisableSource() const { pCh->DisableSource(); }
159inline bool DmaChRef::SourceEnabled() const { return pCh->SourceEnabled(); }
160
161inline void DmaChRef::EnableTrigger() const { pCh->EnableTrigger(); }
162inline void DmaChRef::DisableTrigger() const { pCh->DisableTrigger(); }
163inline bool DmaChRef::TriggerEnabled() const { return pCh->TriggerEnabled(); }
164
165inline void DmaChRef::EnableAlwaysOn() const { pCh->EnableAlwaysOn(); }
166inline void DmaChRef::DisableAlwaysOn() const { pCh->DisableAlwaysOn(); }
167inline bool DmaChRef::AlwaysOnEnabled() const { return pCh->AlwaysOnEnabled(); }
168
169/* DMA Channel Methods */
170inline bool DmaChRef::HaveError() const { return pCh->HaveError(); }
171inline bool DmaChRef::HaveIrq() const { return pCh->HaveIrq(); }
172inline bool DmaChRef::ReqEnabled() const { return pCh->ReqEnabled(); }
173inline bool DmaChRef::ErrIrqEnabled() const { return pCh->ErrIrqEnabled(); }
174inline bool DmaChRef::ReqActive() const { return pCh->ReqActive(); }
175
176inline void DmaChRef::EnableErrIrq() const { pCh->EnableErrIrq(); }
177inline void DmaChRef::DisableErrIrq() const { pCh->DisableErrIrq(); }
178inline void DmaChRef::EnableHwReq() const { pCh->EnableHwReq(); }
179inline void DmaChRef::DisableHwReq() const { pCh->DisableHwReq(); }
180inline void DmaChRef::EnableAsyncStopReq() const { pCh->EnableAsyncStopReq(); }
181inline void DmaChRef::DisableAsyncStopReq() const { pCh->DisableAsyncStopReq(); }
182
183inline void DmaChRef::ClrErr() const { pCh->ClrErr(); }
184inline void DmaChRef::ClrIrq() const { pCh->ClrIrq(); }
185inline void DmaChRef::ForceStart() const { pCh->ForceStart(); }
186inline void DmaChRef::ForceStop() const { pCh->ForceStop(); }
187inline uint32_t DmaChRef::LastError() const { return pCh->LastError(); }
188inline void DmaChRef::ClrLastError() const { pCh->ClrLastError(); }
189
190/* DmaTcd methods */
191
192inline bool DmaChRef::IsHwCh() const { return pCh->IsHwCh(); }
193
194inline void DmaChRef::ResetTcd() const { pCh->ResetTcd(); }
195
196inline uint32_t DmaChRef::MinorSize() const { return pCh->MinorSize(); }
197inline uint32_t DmaChRef::SetMinorSize(uint32_t size) const { return pCh->SetMinorSize(size); }
198inline uint32_t DmaChRef::MajorCount() const { return pCh->MajorCount(); }
199inline uint32_t DmaChRef::SetMajorCount(uint32_t count) const { return pCh->SetMajorCount(count); }
200inline uint32_t DmaChRef::SetMajorCount(uint32_t count, int eLinkCh) const { return pCh->SetMajorCount(count, eLinkCh); }
201
202inline uint32_t DmaChRef::SrcAddr() const { return pCh->SrcAddr(); }
203inline uint32_t DmaChRef::DestAddr() const { return pCh->DestAddr(); }
204inline DmaTcd::eSize DmaChRef::SrcSize() const { return pCh->SrcSize(); }
205inline DmaTcd::eSize DmaChRef::DestSize() const { return pCh->DestSize(); }
206inline uint8_t DmaChRef::SrcRingBuf() const { return pCh->SrcRingBuf(); }
207inline uint8_t DmaChRef::DestRingBuf() const { return pCh->DestRingBuf(); }
208inline uint32_t DmaChRef::TotalBytes() const { return pCh->TotalBytes(); }
209
210inline void DmaChRef::SetTxn(void *dest, void *src, uint32_t bytes, DmaTcd::eSize destSize, DmaTcd::eSize srcSize) const { pCh->SetTxn(dest, src, bytes, destSize, srcSize); }
211
212inline void DmaChRef::SetSrcAddr(void *src) const { pCh->SetSrcAddr(src); }
213inline void DmaChRef::SetDestAddr(void *dest) const { pCh->SetDestAddr(dest); }
214inline void DmaChRef::SetSrcSize(DmaTcd::eSize srcSize) const { pCh->SetSrcSize(srcSize); }
215inline void DmaChRef::SetDestSize(DmaTcd::eSize destSize) const { pCh->SetDestSize(destSize); }
216inline void DmaChRef::SetSrcRingBuf(uint8_t logLen) const { pCh->SetSrcRingBuf(logLen); }
217inline void DmaChRef::SetDestRingBuf(uint8_t logLen) const { pCh->SetDestRingBuf(logLen); }
218
219inline int16_t DmaChRef::SetOffset(DmaTcd::eOffsetAddr target, int16_t offset) const { return pCh->SetOffset(target, offset); }
220inline int32_t DmaChRef::SetMinorLoopOffset(DmaTcd::eOffsetAddr target, int32_t offset) const { return pCh->SetMinorLoopOffset(target, offset); }
221inline uint32_t DmaChRef::SetLastOffest(DmaTcd::eOffsetAddr target, uint32_t offset) const { return pCh->SetLastOffest(target, offset); }
222
223inline void DmaChRef::SetMinorLinkCh(uint32_t linkCh) const { pCh->SetMinorLinkCh(linkCh); }
224inline void DmaChRef::SetMajorLinkCh(uint32_t linkCh) const { pCh->SetMajorLinkCh(linkCh); }
225inline void DmaChRef::ClrMinorLink() const { pCh->ClrMinorLink(); }
226inline void DmaChRef::ClrMajorLink() const { pCh->ClrMajorLink(); }
227
228inline void DmaChRef::SetNextTcd(DmaTcd *pNextTcd) const { pCh->SetNextTcd(pNextTcd); }
229inline DmaTcd * DmaChRef::NextTcd() const { return pCh->NextTcd(); }
230
231inline bool DmaChRef::MajorIrqEnabled() const { return pCh->MajorIrqEnabled(); }
232inline bool DmaChRef::HalfMajorIrqEnabled() const { return pCh->HalfMajorIrqEnabled(); }
233inline bool DmaChRef::IsActive() const { return pCh->IsActive(); }
234inline bool DmaChRef::IsDone() const { return pCh->IsDone(); }
235inline bool DmaChRef::DisableReqEnabled() const { return pCh->DisableReqEnabled(); }
236
237inline void DmaChRef::ClrDone() const { pCh->ClrDone(); }
238inline void DmaChRef::SetDisableRequest() const { pCh->SetDisableRequest(); }
239inline void DmaChRef::ClrDisableRequest() const { pCh->ClrDisableRequest(); }
240
241inline void DmaChRef::EnableMajorIrq() const { pCh->EnableMajorIrq(); }
242inline void DmaChRef::DisableMajorIrq() const { pCh->DisableMajorIrq(); }
243inline void DmaChRef::EnableHalfMajorIrq() const { pCh->EnableHalfMajorIrq(); }
244inline void DmaChRef::DisableHalfMajorIrq() const { pCh->DisableHalfMajorIrq(); }
245
246inline void DmaChRef::Dump() const { pCh->Dump(); }
247
248#endif /* ----- #ifndef __EDMA_IMPL_H ----- */