NetBurner 3.5.7
PDF Version
MIMXRT1061.h
1/*
2** ###################################################################
3** Processors: MIMXRT1061CVJ5A
4** MIMXRT1061CVL5A
5** MIMXRT1061DVJ6A
6** MIMXRT1061DVL6A
7**
8** Compilers: Freescale C/C++ for Embedded ARM
9** GNU C Compiler
10** IAR ANSI C/C++ Compiler for ARM
11** Keil ARM C/C++ Compiler
12** MCUXpresso Compiler
13**
14** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
15** Version: rev. 1.2, 2019-04-29
16** Build: b190429
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MIMXRT1061
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2019 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 0.1 (2017-01-10)
32** Initial version.
33** - rev. 1.0 (2018-11-16)
34** Update header files to align with IMXRT1060RM Rev.0.
35** - rev. 1.1 (2018-11-27)
36** Update header files to align with IMXRT1060RM Rev.1.
37** - rev. 1.2 (2019-04-29)
38** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
39**
40** ###################################################################
41*/
42
43/*
44 * @file MIMXRT1061.h
45 * @version 1.2
46 * @date 2019-04-29
47 * @brief CMSIS Peripheral Access Layer for MIMXRT1061
48 *
49 * CMSIS Peripheral Access Layer for MIMXRT1061
50 */
51
52#ifndef _MIMXRT1061_H_
53#define _MIMXRT1061_H_
55/* Memory map major version (memory maps with equal major version number are compatible) */
56#define MCU_MEM_MAP_VERSION 0x0100U
57/* Memory map minor version */
58#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
59
60#include <cm_core_config.h>
61
62#include "core_cm7.h" /* Core Peripheral Access Layer */
63//#include "system_MIMXRT1061.h" /* Device specific configuration file */
64
65/* @} SHOULD NOT BE HERE end of group Cortex_Core_Configuration */
66
67
68/* ----------------------------------------------------------------------------
69 -- Mapping Information
70 ---------------------------------------------------------------------------- */
71
72/*
73 * @addtogroup Mapping_Information Mapping Information
74 * @{
75 */
76
77
78/* Mapping Information */
79
80
81/*
82 * @addtogroup edma_request
83 * @{
84 */
85
86/*******************************************************************************
87 * Definitions
88 ******************************************************************************/
89
90/*
91 * @brief Structure for the DMA hardware request
92 *
93 * Defines the structure for the DMA hardware request collections. The user can configure the
94 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
95 * of the hardware request varies according to the to SoC.
96 */
97typedef enum _dma_request_source
98{
99 kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U,
100 kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U,
101 kDmaRequestMuxLPUART1Tx = 2|0x100U,
102 kDmaRequestMuxLPUART1Rx = 3|0x100U,
103 kDmaRequestMuxLPUART3Tx = 4|0x100U,
104 kDmaRequestMuxLPUART3Rx = 5|0x100U,
105 kDmaRequestMuxLPUART5Tx = 6|0x100U,
106 kDmaRequestMuxLPUART5Rx = 7|0x100U,
107 kDmaRequestMuxLPUART7Tx = 8|0x100U,
108 kDmaRequestMuxLPUART7Rx = 9|0x100U,
109 kDmaRequestMuxCAN3 = 11|0x100U,
110 kDmaRequestMuxLPSPI1Rx = 13|0x100U,
111 kDmaRequestMuxLPSPI1Tx = 14|0x100U,
112 kDmaRequestMuxLPSPI3Rx = 15|0x100U,
113 kDmaRequestMuxLPSPI3Tx = 16|0x100U,
114 kDmaRequestMuxLPI2C1 = 17|0x100U,
115 kDmaRequestMuxLPI2C3 = 18|0x100U,
116 kDmaRequestMuxSai1Rx = 19|0x100U,
117 kDmaRequestMuxSai1Tx = 20|0x100U,
118 kDmaRequestMuxSai2Rx = 21|0x100U,
119 kDmaRequestMuxSai2Tx = 22|0x100U,
120 kDmaRequestMuxADC_ETC = 23|0x100U,
121 kDmaRequestMuxADC1 = 24|0x100U,
122 kDmaRequestMuxACMP1 = 25|0x100U,
123 kDmaRequestMuxACMP3 = 26|0x100U,
124 kDmaRequestMuxFlexSPIRx = 28|0x100U,
125 kDmaRequestMuxFlexSPITx = 29|0x100U,
126 kDmaRequestMuxXBAR1Request0 = 30|0x100U,
127 kDmaRequestMuxXBAR1Request1 = 31|0x100U,
128 kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U,
129 kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U,
130 kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U,
131 kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U,
132 kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U,
133 kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U,
134 kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U,
135 kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U,
136 kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U,
137 kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U,
138 kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U,
139 kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U,
140 kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U,
141 kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U,
142 kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U,
143 kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U,
144 kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U,
145 kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U,
146 kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U,
147 kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U,
148 kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U,
149 kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U,
150 kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U,
151 kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U,
152 kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U,
153 kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U,
154 kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U,
155 kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U,
156 kDmaRequestMuxFlexSPI2Rx = 60|0x100U,
157 kDmaRequestMuxFlexSPI2Tx = 61|0x100U,
158 kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U,
159 kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U,
160 kDmaRequestMuxLPUART2Tx = 66|0x100U,
161 kDmaRequestMuxLPUART2Rx = 67|0x100U,
162 kDmaRequestMuxLPUART4Tx = 68|0x100U,
163 kDmaRequestMuxLPUART4Rx = 69|0x100U,
164 kDmaRequestMuxLPUART6Tx = 70|0x100U,
165 kDmaRequestMuxLPUART6Rx = 71|0x100U,
166 kDmaRequestMuxLPUART8Tx = 72|0x100U,
167 kDmaRequestMuxLPUART8Rx = 73|0x100U,
168 kDmaRequestMuxLPSPI2Rx = 77|0x100U,
169 kDmaRequestMuxLPSPI2Tx = 78|0x100U,
170 kDmaRequestMuxLPSPI4Rx = 79|0x100U,
171 kDmaRequestMuxLPSPI4Tx = 80|0x100U,
172 kDmaRequestMuxLPI2C2 = 81|0x100U,
173 kDmaRequestMuxLPI2C4 = 82|0x100U,
174 kDmaRequestMuxSai3Rx = 83|0x100U,
175 kDmaRequestMuxSai3Tx = 84|0x100U,
176 kDmaRequestMuxSpdifRx = 85|0x100U,
177 kDmaRequestMuxSpdifTx = 86|0x100U,
178 kDmaRequestMuxADC2 = 88|0x100U,
179 kDmaRequestMuxACMP2 = 89|0x100U,
180 kDmaRequestMuxACMP4 = 90|0x100U,
181 kDmaRequestMuxEnetTimer0 = 92|0x100U,
182 kDmaRequestMuxEnetTimer1 = 93|0x100U,
183 kDmaRequestMuxXBAR1Request2 = 94|0x100U,
184 kDmaRequestMuxXBAR1Request3 = 95|0x100U,
185 kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U,
186 kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U,
187 kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U,
188 kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U,
189 kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U,
190 kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U,
191 kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U,
192 kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U,
193 kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U,
194 kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U,
195 kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U,
196 kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U,
197 kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U,
198 kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U,
199 kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U,
200 kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U,
201 kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U,
202 kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U,
203 kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U,
204 kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U,
205 kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U,
206 kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U,
207 kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U,
208 kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U,
209 kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U,
210 kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U,
211 kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U,
212 kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U,
213 kDmaRequestMuxEnet2Timer0 = 124|0x100U,
214 kDmaRequestMuxEnet2Timer1 = 125|0x100U,
215} dma_request_source_t;
216
217/* @} edma_request */
218
219/*
220 * @addtogroup iomuxc_pads_emc_0
221 * @{
222 */
223
224/*******************************************************************************
225 * Definitions
226*******************************************************************************/
227
228/*
229 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
230 *
231 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
232 */
233typedef enum _iomuxc_sw_mux_ctl_pad
234{
235 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U,
236 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U,
237 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U,
238 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U,
239 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U,
240 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U,
241 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U,
242 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U,
243 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U,
244 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U,
245 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U,
246 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U,
247 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U,
248 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U,
249 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U,
250 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U,
251 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U,
252 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U,
253 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U,
254 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U,
255 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U,
256 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U,
257 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U,
258 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U,
259 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U,
260 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U,
261 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U,
262 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U,
263 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U,
264 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U,
265 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U,
266 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U,
267 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U,
268 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U,
269 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U,
270 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U,
271 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U,
272 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U,
273 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U,
274 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U,
275 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U,
276 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U,
277 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U,
278 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U,
279 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U,
280 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U,
281 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U,
282 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U,
283 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U,
284 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U,
285 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U,
286 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U,
287 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U,
288 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U,
289 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U,
290 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U,
291 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U,
292 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U,
293 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U,
294 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U,
295 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U,
296 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U,
297 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U,
298 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U,
299 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U,
300 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U,
301 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U,
302 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U,
303 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U,
304 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U,
305 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U,
306 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U,
307 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U,
308 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U,
309 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U,
310 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U,
311 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U,
312 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U,
313 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U,
314 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U,
315 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U,
316 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U,
317 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U,
318 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U,
319 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U,
320 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U,
321 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U,
322 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U,
323 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U,
324 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U,
325 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U,
326 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U,
327 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U,
328 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U,
329 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U,
330 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U,
331 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U,
332 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U,
333 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U,
334 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U,
335 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U,
336 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U,
337 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U,
338 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U,
339 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U,
340 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U,
341 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U,
342 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U,
343 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U,
344 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U,
345 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U,
346 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U,
347 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U,
348 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U,
349 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U,
350 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U,
351 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U,
352 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U,
353 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U,
354 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U,
355 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U,
356 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U,
357 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U,
358 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U,
359} iomuxc_sw_mux_ctl_pad_t;
360
361/* @} iomuxc_pads_emc_0 */
362
363/*
364 * @addtogroup iomuxc_pads_spi_0
365 * @{
366 */
367
368/*******************************************************************************
369 * Definitions
370*******************************************************************************/
371
372/*
373 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD_1
374 *
375 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD_1 collections.
376 */
377typedef enum _iomuxc_sw_mux_ctl_pad_1
378{
379 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00 = 0U,
380 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01 = 1U,
381 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02 = 2U,
382 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03 = 3U,
383 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04 = 4U,
384 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05 = 5U,
385 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06 = 6U,
386 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07 = 7U,
387 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08 = 8U,
388 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09 = 9U,
389 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10 = 10U,
390 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11 = 11U,
391 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12 = 12U,
392 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13 = 13U,
393 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00 = 14U,
394 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01 = 15U,
395 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02 = 16U,
396 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03 = 17U,
397 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04 = 18U,
398 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05 = 19U,
399 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06 = 20U,
400 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07 = 21U,
401} iomuxc_sw_mux_ctl_pad_1_t;
402
403/* @} iomuxc_pads_spi_0 */
404
405/*
406 * @addtogroup iomuxc_pads_emc_1
407 * @{
408 */
409
410/*******************************************************************************
411 * Definitions
412*******************************************************************************/
413
414/*
415 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
416 *
417 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
418 */
419typedef enum _iomuxc_sw_pad_ctl_pad
420{
421 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U,
422 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U,
423 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U,
424 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U,
425 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U,
426 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U,
427 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U,
428 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U,
429 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U,
430 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U,
431 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U,
432 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U,
433 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U,
434 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U,
435 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U,
436 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U,
437 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U,
438 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U,
439 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U,
440 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U,
441 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U,
442 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U,
443 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U,
444 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U,
445 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U,
446 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U,
447 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U,
448 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U,
449 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U,
450 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U,
451 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U,
452 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U,
453 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U,
454 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U,
455 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U,
456 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U,
457 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U,
458 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U,
459 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U,
460 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U,
461 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U,
462 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U,
463 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U,
464 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U,
465 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U,
466 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U,
467 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U,
468 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U,
469 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U,
470 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U,
471 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U,
472 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U,
473 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U,
474 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U,
475 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U,
476 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U,
477 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U,
478 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U,
479 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U,
480 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U,
481 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U,
482 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U,
483 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U,
484 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U,
485 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U,
486 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U,
487 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U,
488 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U,
489 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U,
490 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U,
491 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U,
492 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U,
493 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U,
494 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U,
495 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U,
496 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U,
497 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U,
498 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U,
499 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U,
500 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U,
501 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U,
502 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U,
503 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U,
504 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U,
505 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U,
506 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U,
507 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U,
508 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U,
509 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U,
510 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U,
511 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U,
512 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U,
513 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U,
514 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U,
515 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U,
516 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U,
517 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U,
518 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U,
519 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U,
520 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U,
521 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U,
522 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U,
523 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U,
524 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U,
525 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U,
526 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U,
527 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U,
528 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U,
529 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U,
530 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U,
531 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U,
532 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U,
533 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U,
534 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U,
535 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U,
536 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U,
537 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U,
538 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U,
539 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U,
540 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U,
541 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U,
542 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U,
543 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U,
544 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U,
545} iomuxc_sw_pad_ctl_pad_t;
546
547/* @} iomuxc_pads_emc_1 */
548
549/*
550 * @addtogroup iomuxc_pads_spi_1
551 * @{
552 */
553
554/*******************************************************************************
555 * Definitions
556*******************************************************************************/
557
558/*
559 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD_1
560 *
561 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD_1 collections.
562 */
563typedef enum _iomuxc_sw_pad_ctl_pad_1
564{
565 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00 = 0U,
566 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01 = 1U,
567 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02 = 2U,
568 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03 = 3U,
569 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04 = 4U,
570 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05 = 5U,
571 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06 = 6U,
572 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07 = 7U,
573 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08 = 8U,
574 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09 = 9U,
575 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10 = 10U,
576 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11 = 11U,
577 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12 = 12U,
578 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13 = 13U,
579 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00 = 14U,
580 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01 = 15U,
581 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02 = 16U,
582 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03 = 17U,
583 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04 = 18U,
584 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05 = 19U,
585 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06 = 20U,
586 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07 = 21U,
587} iomuxc_sw_pad_ctl_pad_1_t;
588
589/* @} iomuxc_pads_spi_1 */
590
591/*
592 * @brief Enumeration for the IOMUXC select input
593 *
594 * Defines the enumeration for the IOMUXC select input collections.
595 */
596typedef enum _iomuxc_select_input
597{
598 kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U,
599 kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U,
600 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U,
601 kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U,
602 kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U,
603 kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U,
604 kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U,
605 kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U,
606 kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U,
607 kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U,
608 kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U,
609 kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U,
610 kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U,
611 kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U,
612 kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U,
613 kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U,
614 kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U,
615 kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U,
616 kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U,
617 kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U,
618 kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U,
619 kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U,
620 kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U,
621 kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U,
622 kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U,
623 kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U,
624 kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U,
625 kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U,
626 kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U,
627 kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U,
628 kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U,
629 kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U,
630 kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U,
631 kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U,
632 kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U,
633 kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U,
634 kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U,
635 kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U,
636 kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U,
637 kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U,
638 kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U,
639 kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U,
640 kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U,
641 kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U,
642 kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U,
643 kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U,
644 kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U,
645 kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U,
646 kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U,
647 kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U,
648 kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U,
649 kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U,
650 kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U,
651 kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U,
652 kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U,
653 kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U,
654 kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U,
655 kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U,
656 kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U,
657 kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U,
658 kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U,
659 kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U,
660 kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U,
661 kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U,
662 kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U,
663 kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U,
664 kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U,
665 kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U,
666 kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U,
667 kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U,
668 kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U,
669 kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U,
670 kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U,
671 kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U,
672 kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U,
673 kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U,
674 kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U,
675 kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U,
676 kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U,
677 kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U,
678 kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U,
679 kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U,
680 kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U,
681 kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U,
682 kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U,
683 kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U,
684 kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U,
685 kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U,
686 kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U,
687 kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U,
688 kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U,
689 kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U,
690 kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U,
691 kIOMUXC_NMI_SELECT_INPUT = 93U,
692 kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U,
693 kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U,
694 kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U,
695 kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U,
696 kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U,
697 kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U,
698 kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U,
699 kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U,
700 kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U,
701 kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U,
702 kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U,
703 kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U,
704 kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U,
705 kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U,
706 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U,
707 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U,
708 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U,
709 kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U,
710 kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U,
711 kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U,
712 kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U,
713 kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U,
714 kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U,
715 kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U,
716 kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U,
717 kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U,
718 kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U,
719 kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U,
720 kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U,
721 kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U,
722 kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U,
723 kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U,
724 kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U,
725 kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U,
726 kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U,
727 kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U,
728 kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U,
729 kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U,
730 kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U,
731 kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U,
732 kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U,
733 kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U,
734 kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U,
735 kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U,
736 kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U,
737 kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U,
738 kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U,
739 kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U,
740 kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U,
741 kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U,
742 kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U,
743 kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U,
744 kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U,
745 kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U,
746 kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U,
747 kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U,
748 kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U,
749 kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U,
750 kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U,
751 kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U,
752} iomuxc_select_input_t;
753
754/*
755 * @brief Enumeration for the IOMUXC select input
756 *
757 * Defines the enumeration for the IOMUXC select input collections.
758 */
759typedef enum _iomuxc_select_input_1
760{
761 kIOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT = 0U,
762 kIOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT = 1U,
763 kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 = 2U,
764 kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 = 3U,
765 kIOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT = 4U,
766 kIOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT = 5U,
767 kIOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 = 6U,
768 kIOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT = 7U,
769 kIOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT = 8U,
770 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 9U,
771 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 10U,
772 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 11U,
773 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 12U,
774 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT = 13U,
775 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT = 14U,
776 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT = 15U,
777 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT = 16U,
778 kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT = 17U,
779 kIOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT = 18U,
780 kIOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT = 19U,
781 kIOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT = 20U,
782 kIOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT = 21U,
783 kIOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT = 22U,
784 kIOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT = 23U,
785 kIOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT = 24U,
786 kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 25U,
787 kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 26U,
788 kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 27U,
789 kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 28U,
790 kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 29U,
791 kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 30U,
792 kIOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT = 31U,
793 kIOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT = 32U,
794} iomuxc_select_input_1_t;
795
796/* @b _xbar_input_signal */
797typedef enum _xbar_input_signal
798{
799 kXBARA1_InputLogicLow = 0|0x100U,
800 kXBARA1_InputLogicHigh = 1|0x100U,
801 kXBARA1_InputIomuxXbarIn02 = 2|0x100U,
802 kXBARA1_InputIomuxXbarIn03 = 3|0x100U,
803 kXBARA1_InputIomuxXbarInout04 = 4|0x100U,
804 kXBARA1_InputIomuxXbarInout05 = 5|0x100U,
805 kXBARA1_InputIomuxXbarInout06 = 6|0x100U,
806 kXBARA1_InputIomuxXbarInout07 = 7|0x100U,
807 kXBARA1_InputIomuxXbarInout08 = 8|0x100U,
808 kXBARA1_InputIomuxXbarInout09 = 9|0x100U,
809 kXBARA1_InputIomuxXbarInout10 = 10|0x100U,
810 kXBARA1_InputIomuxXbarInout11 = 11|0x100U,
811 kXBARA1_InputIomuxXbarInout12 = 12|0x100U,
812 kXBARA1_InputIomuxXbarInout13 = 13|0x100U,
813 kXBARA1_InputIomuxXbarInout14 = 14|0x100U,
814 kXBARA1_InputIomuxXbarInout15 = 15|0x100U,
815 kXBARA1_InputIomuxXbarInout16 = 16|0x100U,
816 kXBARA1_InputIomuxXbarInout17 = 17|0x100U,
817 kXBARA1_InputIomuxXbarInout18 = 18|0x100U,
818 kXBARA1_InputIomuxXbarInout19 = 19|0x100U,
819 kXBARA1_InputIomuxXbarIn20 = 20|0x100U,
820 kXBARA1_InputIomuxXbarIn21 = 21|0x100U,
821 kXBARA1_InputIomuxXbarIn22 = 22|0x100U,
822 kXBARA1_InputIomuxXbarIn23 = 23|0x100U,
823 kXBARA1_InputIomuxXbarIn24 = 24|0x100U,
824 kXBARA1_InputIomuxXbarIn25 = 25|0x100U,
825 kXBARA1_InputAcmp1Out = 26|0x100U,
826 kXBARA1_InputAcmp2Out = 27|0x100U,
827 kXBARA1_InputAcmp3Out = 28|0x100U,
828 kXBARA1_InputAcmp4Out = 29|0x100U,
829 kXBARA1_InputRESERVED30 = 30|0x100U,
830 kXBARA1_InputRESERVED31 = 31|0x100U,
831 kXBARA1_InputQtimer3Tmr0Output = 32|0x100U,
832 kXBARA1_InputQtimer3Tmr1Output = 33|0x100U,
833 kXBARA1_InputQtimer3Tmr2Output = 34|0x100U,
834 kXBARA1_InputQtimer3Tmr3Output = 35|0x100U,
835 kXBARA1_InputQtimer4Tmr0Output = 36|0x100U,
836 kXBARA1_InputQtimer4Tmr1Output = 37|0x100U,
837 kXBARA1_InputQtimer4Tmr2Output = 38|0x100U,
838 kXBARA1_InputQtimer4Tmr3Output = 39|0x100U,
839 kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U,
840 kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U,
841 kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U,
842 kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U,
843 kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U,
844 kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U,
845 kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U,
846 kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U,
847 kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U,
848 kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U,
849 kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U,
850 kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U,
851 kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U,
852 kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U,
853 kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U,
854 kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U,
855 kXBARA1_InputPitTrigger0 = 56|0x100U,
856 kXBARA1_InputPitTrigger1 = 57|0x100U,
857 kXBARA1_InputPitTrigger2 = 58|0x100U,
858 kXBARA1_InputPitTrigger3 = 59|0x100U,
859 kXBARA1_InputQdc1PosMatch = 60|0x100U,
860 kXBARA1_InputQdc2PosMatch = 61|0x100U,
861 kXBARA1_InputQdc3PosMatch = 62|0x100U,
862 kXBARA1_InputQdc4PosMatch = 63|0x100U,
863 kXBARA1_InputDmaDone0 = 64|0x100U,
864 kXBARA1_InputDmaDone1 = 65|0x100U,
865 kXBARA1_InputDmaDone2 = 66|0x100U,
866 kXBARA1_InputDmaDone3 = 67|0x100U,
867 kXBARA1_InputDmaDone4 = 68|0x100U,
868 kXBARA1_InputDmaDone5 = 69|0x100U,
869 kXBARA1_InputDmaDone6 = 70|0x100U,
870 kXBARA1_InputDmaDone7 = 71|0x100U,
871 kXBARA1_InputAoi1Out0 = 72|0x100U,
872 kXBARA1_InputAoi1Out1 = 73|0x100U,
873 kXBARA1_InputAoi1Out2 = 74|0x100U,
874 kXBARA1_InputAoi1Out3 = 75|0x100U,
875 kXBARA1_InputAoi2Out0 = 76|0x100U,
876 kXBARA1_InputAoi2Out1 = 77|0x100U,
877 kXBARA1_InputAoi2Out2 = 78|0x100U,
878 kXBARA1_InputAoi2Out3 = 79|0x100U,
879 kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U,
880 kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U,
881 kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U,
882 kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U,
883 kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U,
884 kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U,
885 kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U,
886 kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U,
887 kXBARB2_InputLogicLow = 0|0x200U,
888 kXBARB2_InputLogicHigh = 1|0x200U,
889 kXBARB2_InputRESERVED2 = 2|0x200U,
890 kXBARB2_InputRESERVED3 = 3|0x200U,
891 kXBARB2_InputRESERVED4 = 4|0x200U,
892 kXBARB2_InputRESERVED5 = 5|0x200U,
893 kXBARB2_InputAcmp1Out = 6|0x200U,
894 kXBARB2_InputAcmp2Out = 7|0x200U,
895 kXBARB2_InputAcmp3Out = 8|0x200U,
896 kXBARB2_InputAcmp4Out = 9|0x200U,
897 kXBARB2_InputRESERVED10 = 10|0x200U,
898 kXBARB2_InputRESERVED11 = 11|0x200U,
899 kXBARB2_InputQtimer3Tmr0Output = 12|0x200U,
900 kXBARB2_InputQtimer3Tmr1Output = 13|0x200U,
901 kXBARB2_InputQtimer3Tmr2Output = 14|0x200U,
902 kXBARB2_InputQtimer3Tmr3Output = 15|0x200U,
903 kXBARB2_InputQtimer4Tmr0Output = 16|0x200U,
904 kXBARB2_InputQtimer4Tmr1Output = 17|0x200U,
905 kXBARB2_InputQtimer4Tmr2Output = 18|0x200U,
906 kXBARB2_InputQtimer4Tmr3Output = 19|0x200U,
907 kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U,
908 kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U,
909 kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U,
910 kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U,
911 kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U,
912 kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U,
913 kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U,
914 kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U,
915 kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U,
916 kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U,
917 kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U,
918 kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U,
919 kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U,
920 kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U,
921 kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U,
922 kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U,
923 kXBARB2_InputPitTrigger0 = 36|0x200U,
924 kXBARB2_InputPitTrigger1 = 37|0x200U,
925 kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U,
926 kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U,
927 kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U,
928 kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U,
929 kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U,
930 kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U,
931 kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U,
932 kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U,
933 kXBARB2_InputQdc1PosMatch = 46|0x200U,
934 kXBARB2_InputQdc2PosMatch = 47|0x200U,
935 kXBARB2_InputQdc3PosMatch = 48|0x200U,
936 kXBARB2_InputQdc4PosMatch = 49|0x200U,
937 kXBARB2_InputDmaDone0 = 50|0x200U,
938 kXBARB2_InputDmaDone1 = 51|0x200U,
939 kXBARB2_InputDmaDone2 = 52|0x200U,
940 kXBARB2_InputDmaDone3 = 53|0x200U,
941 kXBARB2_InputDmaDone4 = 54|0x200U,
942 kXBARB2_InputDmaDone5 = 55|0x200U,
943 kXBARB2_InputDmaDone6 = 56|0x200U,
944 kXBARB2_InputDmaDone7 = 57|0x200U,
945 kXBARB3_InputLogicLow = 0|0x300U,
946 kXBARB3_InputLogicHigh = 1|0x300U,
947 kXBARB3_InputRESERVED2 = 2|0x300U,
948 kXBARB3_InputRESERVED3 = 3|0x300U,
949 kXBARB3_InputRESERVED4 = 4|0x300U,
950 kXBARB3_InputRESERVED5 = 5|0x300U,
951 kXBARB3_InputAcmp1Out = 6|0x300U,
952 kXBARB3_InputAcmp2Out = 7|0x300U,
953 kXBARB3_InputAcmp3Out = 8|0x300U,
954 kXBARB3_InputAcmp4Out = 9|0x300U,
955 kXBARB3_InputRESERVED10 = 10|0x300U,
956 kXBARB3_InputRESERVED11 = 11|0x300U,
957 kXBARB3_InputQtimer3Tmr0Output = 12|0x300U,
958 kXBARB3_InputQtimer3Tmr1Output = 13|0x300U,
959 kXBARB3_InputQtimer3Tmr2Output = 14|0x300U,
960 kXBARB3_InputQtimer3Tmr3Output = 15|0x300U,
961 kXBARB3_InputQtimer4Tmr0Output = 16|0x300U,
962 kXBARB3_InputQtimer4Tmr1Output = 17|0x300U,
963 kXBARB3_InputQtimer4Tmr2Output = 18|0x300U,
964 kXBARB3_InputQtimer4Tmr3Output = 19|0x300U,
965 kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U,
966 kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U,
967 kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U,
968 kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U,
969 kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U,
970 kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U,
971 kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U,
972 kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U,
973 kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U,
974 kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U,
975 kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U,
976 kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U,
977 kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U,
978 kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U,
979 kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U,
980 kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U,
981 kXBARB3_InputPitTrigger0 = 36|0x300U,
982 kXBARB3_InputPitTrigger1 = 37|0x300U,
983 kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U,
984 kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U,
985 kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U,
986 kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U,
987 kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U,
988 kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U,
989 kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U,
990 kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U,
991 kXBARB3_InputQdc1PosMatch = 46|0x300U,
992 kXBARB3_InputQdc2PosMatch = 47|0x300U,
993 kXBARB3_InputQdc3PosMatch = 48|0x300U,
994 kXBARB3_InputQdc4PosMatch = 49|0x300U,
995 kXBARB3_InputDmaDone0 = 50|0x300U,
996 kXBARB3_InputDmaDone1 = 51|0x300U,
997 kXBARB3_InputDmaDone2 = 52|0x300U,
998 kXBARB3_InputDmaDone3 = 53|0x300U,
999 kXBARB3_InputDmaDone4 = 54|0x300U,
1000 kXBARB3_InputDmaDone5 = 55|0x300U,
1001 kXBARB3_InputDmaDone6 = 56|0x300U,
1002 kXBARB3_InputDmaDone7 = 57|0x300U,
1003} xbar_input_signal_t;
1004
1005/* @b _xbar_output_signal */
1006typedef enum _xbar_output_signal
1007{
1008 kXBARA1_OutputDmaChMuxReq30 = 0|0x100U,
1009 kXBARA1_OutputDmaChMuxReq31 = 1|0x100U,
1010 kXBARA1_OutputDmaChMuxReq94 = 2|0x100U,
1011 kXBARA1_OutputDmaChMuxReq95 = 3|0x100U,
1012 kXBARA1_OutputIomuxXbarInout04 = 4|0x100U,
1013 kXBARA1_OutputIomuxXbarInout05 = 5|0x100U,
1014 kXBARA1_OutputIomuxXbarInout06 = 6|0x100U,
1015 kXBARA1_OutputIomuxXbarInout07 = 7|0x100U,
1016 kXBARA1_OutputIomuxXbarInout08 = 8|0x100U,
1017 kXBARA1_OutputIomuxXbarInout09 = 9|0x100U,
1018 kXBARA1_OutputIomuxXbarInout10 = 10|0x100U,
1019 kXBARA1_OutputIomuxXbarInout11 = 11|0x100U,
1020 kXBARA1_OutputIomuxXbarInout12 = 12|0x100U,
1021 kXBARA1_OutputIomuxXbarInout13 = 13|0x100U,
1022 kXBARA1_OutputIomuxXbarInout14 = 14|0x100U,
1023 kXBARA1_OutputIomuxXbarInout15 = 15|0x100U,
1024 kXBARA1_OutputIomuxXbarInout16 = 16|0x100U,
1025 kXBARA1_OutputIomuxXbarInout17 = 17|0x100U,
1026 kXBARA1_OutputIomuxXbarInout18 = 18|0x100U,
1027 kXBARA1_OutputIomuxXbarInout19 = 19|0x100U,
1028 kXBARA1_OutputAcmp1Sample = 20|0x100U,
1029 kXBARA1_OutputAcmp2Sample = 21|0x100U,
1030 kXBARA1_OutputAcmp3Sample = 22|0x100U,
1031 kXBARA1_OutputAcmp4Sample = 23|0x100U,
1032 kXBARA1_OutputRESERVED24 = 24|0x100U,
1033 kXBARA1_OutputRESERVED25 = 25|0x100U,
1034 kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U,
1035 kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U,
1036 kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U,
1037 kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U,
1038 kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U,
1039 kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U,
1040 kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U,
1041 kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U,
1042 kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U,
1043 kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U,
1044 kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U,
1045 kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U,
1046 kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U,
1047 kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U,
1048 kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U,
1049 kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U,
1050 kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U,
1051 kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U,
1052 kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U,
1053 kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U,
1054 kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U,
1055 kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U,
1056 kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U,
1057 kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U,
1058 kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U,
1059 kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U,
1060 kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U,
1061 kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U,
1062 kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U,
1063 kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U,
1064 kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U,
1065 kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U,
1066 kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U,
1067 kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U,
1068 kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U,
1069 kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U,
1070 kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U,
1071 kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U,
1072 kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U,
1073 kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U,
1074 kXBARA1_OutputQdc1PhaseAInput = 66|0x100U,
1075 kXBARA1_OutputQdc1PhaseBInput = 67|0x100U,
1076 kXBARA1_OutputQdc1Index = 68|0x100U,
1077 kXBARA1_OutputQdc1Home = 69|0x100U,
1078 kXBARA1_OutputQdc1Trigger = 70|0x100U,
1079 kXBARA1_OutputQdc2PhaseAInput = 71|0x100U,
1080 kXBARA1_OutputQdc2PhaseBInput = 72|0x100U,
1081 kXBARA1_OutputQdc2Index = 73|0x100U,
1082 kXBARA1_OutputQdc2Home = 74|0x100U,
1083 kXBARA1_OutputQdc2Trigger = 75|0x100U,
1084 kXBARA1_OutputQdc3PhaseAInput = 76|0x100U,
1085 kXBARA1_OutputQdc3PhaseBInput = 77|0x100U,
1086 kXBARA1_OutputQdc3Index = 78|0x100U,
1087 kXBARA1_OutputQdc3Home = 79|0x100U,
1088 kXBARA1_OutputQdc3Trigger = 80|0x100U,
1089 kXBARA1_OutputQdc4PhaseAInput = 81|0x100U,
1090 kXBARA1_OutputQdc4PhaseBInput = 82|0x100U,
1091 kXBARA1_OutputQdc4Index = 83|0x100U,
1092 kXBARA1_OutputQdc4Home = 84|0x100U,
1093 kXBARA1_OutputQdc4Trigger = 85|0x100U,
1094 kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U,
1095 kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U,
1096 kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U,
1097 kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U,
1098 kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U,
1099 kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U,
1100 kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U,
1101 kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U,
1102 kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U,
1103 kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U,
1104 kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U,
1105 kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U,
1106 kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U,
1107 kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U,
1108 kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U,
1109 kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U,
1110 kXBARA1_OutputEwmEwmIn = 102|0x100U,
1111 kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U,
1112 kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U,
1113 kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U,
1114 kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U,
1115 kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U,
1116 kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U,
1117 kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U,
1118 kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U,
1119 kXBARA1_OutputLpi2c1TrgInput = 111|0x100U,
1120 kXBARA1_OutputLpi2c2TrgInput = 112|0x100U,
1121 kXBARA1_OutputLpi2c3TrgInput = 113|0x100U,
1122 kXBARA1_OutputLpi2c4TrgInput = 114|0x100U,
1123 kXBARA1_OutputLpspi1TrgInput = 115|0x100U,
1124 kXBARA1_OutputLpspi2TrgInput = 116|0x100U,
1125 kXBARA1_OutputLpspi3TrgInput = 117|0x100U,
1126 kXBARA1_OutputLpspi4TrgInput = 118|0x100U,
1127 kXBARA1_OutputLpuart1TrgInput = 119|0x100U,
1128 kXBARA1_OutputLpuart2TrgInput = 120|0x100U,
1129 kXBARA1_OutputLpuart3TrgInput = 121|0x100U,
1130 kXBARA1_OutputLpuart4TrgInput = 122|0x100U,
1131 kXBARA1_OutputLpuart5TrgInput = 123|0x100U,
1132 kXBARA1_OutputLpuart6TrgInput = 124|0x100U,
1133 kXBARA1_OutputLpuart7TrgInput = 125|0x100U,
1134 kXBARA1_OutputLpuart8TrgInput = 126|0x100U,
1135 kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U,
1136 kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U,
1137 kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U,
1138 kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U,
1139 kXBARB2_OutputAoi1In00 = 0|0x200U,
1140 kXBARB2_OutputAoi1In01 = 1|0x200U,
1141 kXBARB2_OutputAoi1In02 = 2|0x200U,
1142 kXBARB2_OutputAoi1In03 = 3|0x200U,
1143 kXBARB2_OutputAoi1In04 = 4|0x200U,
1144 kXBARB2_OutputAoi1In05 = 5|0x200U,
1145 kXBARB2_OutputAoi1In06 = 6|0x200U,
1146 kXBARB2_OutputAoi1In07 = 7|0x200U,
1147 kXBARB2_OutputAoi1In08 = 8|0x200U,
1148 kXBARB2_OutputAoi1In09 = 9|0x200U,
1149 kXBARB2_OutputAoi1In10 = 10|0x200U,
1150 kXBARB2_OutputAoi1In11 = 11|0x200U,
1151 kXBARB2_OutputAoi1In12 = 12|0x200U,
1152 kXBARB2_OutputAoi1In13 = 13|0x200U,
1153 kXBARB2_OutputAoi1In14 = 14|0x200U,
1154 kXBARB2_OutputAoi1In15 = 15|0x200U,
1155 kXBARB3_OutputAoi2In00 = 0|0x300U,
1156 kXBARB3_OutputAoi2In01 = 1|0x300U,
1157 kXBARB3_OutputAoi2In02 = 2|0x300U,
1158 kXBARB3_OutputAoi2In03 = 3|0x300U,
1159 kXBARB3_OutputAoi2In04 = 4|0x300U,
1160 kXBARB3_OutputAoi2In05 = 5|0x300U,
1161 kXBARB3_OutputAoi2In06 = 6|0x300U,
1162 kXBARB3_OutputAoi2In07 = 7|0x300U,
1163 kXBARB3_OutputAoi2In08 = 8|0x300U,
1164 kXBARB3_OutputAoi2In09 = 9|0x300U,
1165 kXBARB3_OutputAoi2In10 = 10|0x300U,
1166 kXBARB3_OutputAoi2In11 = 11|0x300U,
1167 kXBARB3_OutputAoi2In12 = 12|0x300U,
1168 kXBARB3_OutputAoi2In13 = 13|0x300U,
1169 kXBARB3_OutputAoi2In14 = 14|0x300U,
1170 kXBARB3_OutputAoi2In15 = 15|0x300U,
1171} xbar_output_signal_t;
1172
1173
1174/* @} end of group Mapping_Information */
1175
1176
1177/* ----------------------------------------------------------------------------
1178 -- Device Peripheral Access Layer
1179 ---------------------------------------------------------------------------- */
1180
1181/*
1182 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
1183 * @{
1184 */
1185
1186
1187/* Start of section using anonymous unions */
1188
1189#if defined(__ARMCC_VERSION)
1190 #if (__ARMCC_VERSION >= 6010050)
1191 #pragma clang diagnostic push
1192 #else
1193 #pragma push
1194 #pragma anon_unions
1195 #endif
1196#elif defined(__CWCC__)
1197 #pragma push
1198 #pragma cpp_extensions on
1199#elif defined(__GNUC__)
1200 /* anonymous unions are enabled by default */
1201#elif defined(__IAR_SYSTEMS_ICC__)
1202 #pragma language=extended
1203#else
1204 #error Not supported compiler type
1205#endif
1206
1207/* ----------------------------------------------------------------------------
1208 -- ADC Peripheral Access Layer
1209 ---------------------------------------------------------------------------- */
1210
1211/*
1212 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
1213 * @{
1214 */
1215
1216/* ADC - Register Layout Typedef */
1217typedef struct {
1218 __IO uint32_t HC[8];
1219 __I uint32_t HS;
1220 __I uint32_t R[8];
1221 __IO uint32_t CFG;
1222 __IO uint32_t GC;
1223 __IO uint32_t GS;
1224 __IO uint32_t CV;
1225 __IO uint32_t OFS;
1226 __IO uint32_t CAL;
1227} ADC_Type;
1228
1229/* ----------------------------------------------------------------------------
1230 -- ADC Register Masks
1231 ---------------------------------------------------------------------------- */
1232
1233/*
1234 * @addtogroup ADC_Register_Masks ADC Register Masks
1235 * @{
1236 */
1237
1238/* @name HC - Control register for hardware triggers */
1239/* @{ */
1240#define ADC_HC_ADCH_MASK (0x1FU)
1241#define ADC_HC_ADCH_SHIFT (0U)
1242/* ADCH - Input Channel Select
1243 * 0b10000..External channel selection from ADC_ETC
1244 * 0b11000..Reserved.
1245 * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
1246 * 0b11010..Reserved.
1247 * 0b11011..Reserved.
1248 * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
1249 */
1250#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1251#define ADC_HC_AIEN_MASK (0x80U)
1252#define ADC_HC_AIEN_SHIFT (7U)
1253/* AIEN - Conversion Complete Interrupt Enable/Disable Control
1254 * 0b1..Conversion complete interrupt enabled
1255 * 0b0..Conversion complete interrupt disabled
1256 */
1257#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1258/* @} HC */
1259
1260/* The count of ADC_HC */
1261#define ADC_HC_COUNT (8U)
1262
1263/* @name HS - Status register for HW triggers */
1264/* @{ */
1265#define ADC_HS_COCO0_MASK (0x1U)
1266#define ADC_HS_COCO0_SHIFT (0U)
1267#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1268/* @} HS */
1269
1270/* @name R - Data result register for HW triggers */
1271/* @{ */
1272#define ADC_R_CDATA_MASK (0xFFFU)
1273#define ADC_R_CDATA_SHIFT (0U)
1274#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1275/* @} R */
1276
1277/* The count of ADC_R */
1278#define ADC_R_COUNT (8U)
1279
1280/* @name CFG - Configuration register */
1281/* @{ */
1282#define ADC_CFG_ADICLK_MASK (0x3U)
1283#define ADC_CFG_ADICLK_SHIFT (0U)
1284/* ADICLK - Input Clock Select
1285 * 0b00..IPG clock
1286 * 0b01..IPG clock divided by 2
1287 * 0b10..Reserved
1288 * 0b11..Asynchronous clock (ADACK)
1289 */
1290#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1291#define ADC_CFG_MODE_MASK (0xCU)
1292#define ADC_CFG_MODE_SHIFT (2U)
1293/* MODE - Conversion Mode Selection
1294 * 0b00..8-bit conversion
1295 * 0b01..10-bit conversion
1296 * 0b10..12-bit conversion
1297 * 0b11..Reserved
1298 */
1299#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1300#define ADC_CFG_ADLSMP_MASK (0x10U)
1301#define ADC_CFG_ADLSMP_SHIFT (4U)
1302/* ADLSMP - Long Sample Time Configuration
1303 * 0b0..Short sample mode.
1304 * 0b1..Long sample mode.
1305 */
1306#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1307#define ADC_CFG_ADIV_MASK (0x60U)
1308#define ADC_CFG_ADIV_SHIFT (5U)
1309/* ADIV - Clock Divide Select
1310 * 0b00..Input clock
1311 * 0b01..Input clock / 2
1312 * 0b10..Input clock / 4
1313 * 0b11..Input clock / 8
1314 */
1315#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1316#define ADC_CFG_ADLPC_MASK (0x80U)
1317#define ADC_CFG_ADLPC_SHIFT (7U)
1318/* ADLPC - Low-Power Configuration
1319 * 0b0..ADC hard block not in low power mode.
1320 * 0b1..ADC hard block in low power mode.
1321 */
1322#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1323#define ADC_CFG_ADSTS_MASK (0x300U)
1324#define ADC_CFG_ADSTS_SHIFT (8U)
1325/* ADSTS
1326 * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b
1327 * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b
1328 * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b
1329 * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b
1330 */
1331#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1332#define ADC_CFG_ADHSC_MASK (0x400U)
1333#define ADC_CFG_ADHSC_SHIFT (10U)
1334/* ADHSC - High Speed Configuration
1335 * 0b0..Normal conversion selected.
1336 * 0b1..High speed conversion selected.
1337 */
1338#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1339#define ADC_CFG_REFSEL_MASK (0x1800U)
1340#define ADC_CFG_REFSEL_SHIFT (11U)
1341/* REFSEL - Voltage Reference Selection
1342 * 0b00..Selects VREFH/VREFL as reference voltage.
1343 * 0b01..Reserved
1344 * 0b10..Reserved
1345 * 0b11..Reserved
1346 */
1347#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1348#define ADC_CFG_ADTRG_MASK (0x2000U)
1349#define ADC_CFG_ADTRG_SHIFT (13U)
1350/* ADTRG - Conversion Trigger Select
1351 * 0b0..Software trigger selected
1352 * 0b1..Hardware trigger selected
1353 */
1354#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1355#define ADC_CFG_AVGS_MASK (0xC000U)
1356#define ADC_CFG_AVGS_SHIFT (14U)
1357/* AVGS - Hardware Average select
1358 * 0b00..4 samples averaged
1359 * 0b01..8 samples averaged
1360 * 0b10..16 samples averaged
1361 * 0b11..32 samples averaged
1362 */
1363#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1364#define ADC_CFG_OVWREN_MASK (0x10000U)
1365#define ADC_CFG_OVWREN_SHIFT (16U)
1366/* OVWREN - Data Overwrite Enable
1367 * 0b1..Enable the overwriting.
1368 * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
1369 */
1370#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1371/* @} CFG */
1372
1373/* @name GC - General control register */
1374/* @{ */
1375#define ADC_GC_ADACKEN_MASK (0x1U)
1376#define ADC_GC_ADACKEN_SHIFT (0U)
1377/* ADACKEN - Asynchronous clock output enable
1378 * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
1379 * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
1380 */
1381#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1382#define ADC_GC_DMAEN_MASK (0x2U)
1383#define ADC_GC_DMAEN_SHIFT (1U)
1384/* DMAEN - DMA Enable
1385 * 0b0..DMA disabled (default)
1386 * 0b1..DMA enabled
1387 */
1388#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1389#define ADC_GC_ACREN_MASK (0x4U)
1390#define ADC_GC_ACREN_SHIFT (2U)
1391/* ACREN - Compare Function Range Enable
1392 * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
1393 * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
1394 */
1395#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1396#define ADC_GC_ACFGT_MASK (0x8U)
1397#define ADC_GC_ACFGT_SHIFT (3U)
1398/* ACFGT - Compare Function Greater Than Enable
1399 * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
1400 * functionality based on the values placed in the ADC_CV register.
1401 * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
1402 * functionality based on the values placed in the ADC_CV registers.
1403 */
1404#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1405#define ADC_GC_ACFE_MASK (0x10U)
1406#define ADC_GC_ACFE_SHIFT (4U)
1407/* ACFE - Compare Function Enable
1408 * 0b0..Compare function disabled
1409 * 0b1..Compare function enabled
1410 */
1411#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1412#define ADC_GC_AVGE_MASK (0x20U)
1413#define ADC_GC_AVGE_SHIFT (5U)
1414/* AVGE - Hardware average enable
1415 * 0b0..Hardware average function disabled
1416 * 0b1..Hardware average function enabled
1417 */
1418#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1419#define ADC_GC_ADCO_MASK (0x40U)
1420#define ADC_GC_ADCO_SHIFT (6U)
1421/* ADCO - Continuous Conversion Enable
1422 * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1423 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1424 */
1425#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1426#define ADC_GC_CAL_MASK (0x80U)
1427#define ADC_GC_CAL_SHIFT (7U)
1428#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1429/* @} GC */
1430
1431/* @name GS - General status register */
1432/* @{ */
1433#define ADC_GS_ADACT_MASK (0x1U)
1434#define ADC_GS_ADACT_SHIFT (0U)
1435/* ADACT - Conversion Active
1436 * 0b0..Conversion not in progress.
1437 * 0b1..Conversion in progress.
1438 */
1439#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1440#define ADC_GS_CALF_MASK (0x2U)
1441#define ADC_GS_CALF_SHIFT (1U)
1442/* CALF - Calibration Failed Flag
1443 * 0b0..Calibration completed normally.
1444 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
1445 */
1446#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1447#define ADC_GS_AWKST_MASK (0x4U)
1448#define ADC_GS_AWKST_SHIFT (2U)
1449/* AWKST - Asynchronous wakeup interrupt status
1450 * 0b1..Asynchronous wake up interrupt occurred in stop mode.
1451 * 0b0..No asynchronous interrupt.
1452 */
1453#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1454/* @} GS */
1455
1456/* @name CV - Compare value register */
1457/* @{ */
1458#define ADC_CV_CV1_MASK (0xFFFU)
1459#define ADC_CV_CV1_SHIFT (0U)
1460#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1461#define ADC_CV_CV2_MASK (0xFFF0000U)
1462#define ADC_CV_CV2_SHIFT (16U)
1463#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1464/* @} CV */
1465
1466/* @name OFS - Offset correction value register */
1467/* @{ */
1468#define ADC_OFS_OFS_MASK (0xFFFU)
1469#define ADC_OFS_OFS_SHIFT (0U)
1470#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1471#define ADC_OFS_SIGN_MASK (0x1000U)
1472#define ADC_OFS_SIGN_SHIFT (12U)
1473/* SIGN - Sign bit
1474 * 0b0..The offset value is added with the raw result
1475 * 0b1..The offset value is subtracted from the raw converted value
1476 */
1477#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1478/* @} OFS */
1479
1480/* @name CAL - Calibration value register */
1481/* @{ */
1482#define ADC_CAL_CAL_CODE_MASK (0xFU)
1483#define ADC_CAL_CAL_CODE_SHIFT (0U)
1484#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
1485/* @} CAL */
1486
1487
1488/* @} end of group ADC_Register_Masks */
1489
1490
1491
1492/* ADC - Peripheral instance base addresses */
1493/* Peripheral ADC1 base address */
1494#define ADC1_BASE (0x400C4000u)
1495/* Peripheral ADC1 base pointer */
1496#define ADC1 ((ADC_Type *)ADC1_BASE)
1497/* Peripheral ADC2 base address */
1498#define ADC2_BASE (0x400C8000u)
1499/* Peripheral ADC2 base pointer */
1500#define ADC2 ((ADC_Type *)ADC2_BASE)
1501/* Array initializer of ADC peripheral base addresses */
1502#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
1503/* Array initializer of ADC peripheral base pointers */
1504#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
1505/* Interrupt vectors for the ADC peripheral type */
1506#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1507
1508/* @} end of group ADC_Peripheral_Access_Layer */
1509
1510
1511/* ----------------------------------------------------------------------------
1512 -- ADC_ETC Peripheral Access Layer
1513 ---------------------------------------------------------------------------- */
1514
1515/*
1516 * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
1517 * @{
1518 */
1519
1520/* ADC_ETC - Register Layout Typedef */
1521typedef struct {
1522 __IO uint32_t CTRL;
1523 __IO uint32_t DONE0_1_IRQ;
1524 __IO uint32_t DONE2_ERR_IRQ;
1525 __IO uint32_t DMA_CTRL;
1526 struct { /* offset: 0x10, array step: 0x28 */
1527 __IO uint32_t CTRL;
1528 __IO uint32_t COUNTER;
1529 union{
1530 struct {
1531 __IO uint32_t CHAIN_1_0;
1532 __IO uint32_t CHAIN_3_2;
1533 __IO uint32_t CHAIN_5_4;
1534 __IO uint32_t CHAIN_7_6;
1535 };
1536 __IO uint32_t CHAIN[4];
1537 };
1538 union {
1539 struct{
1540 __I uint32_t RESULT_1_0;
1541 __I uint32_t RESULT_3_2;
1542 __I uint32_t RESULT_5_4;
1543 __I uint32_t RESULT_7_6;
1544 };
1545 __I uint32_t RESULT[4];
1546 };
1547 } TRIG[8];
1548} ADC_ETC_Type;
1549
1550/* ----------------------------------------------------------------------------
1551 -- ADC_ETC Register Masks
1552 ---------------------------------------------------------------------------- */
1553
1554/*
1555 * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
1556 * @{
1557 */
1558
1559/* @name CTRL - ADC_ETC Global Control Register */
1560/* @{ */
1561#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1562#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1563#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1564#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1565#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1566#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1567#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1568#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1569#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1570#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1571#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1572#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1573#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1574#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1575#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1576#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1577#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1578#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1579#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1580#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1581#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1582#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1583#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1584#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1585#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1586#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1587#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1588/* @} */
1589
1590/* @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
1591/* @{ */
1592#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1593#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1594#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1595#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1596#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1597#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1598#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1599#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1600#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1601#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1602#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1603#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1604#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1605#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1606#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1607#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1608#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1609#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1610#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1611#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1612#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1613#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1614#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1615#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1616#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1617#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1618#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1619#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1620#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1621#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1622#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1623#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1624#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1625#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1626#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1627#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1628#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1629#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1630#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1631#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1632#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1633#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1634#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1635#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1636#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1637#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1638#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1639#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1640/* @} */
1641
1642/* @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
1643/* @{ */
1644#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1645#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1646#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
1647#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1648#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1649#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1650#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1651#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1652#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1653#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1654#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1655#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1656#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1657#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1658#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1659#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1660#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1661#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1662#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1663#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1664#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1665#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1666#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1667#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1668#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1669#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1670#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1671#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1672#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1673#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1674#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1675#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1676#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1677#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1678#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1679#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1680#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1681#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1682#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1683#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1684#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1685#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1686#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1687#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1688#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1689#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1690#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1691#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1692/* @} */
1693
1694/* @name DMA_CTRL - ETC DMA control Register */
1695/* @{ */
1696#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1697#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1698#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1699#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1700#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1701#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1702#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1703#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1704#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1705#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1706#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1707#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1708#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1709#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1710#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1711#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1712#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1713#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1714#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1715#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1716#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1717#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1718#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1719#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1720#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1721#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1722#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1723#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1724#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1725#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1726#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1727#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1728#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1729#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1730#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1731#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1732#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1733#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1734#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1735#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1736#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1737#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1738#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1739#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1740#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1741#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1742#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1743#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1744/* @} */
1745
1746/* @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */
1747/* @{ */
1748#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1749#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1750#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1751#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1752#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1753#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1754#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1755#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1756#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1757#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1758#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1759#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1760#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1761#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1762#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1763/* @} */
1764
1765/* The count of ADC_ETC_TRIGn_CTRL */
1766#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
1767
1768/* @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */
1769/* @{ */
1770#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1771#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1772#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1773#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1774#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1775#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1776/* @} */
1777
1778/* The count of ADC_ETC_TRIGn_COUNTER */
1779#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
1780
1781/* @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
1782/* @{ */
1783#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
1784#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
1785#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
1786#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
1787#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
1788#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
1789#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
1790#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
1791#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
1792#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
1793#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
1794#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
1795#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
1796#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
1797#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
1798#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
1799#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
1800#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
1801#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
1802#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
1803#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
1804#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
1805#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
1806#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
1807/* @} */
1808
1809/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
1810#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
1811
1812/* @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
1813/* @{ */
1814#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
1815#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
1816#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
1817#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
1818#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
1819#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
1820#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
1821#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
1822#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
1823#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
1824#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
1825#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
1826#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
1827#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
1828#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
1829#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
1830#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
1831#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
1832#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
1833#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
1834#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
1835#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
1836#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
1837#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
1838/* @} */
1839
1840/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
1841#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
1842
1843/* @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
1844/* @{ */
1845#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
1846#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
1847#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
1848#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
1849#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
1850#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
1851#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
1852#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
1853#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
1854#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
1855#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
1856#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
1857#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
1858#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
1859#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
1860#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
1861#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
1862#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
1863#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
1864#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
1865#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
1866#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
1867#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
1868#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
1869/* @} */
1870
1871/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
1872#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
1873
1874/* @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
1875/* @{ */
1876#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
1877#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
1878#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
1879#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
1880#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
1881#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
1882#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
1883#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
1884#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
1885#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
1886#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
1887#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
1888#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
1889#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
1890#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
1891#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
1892#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
1893#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
1894#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
1895#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
1896#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
1897#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
1898#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
1899#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
1900/* @} */
1901
1902/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
1903#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
1904
1905/* @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
1906/* @{ */
1907#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
1908#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
1909#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
1910#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
1911#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
1912#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
1913/* @} */
1914
1915/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
1916#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
1917
1918/* @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
1919/* @{ */
1920#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
1921#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
1922#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
1923#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
1924#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
1925#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
1926/* @} */
1927
1928/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
1929#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
1930
1931/* @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
1932/* @{ */
1933#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
1934#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
1935#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
1936#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
1937#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
1938#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
1939/* @} */
1940
1941/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
1942#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
1943
1944/* @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
1945/* @{ */
1946#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
1947#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
1948#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
1949#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
1950#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
1951#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
1952/* @} */
1953
1954/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
1955#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
1956
1957
1958/*
1959 * @}
1960 */ /* end of group ADC_ETC_Register_Masks */
1961
1962
1963/* ADC_ETC - Peripheral instance base addresses */
1964/* Peripheral ADC_ETC base address */
1965#define ADC_ETC_BASE (0x403B0000u)
1966/* Peripheral ADC_ETC base pointer */
1967#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
1968/* Array initializer of ADC_ETC peripheral base addresses */
1969#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
1970/* Array initializer of ADC_ETC peripheral base pointers */
1971#define ADC_ETC_BASE_PTRS { ADC_ETC }
1972/* Interrupt vectors for the ADC_ETC peripheral type */
1973#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
1974#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
1975
1976/*
1977 * @}
1978 */ /* end of group ADC_ETC_Peripheral_Access_Layer */
1979
1980
1981/* ----------------------------------------------------------------------------
1982 -- AIPSTZ Peripheral Access Layer
1983 ---------------------------------------------------------------------------- */
1984
1985/*
1986 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
1987 * @{
1988 */
1989
1990/* AIPSTZ - Register Layout Typedef */
1991typedef struct {
1992 __IO uint32_t MPR;
1993 uint8_t RESERVED_0[60];
1994 __IO uint32_t OPACR;
1995 __IO uint32_t OPACR1;
1996 __IO uint32_t OPACR2;
1997 __IO uint32_t OPACR3;
1998 __IO uint32_t OPACR4;
1999} AIPSTZ_Type;
2000
2001/* ----------------------------------------------------------------------------
2002 -- AIPSTZ Register Masks
2003 ---------------------------------------------------------------------------- */
2004
2005/*
2006 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
2007 * @{
2008 */
2009
2010/* @name MPR - Master Priviledge Registers */
2011/* @{ */
2012#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
2013#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
2014/* MPROT5
2015 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2016 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2017 * 0bxx0x..This master is not trusted for write accesses.
2018 * 0bxx1x..This master is trusted for write accesses.
2019 * 0bx0xx..This master is not trusted for read accesses.
2020 * 0bx1xx..This master is trusted for read accesses.
2021 * 0b1xxx..Write accesses from this master are allowed to be buffered
2022 */
2023#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
2024#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
2025#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
2026/* MPROT3
2027 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2028 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2029 * 0bxx0x..This master is not trusted for write accesses.
2030 * 0bxx1x..This master is trusted for write accesses.
2031 * 0bx0xx..This master is not trusted for read accesses.
2032 * 0bx1xx..This master is trusted for read accesses.
2033 * 0b1xxx..Write accesses from this master are allowed to be buffered
2034 */
2035#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
2036#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
2037#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
2038/* MPROT2
2039 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2040 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2041 * 0bxx0x..This master is not trusted for write accesses.
2042 * 0bxx1x..This master is trusted for write accesses.
2043 * 0bx0xx..This master is not trusted for read accesses.
2044 * 0bx1xx..This master is trusted for read accesses.
2045 * 0b1xxx..Write accesses from this master are allowed to be buffered
2046 */
2047#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
2048#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
2049#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
2050/* MPROT1
2051 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2052 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2053 * 0bxx0x..This master is not trusted for write accesses.
2054 * 0bxx1x..This master is trusted for write accesses.
2055 * 0bx0xx..This master is not trusted for read accesses.
2056 * 0bx1xx..This master is trusted for read accesses.
2057 * 0b1xxx..Write accesses from this master are allowed to be buffered
2058 */
2059#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
2060#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
2061#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
2062/* MPROT0
2063 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2064 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2065 * 0bxx0x..This master is not trusted for write accesses.
2066 * 0bxx1x..This master is trusted for write accesses.
2067 * 0bx0xx..This master is not trusted for read accesses.
2068 * 0bx1xx..This master is trusted for read accesses.
2069 * 0b1xxx..Write accesses from this master are allowed to be buffered
2070 */
2071#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
2072/* @} */
2073
2074/* @name OPACR - Off-Platform Peripheral Access Control Registers */
2075/* @{ */
2076#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
2077#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
2078/* OPAC7
2079 * 0bxxx0..Accesses from an untrusted master are allowed.
2080 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2081 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2082 * 0bxx0x..This peripheral allows write accesses.
2083 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2084 * error response and no peripheral access is initiated on the IPS bus.
2085 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2086 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2087 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2088 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2089 * on the IPS bus.
2090 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2091 */
2092#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
2093#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
2094#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
2095/* OPAC6
2096 * 0bxxx0..Accesses from an untrusted master are allowed.
2097 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2098 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2099 * 0bxx0x..This peripheral allows write accesses.
2100 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2101 * error response and no peripheral access is initiated on the IPS bus.
2102 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2103 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2104 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2105 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2106 * on the IPS bus.
2107 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2108 */
2109#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
2110#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
2111#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
2112/* OPAC5
2113 * 0bxxx0..Accesses from an untrusted master are allowed.
2114 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2115 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2116 * 0bxx0x..This peripheral allows write accesses.
2117 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2118 * error response and no peripheral access is initiated on the IPS bus.
2119 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2120 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2121 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2122 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2123 * on the IPS bus.
2124 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2125 */
2126#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2127#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
2128#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
2129/* OPAC4
2130 * 0bxxx0..Accesses from an untrusted master are allowed.
2131 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2132 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2133 * 0bxx0x..This peripheral allows write accesses.
2134 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2135 * error response and no peripheral access is initiated on the IPS bus.
2136 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2137 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2138 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2139 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2140 * on the IPS bus.
2141 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2142 */
2143#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2144#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
2145#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
2146/* OPAC3
2147 * 0bxxx0..Accesses from an untrusted master are allowed.
2148 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2149 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2150 * 0bxx0x..This peripheral allows write accesses.
2151 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2152 * error response and no peripheral access is initiated on the IPS bus.
2153 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2154 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2155 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2156 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2157 * on the IPS bus.
2158 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2159 */
2160#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2161#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
2162#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
2163/* OPAC2
2164 * 0bxxx0..Accesses from an untrusted master are allowed.
2165 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2166 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2167 * 0bxx0x..This peripheral allows write accesses.
2168 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2169 * error response and no peripheral access is initiated on the IPS bus.
2170 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2171 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2172 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2173 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2174 * on the IPS bus.
2175 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2176 */
2177#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2178#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
2179#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
2180/* OPAC1
2181 * 0bxxx0..Accesses from an untrusted master are allowed.
2182 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2183 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2184 * 0bxx0x..This peripheral allows write accesses.
2185 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2186 * error response and no peripheral access is initiated on the IPS bus.
2187 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2188 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2189 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2190 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2191 * on the IPS bus.
2192 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2193 */
2194#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
2195#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
2196#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
2197/* OPAC0
2198 * 0bxxx0..Accesses from an untrusted master are allowed.
2199 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2200 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2201 * 0bxx0x..This peripheral allows write accesses.
2202 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2203 * error response and no peripheral access is initiated on the IPS bus.
2204 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2205 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2206 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2207 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2208 * on the IPS bus.
2209 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2210 */
2211#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
2212/* @} */
2213
2214/* @name OPACR1 - Off-Platform Peripheral Access Control Registers */
2215/* @{ */
2216#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
2217#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
2218/* OPAC15
2219 * 0bxxx0..Accesses from an untrusted master are allowed.
2220 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2221 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2222 * 0bxx0x..This peripheral allows write accesses.
2223 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2224 * error response and no peripheral access is initiated on the IPS bus.
2225 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2226 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2227 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2228 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2229 * on the IPS bus.
2230 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2231 */
2232#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
2233#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
2234#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
2235/* OPAC14
2236 * 0bxxx0..Accesses from an untrusted master are allowed.
2237 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2238 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2239 * 0bxx0x..This peripheral allows write accesses.
2240 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2241 * error response and no peripheral access is initiated on the IPS bus.
2242 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2243 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2244 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2245 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2246 * on the IPS bus.
2247 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2248 */
2249#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
2250#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
2251#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
2252/* OPAC13
2253 * 0bxxx0..Accesses from an untrusted master are allowed.
2254 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2255 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2256 * 0bxx0x..This peripheral allows write accesses.
2257 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2258 * error response and no peripheral access is initiated on the IPS bus.
2259 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2260 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2261 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2262 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2263 * on the IPS bus.
2264 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2265 */
2266#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
2267#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
2268#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
2269/* OPAC12
2270 * 0bxxx0..Accesses from an untrusted master are allowed.
2271 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2272 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2273 * 0bxx0x..This peripheral allows write accesses.
2274 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2275 * error response and no peripheral access is initiated on the IPS bus.
2276 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2277 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2278 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2279 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2280 * on the IPS bus.
2281 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2282 */
2283#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
2284#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
2285#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
2286/* OPAC11
2287 * 0bxxx0..Accesses from an untrusted master are allowed.
2288 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2289 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2290 * 0bxx0x..This peripheral allows write accesses.
2291 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2292 * error response and no peripheral access is initiated on the IPS bus.
2293 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2294 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2295 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2296 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2297 * on the IPS bus.
2298 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2299 */
2300#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
2301#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
2302#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
2303/* OPAC10
2304 * 0bxxx0..Accesses from an untrusted master are allowed.
2305 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2306 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2307 * 0bxx0x..This peripheral allows write accesses.
2308 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2309 * error response and no peripheral access is initiated on the IPS bus.
2310 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2311 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2312 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2313 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2314 * on the IPS bus.
2315 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2316 */
2317#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
2318#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
2319#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
2320/* OPAC9
2321 * 0bxxx0..Accesses from an untrusted master are allowed.
2322 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2323 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2324 * 0bxx0x..This peripheral allows write accesses.
2325 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2326 * error response and no peripheral access is initiated on the IPS bus.
2327 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2328 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2329 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2330 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2331 * on the IPS bus.
2332 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2333 */
2334#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
2335#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
2336#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
2337/* OPAC8
2338 * 0bxxx0..Accesses from an untrusted master are allowed.
2339 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2340 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2341 * 0bxx0x..This peripheral allows write accesses.
2342 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2343 * error response and no peripheral access is initiated on the IPS bus.
2344 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2345 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2346 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2347 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2348 * on the IPS bus.
2349 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2350 */
2351#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
2352/* @} */
2353
2354/* @name OPACR2 - Off-Platform Peripheral Access Control Registers */
2355/* @{ */
2356#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
2357#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
2358/* OPAC23
2359 * 0bxxx0..Accesses from an untrusted master are allowed.
2360 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2361 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2362 * 0bxx0x..This peripheral allows write accesses.
2363 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2364 * error response and no peripheral access is initiated on the IPS bus.
2365 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2366 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2367 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2368 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2369 * on the IPS bus.
2370 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2371 */
2372#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
2373#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
2374#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
2375/* OPAC22
2376 * 0bxxx0..Accesses from an untrusted master are allowed.
2377 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2378 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2379 * 0bxx0x..This peripheral allows write accesses.
2380 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2381 * error response and no peripheral access is initiated on the IPS bus.
2382 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2383 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2384 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2385 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2386 * on the IPS bus.
2387 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2388 */
2389#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
2390#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
2391#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
2392/* OPAC21
2393 * 0bxxx0..Accesses from an untrusted master are allowed.
2394 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2395 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2396 * 0bxx0x..This peripheral allows write accesses.
2397 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2398 * error response and no peripheral access is initiated on the IPS bus.
2399 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2400 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2401 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2402 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2403 * on the IPS bus.
2404 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2405 */
2406#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
2407#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
2408#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
2409/* OPAC20
2410 * 0bxxx0..Accesses from an untrusted master are allowed.
2411 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2412 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2413 * 0bxx0x..This peripheral allows write accesses.
2414 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2415 * error response and no peripheral access is initiated on the IPS bus.
2416 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2417 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2418 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2419 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2420 * on the IPS bus.
2421 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2422 */
2423#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
2424#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
2425#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
2426/* OPAC19
2427 * 0bxxx0..Accesses from an untrusted master are allowed.
2428 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2429 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2430 * 0bxx0x..This peripheral allows write accesses.
2431 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2432 * error response and no peripheral access is initiated on the IPS bus.
2433 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2434 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2435 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2436 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2437 * on the IPS bus.
2438 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2439 */
2440#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
2441#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
2442#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
2443/* OPAC18
2444 * 0bxxx0..Accesses from an untrusted master are allowed.
2445 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2446 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2447 * 0bxx0x..This peripheral allows write accesses.
2448 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2449 * error response and no peripheral access is initiated on the IPS bus.
2450 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2451 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2452 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2453 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2454 * on the IPS bus.
2455 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2456 */
2457#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
2458#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
2459#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
2460/* OPAC17
2461 * 0bxxx0..Accesses from an untrusted master are allowed.
2462 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2463 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2464 * 0bxx0x..This peripheral allows write accesses.
2465 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2466 * error response and no peripheral access is initiated on the IPS bus.
2467 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2468 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2469 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2470 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2471 * on the IPS bus.
2472 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2473 */
2474#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
2475#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
2476#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
2477/* OPAC16
2478 * 0bxxx0..Accesses from an untrusted master are allowed.
2479 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2480 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2481 * 0bxx0x..This peripheral allows write accesses.
2482 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2483 * error response and no peripheral access is initiated on the IPS bus.
2484 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2485 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2486 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2487 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2488 * on the IPS bus.
2489 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2490 */
2491#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
2492/* @} */
2493
2494/* @name OPACR3 - Off-Platform Peripheral Access Control Registers */
2495/* @{ */
2496#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
2497#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
2498/* OPAC31
2499 * 0bxxx0..Accesses from an untrusted master are allowed.
2500 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2501 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2502 * 0bxx0x..This peripheral allows write accesses.
2503 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2504 * error response and no peripheral access is initiated on the IPS bus.
2505 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2506 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2507 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2508 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2509 * on the IPS bus.
2510 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2511 */
2512#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
2513#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
2514#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
2515/* OPAC30
2516 * 0bxxx0..Accesses from an untrusted master are allowed.
2517 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2518 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2519 * 0bxx0x..This peripheral allows write accesses.
2520 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2521 * error response and no peripheral access is initiated on the IPS bus.
2522 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2523 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2524 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2525 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2526 * on the IPS bus.
2527 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2528 */
2529#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
2530#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
2531#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
2532/* OPAC29
2533 * 0bxxx0..Accesses from an untrusted master are allowed.
2534 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2535 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2536 * 0bxx0x..This peripheral allows write accesses.
2537 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2538 * error response and no peripheral access is initiated on the IPS bus.
2539 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2540 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2541 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2542 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2543 * on the IPS bus.
2544 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2545 */
2546#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
2547#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
2548#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
2549/* OPAC28
2550 * 0bxxx0..Accesses from an untrusted master are allowed.
2551 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2552 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2553 * 0bxx0x..This peripheral allows write accesses.
2554 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2555 * error response and no peripheral access is initiated on the IPS bus.
2556 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2557 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2558 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2559 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2560 * on the IPS bus.
2561 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2562 */
2563#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
2564#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
2565#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
2566/* OPAC27
2567 * 0bxxx0..Accesses from an untrusted master are allowed.
2568 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2569 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2570 * 0bxx0x..This peripheral allows write accesses.
2571 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2572 * error response and no peripheral access is initiated on the IPS bus.
2573 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2574 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2575 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2576 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2577 * on the IPS bus.
2578 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2579 */
2580#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
2581#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
2582#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
2583/* OPAC26
2584 * 0bxxx0..Accesses from an untrusted master are allowed.
2585 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2586 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2587 * 0bxx0x..This peripheral allows write accesses.
2588 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2589 * error response and no peripheral access is initiated on the IPS bus.
2590 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2591 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2592 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2593 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2594 * on the IPS bus.
2595 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2596 */
2597#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2598#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2599#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2600/* OPAC25
2601 * 0bxxx0..Accesses from an untrusted master are allowed.
2602 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2603 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2604 * 0bxx0x..This peripheral allows write accesses.
2605 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2606 * error response and no peripheral access is initiated on the IPS bus.
2607 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2608 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2609 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2610 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2611 * on the IPS bus.
2612 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2613 */
2614#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2615#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2616#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2617/* OPAC24
2618 * 0bxxx0..Accesses from an untrusted master are allowed.
2619 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2620 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2621 * 0bxx0x..This peripheral allows write accesses.
2622 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2623 * error response and no peripheral access is initiated on the IPS bus.
2624 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2625 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2626 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2627 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2628 * on the IPS bus.
2629 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2630 */
2631#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2632/* @} */
2633
2634/* @name OPACR4 - Off-Platform Peripheral Access Control Registers */
2635/* @{ */
2636#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2637#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2638/* OPAC33
2639 * 0bxxx0..Accesses from an untrusted master are allowed.
2640 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2641 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2642 * 0bxx0x..This peripheral allows write accesses.
2643 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2644 * error response and no peripheral access is initiated on the IPS bus.
2645 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2646 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2647 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2648 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2649 * on the IPS bus.
2650 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2651 */
2652#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2653#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2654#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2655/* OPAC32
2656 * 0bxxx0..Accesses from an untrusted master are allowed.
2657 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2658 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2659 * 0bxx0x..This peripheral allows write accesses.
2660 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2661 * error response and no peripheral access is initiated on the IPS bus.
2662 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2663 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2664 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2665 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2666 * on the IPS bus.
2667 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2668 */
2669#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
2670/* @} */
2671
2672
2673/*
2674 * @}
2675 */ /* end of group AIPSTZ_Register_Masks */
2676
2677
2678/* AIPSTZ - Peripheral instance base addresses */
2679/* Peripheral AIPSTZ1 base address */
2680#define AIPSTZ1_BASE (0x4007C000u)
2681/* Peripheral AIPSTZ1 base pointer */
2682#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2683/* Peripheral AIPSTZ2 base address */
2684#define AIPSTZ2_BASE (0x4017C000u)
2685/* Peripheral AIPSTZ2 base pointer */
2686#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2687/* Peripheral AIPSTZ3 base address */
2688#define AIPSTZ3_BASE (0x4027C000u)
2689/* Peripheral AIPSTZ3 base pointer */
2690#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
2691/* Peripheral AIPSTZ4 base address */
2692#define AIPSTZ4_BASE (0x4037C000u)
2693/* Peripheral AIPSTZ4 base pointer */
2694#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
2695/* Array initializer of AIPSTZ peripheral base addresses */
2696#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
2697/* Array initializer of AIPSTZ peripheral base pointers */
2698#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
2699
2700/*
2701 * @}
2702 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
2703
2704
2705/* ----------------------------------------------------------------------------
2706 -- AOI Peripheral Access Layer
2707 ---------------------------------------------------------------------------- */
2708
2709/*
2710 * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
2711 * @{
2712 */
2713
2714/* AOI - Register Layout Typedef */
2715typedef struct {
2716 struct { /* offset: 0x0, array step: 0x4 */
2717 __IO uint16_t BFCRT01;
2718 __IO uint16_t BFCRT23;
2719 } BFCRT[4];
2720} AOI_Type;
2721
2722/* ----------------------------------------------------------------------------
2723 -- AOI Register Masks
2724 ---------------------------------------------------------------------------- */
2725
2726/*
2727 * @addtogroup AOI_Register_Masks AOI Register Masks
2728 * @{
2729 */
2730
2731/* @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
2732/* @{ */
2733#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2734#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2735/* PT1_DC - Product term 1, D input configuration
2736 * 0b00..Force the D input in this product term to a logical zero
2737 * 0b01..Pass the D input in this product term
2738 * 0b10..Complement the D input in this product term
2739 * 0b11..Force the D input in this product term to a logical one
2740 */
2741#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2742#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2743#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2744/* PT1_CC - Product term 1, C input configuration
2745 * 0b00..Force the C input in this product term to a logical zero
2746 * 0b01..Pass the C input in this product term
2747 * 0b10..Complement the C input in this product term
2748 * 0b11..Force the C input in this product term to a logical one
2749 */
2750#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2751#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2752#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2753/* PT1_BC - Product term 1, B input configuration
2754 * 0b00..Force the B input in this product term to a logical zero
2755 * 0b01..Pass the B input in this product term
2756 * 0b10..Complement the B input in this product term
2757 * 0b11..Force the B input in this product term to a logical one
2758 */
2759#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2760#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2761#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2762/* PT1_AC - Product term 1, A input configuration
2763 * 0b00..Force the A input in this product term to a logical zero
2764 * 0b01..Pass the A input in this product term
2765 * 0b10..Complement the A input in this product term
2766 * 0b11..Force the A input in this product term to a logical one
2767 */
2768#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2769#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2770#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2771/* PT0_DC - Product term 0, D input configuration
2772 * 0b00..Force the D input in this product term to a logical zero
2773 * 0b01..Pass the D input in this product term
2774 * 0b10..Complement the D input in this product term
2775 * 0b11..Force the D input in this product term to a logical one
2776 */
2777#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2778#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2779#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2780/* PT0_CC - Product term 0, C input configuration
2781 * 0b00..Force the C input in this product term to a logical zero
2782 * 0b01..Pass the C input in this product term
2783 * 0b10..Complement the C input in this product term
2784 * 0b11..Force the C input in this product term to a logical one
2785 */
2786#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
2787#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
2788#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
2789/* PT0_BC - Product term 0, B input configuration
2790 * 0b00..Force the B input in this product term to a logical zero
2791 * 0b01..Pass the B input in this product term
2792 * 0b10..Complement the B input in this product term
2793 * 0b11..Force the B input in this product term to a logical one
2794 */
2795#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
2796#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
2797#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
2798/* PT0_AC - Product term 0, A input configuration
2799 * 0b00..Force the A input in this product term to a logical zero
2800 * 0b01..Pass the A input in this product term
2801 * 0b10..Complement the A input in this product term
2802 * 0b11..Force the A input in this product term to a logical one
2803 */
2804#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
2805/* @} */
2806
2807/* The count of AOI_BFCRT01 */
2808#define AOI_BFCRT01_COUNT (4U)
2809
2810/* @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
2811/* @{ */
2812#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
2813#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
2814/* PT3_DC - Product term 3, D input configuration
2815 * 0b00..Force the D input in this product term to a logical zero
2816 * 0b01..Pass the D input in this product term
2817 * 0b10..Complement the D input in this product term
2818 * 0b11..Force the D input in this product term to a logical one
2819 */
2820#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
2821#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
2822#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
2823/* PT3_CC - Product term 3, C input configuration
2824 * 0b00..Force the C input in this product term to a logical zero
2825 * 0b01..Pass the C input in this product term
2826 * 0b10..Complement the C input in this product term
2827 * 0b11..Force the C input in this product term to a logical one
2828 */
2829#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
2830#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
2831#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
2832/* PT3_BC - Product term 3, B input configuration
2833 * 0b00..Force the B input in this product term to a logical zero
2834 * 0b01..Pass the B input in this product term
2835 * 0b10..Complement the B input in this product term
2836 * 0b11..Force the B input in this product term to a logical one
2837 */
2838#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
2839#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
2840#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
2841/* PT3_AC - Product term 3, A input configuration
2842 * 0b00..Force the A input in this product term to a logical zero
2843 * 0b01..Pass the A input in this product term
2844 * 0b10..Complement the A input in this product term
2845 * 0b11..Force the A input in this product term to a logical one
2846 */
2847#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
2848#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
2849#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
2850/* PT2_DC - Product term 2, D input configuration
2851 * 0b00..Force the D input in this product term to a logical zero
2852 * 0b01..Pass the D input in this product term
2853 * 0b10..Complement the D input in this product term
2854 * 0b11..Force the D input in this product term to a logical one
2855 */
2856#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
2857#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
2858#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
2859/* PT2_CC - Product term 2, C input configuration
2860 * 0b00..Force the C input in this product term to a logical zero
2861 * 0b01..Pass the C input in this product term
2862 * 0b10..Complement the C input in this product term
2863 * 0b11..Force the C input in this product term to a logical one
2864 */
2865#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
2866#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
2867#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
2868/* PT2_BC - Product term 2, B input configuration
2869 * 0b00..Force the B input in this product term to a logical zero
2870 * 0b01..Pass the B input in this product term
2871 * 0b10..Complement the B input in this product term
2872 * 0b11..Force the B input in this product term to a logical one
2873 */
2874#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
2875#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
2876#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
2877/* PT2_AC - Product term 2, A input configuration
2878 * 0b00..Force the A input in this product term to a logical zero
2879 * 0b01..Pass the A input in this product term
2880 * 0b10..Complement the A input in this product term
2881 * 0b11..Force the A input in this product term to a logical one
2882 */
2883#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
2884/* @} */
2885
2886/* The count of AOI_BFCRT23 */
2887#define AOI_BFCRT23_COUNT (4U)
2888
2889
2890/*
2891 * @}
2892 */ /* end of group AOI_Register_Masks */
2893
2894
2895/* AOI - Peripheral instance base addresses */
2896/* Peripheral AOI1 base address */
2897#define AOI1_BASE (0x403B4000u)
2898/* Peripheral AOI1 base pointer */
2899#define AOI1 ((AOI_Type *)AOI1_BASE)
2900/* Peripheral AOI2 base address */
2901#define AOI2_BASE (0x403B8000u)
2902/* Peripheral AOI2 base pointer */
2903#define AOI2 ((AOI_Type *)AOI2_BASE)
2904/* Array initializer of AOI peripheral base addresses */
2905#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
2906/* Array initializer of AOI peripheral base pointers */
2907#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
2908
2909/*
2910 * @}
2911 */ /* end of group AOI_Peripheral_Access_Layer */
2912
2913
2914/* ----------------------------------------------------------------------------
2915 -- BEE Peripheral Access Layer
2916 ---------------------------------------------------------------------------- */
2917
2918/*
2919 * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
2920 * @{
2921 */
2922
2923/* BEE - Register Layout Typedef */
2924typedef struct {
2925 __IO uint32_t CTRL;
2926 __IO uint32_t ADDR_OFFSET0;
2927 __IO uint32_t ADDR_OFFSET1;
2928 __IO uint32_t AES_KEY0_W0;
2929 __IO uint32_t AES_KEY0_W1;
2930 __IO uint32_t AES_KEY0_W2;
2931 __IO uint32_t AES_KEY0_W3;
2932 __IO uint32_t STATUS;
2933 __O uint32_t CTR_NONCE0_W0;
2934 __O uint32_t CTR_NONCE0_W1;
2935 __O uint32_t CTR_NONCE0_W2;
2936 __O uint32_t CTR_NONCE0_W3;
2937 __O uint32_t CTR_NONCE1_W0;
2938 __O uint32_t CTR_NONCE1_W1;
2939 __O uint32_t CTR_NONCE1_W2;
2940 __O uint32_t CTR_NONCE1_W3;
2941 __IO uint32_t REGION1_TOP;
2942 __IO uint32_t REGION1_BOT;
2943} BEE_Type;
2944
2945/* ----------------------------------------------------------------------------
2946 -- BEE Register Masks
2947 ---------------------------------------------------------------------------- */
2948
2949/*
2950 * @addtogroup BEE_Register_Masks BEE Register Masks
2951 * @{
2952 */
2953
2954/* @name CTRL - BEE Control Register */
2955/* @{ */
2956#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
2957#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
2958/* BEE_ENABLE
2959 * 0b0..Disable BEE
2960 * 0b1..Enable BEE
2961 */
2962#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
2963#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
2964#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
2965#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
2966#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
2967#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
2968#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
2969#define BEE_CTRL_KEY_VALID_MASK (0x10U)
2970#define BEE_CTRL_KEY_VALID_SHIFT (4U)
2971#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
2972#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
2973#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
2974/* KEY_REGION_SEL
2975 * 0b0..Load AES key for region0
2976 * 0b1..Load AES key for region1
2977 */
2978#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
2979#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
2980#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
2981#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
2982#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
2983#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
2984/* LITTLE_ENDIAN
2985 * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8,
2986 * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to
2987 * Byte0 to Byte15.
2988 * 0b1..The input and output data of AES core is not swapped.
2989 */
2990#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
2991#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
2992#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
2993#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
2994#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
2995#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
2996/* CTRL_AES_MODE_R0
2997 * 0b0..ECB
2998 * 0b1..CTR
2999 */
3000#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
3001#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
3002#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
3003#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
3004#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
3005#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
3006/* CTRL_AES_MODE_R1
3007 * 0b0..ECB
3008 * 0b1..CTR
3009 */
3010#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
3011#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
3012#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
3013#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
3014#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
3015#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
3016#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
3017#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
3018#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
3019#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
3020#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
3021#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
3022#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
3023#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
3024#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
3025#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
3026#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
3027#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
3028#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
3029#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
3030#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
3031#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
3032#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
3033#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
3034#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
3035#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
3036#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
3037#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
3038#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
3039#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
3040#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
3041#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
3042#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
3043#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
3044#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
3045#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
3046#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
3047#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
3048#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
3049#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
3050#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
3051#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
3052#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
3053/* @} */
3054
3055/* @name ADDR_OFFSET0 - */
3056/* @{ */
3057#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
3058#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
3059#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
3060#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
3061#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
3062#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
3063/* @} */
3064
3065/* @name ADDR_OFFSET1 - */
3066/* @{ */
3067#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
3068#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
3069#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
3070#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
3071#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
3072#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
3073/* @} */
3074
3075/* @name AES_KEY0_W0 - */
3076/* @{ */
3077#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
3078#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
3079#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
3080/* @} */
3081
3082/* @name AES_KEY0_W1 - */
3083/* @{ */
3084#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
3085#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
3086#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
3087/* @} */
3088
3089/* @name AES_KEY0_W2 - */
3090/* @{ */
3091#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
3092#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
3093#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
3094/* @} */
3095
3096/* @name AES_KEY0_W3 - */
3097/* @{ */
3098#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
3099#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
3100#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
3101/* @} */
3102
3103/* @name STATUS - */
3104/* @{ */
3105#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
3106#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
3107#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
3108#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
3109#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
3110#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
3111/* @} */
3112
3113/* @name CTR_NONCE0_W0 - */
3114/* @{ */
3115#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
3116#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
3117#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
3118/* @} */
3119
3120/* @name CTR_NONCE0_W1 - */
3121/* @{ */
3122#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
3123#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
3124#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
3125/* @} */
3126
3127/* @name CTR_NONCE0_W2 - */
3128/* @{ */
3129#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
3130#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
3131#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
3132/* @} */
3133
3134/* @name CTR_NONCE0_W3 - */
3135/* @{ */
3136#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
3137#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
3138#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
3139/* @} */
3140
3141/* @name CTR_NONCE1_W0 - */
3142/* @{ */
3143#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
3144#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
3145#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
3146/* @} */
3147
3148/* @name CTR_NONCE1_W1 - */
3149/* @{ */
3150#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
3151#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
3152#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
3153/* @} */
3154
3155/* @name CTR_NONCE1_W2 - */
3156/* @{ */
3157#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
3158#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
3159#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
3160/* @} */
3161
3162/* @name CTR_NONCE1_W3 - */
3163/* @{ */
3164#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
3165#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
3166#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
3167/* @} */
3168
3169/* @name REGION1_TOP - */
3170/* @{ */
3171#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
3172#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
3173#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
3174/* @} */
3175
3176/* @name REGION1_BOT - */
3177/* @{ */
3178#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
3179#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
3180#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
3181/* @} */
3182
3183
3184/*
3185 * @}
3186 */ /* end of group BEE_Register_Masks */
3187
3188
3189/* BEE - Peripheral instance base addresses */
3190/* Peripheral BEE base address */
3191#define BEE_BASE (0x403EC000u)
3192/* Peripheral BEE base pointer */
3193#define BEE ((BEE_Type *)BEE_BASE)
3194/* Array initializer of BEE peripheral base addresses */
3195#define BEE_BASE_ADDRS { BEE_BASE }
3196/* Array initializer of BEE peripheral base pointers */
3197#define BEE_BASE_PTRS { BEE }
3198
3199/*
3200 * @}
3201 */ /* end of group BEE_Peripheral_Access_Layer */
3202
3203
3204/* ----------------------------------------------------------------------------
3205 -- CAN Peripheral Access Layer
3206 ---------------------------------------------------------------------------- */
3207
3208/*
3209 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
3210 * @{
3211 */
3212
3213/* CAN - Register Layout Typedef */
3214typedef struct {
3215 __IO uint32_t MCR;
3216 __IO uint32_t CTRL1;
3217 __IO uint32_t TIMER;
3218 uint8_t RESERVED_0[4];
3219 __IO uint32_t RXMGMASK;
3220 __IO uint32_t RX14MASK;
3221 __IO uint32_t RX15MASK;
3222 __IO uint32_t ECR;
3223 __IO uint32_t ESR1;
3224 __IO uint32_t IMASK2;
3225 __IO uint32_t IMASK1;
3226 __IO uint32_t IFLAG2;
3227 __IO uint32_t IFLAG1;
3228 __IO uint32_t CTRL2;
3229 __I uint32_t ESR2;
3230 uint8_t RESERVED_1[8];
3231 __I uint32_t CRCR;
3232 __IO uint32_t RXFGMASK;
3233 __I uint32_t RXFIR;
3234 __IO uint32_t CBT;
3235 uint8_t RESERVED_2[4];
3236 __I uint32_t DBG1;
3237 __I uint32_t DBG2;
3238 uint8_t RESERVED_3[32];
3239 union { /* offset: 0x80 */
3240 struct { /* offset: 0x80, array step: 0x10 */
3241 __IO uint32_t CS;
3242 __IO uint32_t ID;
3243 __IO uint32_t WORD[2];
3244 } MB_8B[64];
3245 struct { /* offset: 0x80, array step: 0x18 */
3246 __IO uint32_t CS;
3247 __IO uint32_t ID;
3248 __IO uint32_t WORD[4];
3249 } MB_16B[42];
3250 struct { /* offset: 0x80, array step: 0x28 */
3251 __IO uint32_t CS;
3252 __IO uint32_t ID;
3253 __IO uint32_t WORD[8];
3254 } MB_32B[24];
3255 struct { /* offset: 0x80, array step: 0x48 */
3256 __IO uint32_t CS;
3257 __IO uint32_t ID;
3258 __IO uint32_t WORD[16];
3259 } MB_64B[14];
3260 struct { /* offset: 0x80, array step: 0x10 */
3261 __IO uint32_t CS;
3262 __IO uint32_t ID;
3263 __IO uint32_t WORD0;
3264 __IO uint32_t WORD1;
3265 } MB[64];
3266 };
3267 uint8_t RESERVED_4[1024];
3268 __IO uint32_t RXIMR[64];
3269 uint8_t RESERVED_5[96];
3270 __IO uint32_t GFWR;
3271 uint8_t RESERVED_6[524];
3272 __IO uint32_t EPRS;
3273 __IO uint32_t ENCBT;
3274 __IO uint32_t EDCBT;
3275 __IO uint32_t ETDC;
3276 __IO uint32_t FDCTRL;
3277 __IO uint32_t FDCBT;
3278 __I uint32_t FDCRC;
3279 __IO uint32_t ERFCR;
3280 __IO uint32_t ERFIER;
3281 __IO uint32_t ERFSR;
3282 uint8_t RESERVED_7[24];
3283 __I uint32_t HR_TIME_STAMP[64];
3284 uint8_t RESERVED_8[8912];
3285 __IO uint32_t ERFFEL[128];
3286} CAN_Type;
3287
3288/* ----------------------------------------------------------------------------
3289 -- CAN Register Masks
3290 ---------------------------------------------------------------------------- */
3291
3292/*
3293 * @addtogroup CAN_Register_Masks CAN Register Masks
3294 * @{
3295 */
3296
3297/* @name MCR - Module Configuration Register */
3298/* @{ */
3299#define CAN_MCR_MAXMB_MASK (0x7FU)
3300#define CAN_MCR_MAXMB_SHIFT (0U)
3301#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
3302#define CAN_MCR_IDAM_MASK (0x300U)
3303#define CAN_MCR_IDAM_SHIFT (8U)
3304/* IDAM - ID Acceptance Mode
3305 * 0b00..Format A One full ID (standard or extended) per ID filter Table element.
3306 * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
3307 * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
3308 * 0b11..Format D All frames rejected.
3309 */
3310#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
3311#define CAN_MCR_FDEN_MASK (0x800U)
3312#define CAN_MCR_FDEN_SHIFT (11U)
3313/* FDEN - CAN FD operation enable
3314 * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
3315 * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
3316 */
3317#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
3318#define CAN_MCR_AEN_MASK (0x1000U)
3319#define CAN_MCR_AEN_SHIFT (12U)
3320/* AEN - Abort Enable
3321 * 0b1..Abort enabled
3322 * 0b0..Abort disabled
3323 */
3324#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
3325#define CAN_MCR_LPRIOEN_MASK (0x2000U)
3326#define CAN_MCR_LPRIOEN_SHIFT (13U)
3327/* LPRIOEN - Local Priority Enable
3328 * 0b1..Local Priority enabled
3329 * 0b0..Local Priority disabled
3330 */
3331#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
3332#define CAN_MCR_DMA_MASK (0x8000U)
3333#define CAN_MCR_DMA_SHIFT (15U)
3334/* DMA - DMA Enable
3335 * 0b0..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are disabled.
3336 * 0b1..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are enabled.
3337 */
3338#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
3339#define CAN_MCR_IRMQ_MASK (0x10000U)
3340#define CAN_MCR_IRMQ_SHIFT (16U)
3341/* IRMQ - Individual Rx Masking And Queue Enable
3342 * 0b1..Individual Rx masking and queue feature are enabled.
3343 * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.
3344 */
3345#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
3346#define CAN_MCR_SRXDIS_MASK (0x20000U)
3347#define CAN_MCR_SRXDIS_SHIFT (17U)
3348/* SRXDIS - Self Reception Disable
3349 * 0b1..Self reception disabled
3350 * 0b0..Self reception enabled
3351 */
3352#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
3353#define CAN_MCR_DOZE_MASK (0x40000U)
3354#define CAN_MCR_DOZE_SHIFT (18U)
3355/* DOZE - Doze Mode Enable
3356 * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
3357 * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
3358 */
3359#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
3360#define CAN_MCR_WAKSRC_MASK (0x80000U)
3361#define CAN_MCR_WAKSRC_SHIFT (19U)
3362/* WAKSRC - Wake Up Source
3363 * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus
3364 * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.
3365 */
3366#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
3367#define CAN_MCR_LPMACK_MASK (0x100000U)
3368#define CAN_MCR_LPMACK_SHIFT (20U)
3369/* LPMACK - Low-Power Mode Acknowledge
3370 * 0b1..FLEXCAN is either in Disable Mode, or Stop mode
3371 * 0b0..FLEXCAN not in any of the low power modes
3372 */
3373#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
3374#define CAN_MCR_WRNEN_MASK (0x200000U)
3375#define CAN_MCR_WRNEN_SHIFT (21U)
3376/* WRNEN - Warning Interrupt Enable
3377 * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96.
3378 * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
3379 */
3380#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
3381#define CAN_MCR_SLFWAK_MASK (0x400000U)
3382#define CAN_MCR_SLFWAK_SHIFT (22U)
3383/* SLFWAK - Self Wake Up
3384 * 0b1..FLEXCAN Self Wake Up feature is enabled
3385 * 0b0..FLEXCAN Self Wake Up feature is disabled
3386 */
3387#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
3388#define CAN_MCR_SUPV_MASK (0x800000U)
3389#define CAN_MCR_SUPV_SHIFT (23U)
3390/* SUPV - Supervisor Mode
3391 * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
3392 * behaves as though the access was done to an unimplemented register location
3393 * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
3394 */
3395#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
3396#define CAN_MCR_FRZACK_MASK (0x1000000U)
3397#define CAN_MCR_FRZACK_SHIFT (24U)
3398/* FRZACK - Freeze Mode Acknowledge
3399 * 0b1..FLEXCAN in Freeze Mode, prescaler stopped
3400 * 0b0..FLEXCAN not in Freeze Mode, prescaler running
3401 */
3402#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
3403#define CAN_MCR_SOFTRST_MASK (0x2000000U)
3404#define CAN_MCR_SOFTRST_SHIFT (25U)
3405/* SOFTRST - Soft Reset
3406 * 0b1..Reset the registers
3407 * 0b0..No reset request
3408 */
3409#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
3410#define CAN_MCR_WAKMSK_MASK (0x4000000U)
3411#define CAN_MCR_WAKMSK_SHIFT (26U)
3412/* WAKMSK - Wake Up Interrupt Mask
3413 * 0b1..Wake Up Interrupt is enabled
3414 * 0b0..Wake Up Interrupt is disabled
3415 */
3416#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
3417#define CAN_MCR_NOTRDY_MASK (0x8000000U)
3418#define CAN_MCR_NOTRDY_SHIFT (27U)
3419/* NOTRDY - FlexCAN Not Ready
3420 * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode
3421 * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
3422 */
3423#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
3424#define CAN_MCR_HALT_MASK (0x10000000U)
3425#define CAN_MCR_HALT_SHIFT (28U)
3426/* HALT - Halt FlexCAN
3427 * 0b1..Enters Freeze Mode if the FRZ bit is asserted.
3428 * 0b0..No Freeze Mode request.
3429 */
3430#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
3431#define CAN_MCR_RFEN_MASK (0x20000000U)
3432#define CAN_MCR_RFEN_SHIFT (29U)
3433/* RFEN - Legacy Rx FIFO Enable
3434 * 0b1..FIFO enabled
3435 * 0b0..FIFO not enabled
3436 */
3437#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
3438#define CAN_MCR_FRZ_MASK (0x40000000U)
3439#define CAN_MCR_FRZ_SHIFT (30U)
3440/* FRZ - Freeze Enable
3441 * 0b1..Enabled to enter Freeze Mode
3442 * 0b0..Not enabled to enter Freeze Mode
3443 */
3444#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
3445#define CAN_MCR_MDIS_MASK (0x80000000U)
3446#define CAN_MCR_MDIS_SHIFT (31U)
3447/* MDIS - Module Disable
3448 * 0b1..Disable the FLEXCAN module
3449 * 0b0..Enable the FLEXCAN module
3450 */
3451#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
3452/* @} */
3453
3454/* @name CTRL1 - Control 1 Register..Control 1 register */
3455/* @{ */
3456#define CAN_CTRL1_PROPSEG_MASK (0x7U)
3457#define CAN_CTRL1_PROPSEG_SHIFT (0U)
3458#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
3459#define CAN_CTRL1_LOM_MASK (0x8U)
3460#define CAN_CTRL1_LOM_SHIFT (3U)
3461/* LOM - Listen-Only Mode
3462 * 0b1..FLEXCAN module operates in Listen Only Mode
3463 * 0b0..Listen Only Mode is deactivated
3464 */
3465#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
3466#define CAN_CTRL1_LBUF_MASK (0x10U)
3467#define CAN_CTRL1_LBUF_SHIFT (4U)
3468/* LBUF - Lowest Buffer Transmitted First
3469 * 0b1..Lowest number buffer is transmitted first
3470 * 0b0..Buffer with highest priority is transmitted first
3471 */
3472#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
3473#define CAN_CTRL1_TSYN_MASK (0x20U)
3474#define CAN_CTRL1_TSYN_SHIFT (5U)
3475/* TSYN - Timer Sync
3476 * 0b1..Timer Sync feature enabled
3477 * 0b0..Timer Sync feature disabled
3478 */
3479#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
3480#define CAN_CTRL1_BOFFREC_MASK (0x40U)
3481#define CAN_CTRL1_BOFFREC_SHIFT (6U)
3482/* BOFFREC - Bus Off Recovery
3483 * 0b1..Automatic recovering from Bus Off state disabled
3484 * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
3485 */
3486#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
3487#define CAN_CTRL1_SMP_MASK (0x80U)
3488#define CAN_CTRL1_SMP_SHIFT (7U)
3489/* SMP - CAN Bit Sampling
3490 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2
3491 * preceding samples, a majority rule is used
3492 * 0b0..Just one sample is used to determine the bit value
3493 */
3494#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
3495#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
3496#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
3497/* RWRNMSK - Rx Warning Interrupt Mask
3498 * 0b1..Rx Warning Interrupt enabled
3499 * 0b0..Rx Warning Interrupt disabled
3500 */
3501#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
3502#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
3503#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
3504/* TWRNMSK - Tx Warning Interrupt Mask
3505 * 0b1..Tx Warning Interrupt enabled
3506 * 0b0..Tx Warning Interrupt disabled
3507 */
3508#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
3509#define CAN_CTRL1_LPB_MASK (0x1000U)
3510#define CAN_CTRL1_LPB_SHIFT (12U)
3511/* LPB - Loop Back Mode
3512 * 0b1..Loop Back enabled
3513 * 0b0..Loop Back disabled
3514 */
3515#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
3516#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
3517#define CAN_CTRL1_CLKSRC_SHIFT (13U)
3518/* CLKSRC - CAN Engine Clock Source
3519 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
3520 * 0b1..The CAN engine clock source is the peripheral clock.
3521 */
3522#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
3523#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
3524#define CAN_CTRL1_ERRMSK_SHIFT (14U)
3525/* ERRMSK - Error Interrupt Mask
3526 * 0b1..Error interrupt enabled
3527 * 0b0..Error interrupt disabled
3528 */
3529#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
3530#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
3531#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
3532/* BOFFMSK - Bus Off Interrupt Mask
3533 * 0b1..Bus Off interrupt enabled
3534 * 0b0..Bus Off interrupt disabled
3535 */
3536#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
3537#define CAN_CTRL1_PSEG2_MASK (0x70000U)
3538#define CAN_CTRL1_PSEG2_SHIFT (16U)
3539#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
3540#define CAN_CTRL1_PSEG1_MASK (0x380000U)
3541#define CAN_CTRL1_PSEG1_SHIFT (19U)
3542#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
3543#define CAN_CTRL1_RJW_MASK (0xC00000U)
3544#define CAN_CTRL1_RJW_SHIFT (22U)
3545#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
3546#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
3547#define CAN_CTRL1_PRESDIV_SHIFT (24U)
3548#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
3549/* @} */
3550
3551/* @name TIMER - Free Running Timer Register..Free Running Timer */
3552/* @{ */
3553#define CAN_TIMER_TIMER_MASK (0xFFFFU)
3554#define CAN_TIMER_TIMER_SHIFT (0U)
3555#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
3556/* @} */
3557
3558/* @name RXMGMASK - Rx Mailboxes Global Mask Register */
3559/* @{ */
3560#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
3561#define CAN_RXMGMASK_MG_SHIFT (0U)
3562/* MG - Rx Mailboxes Global Mask Bits
3563 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received
3564 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3565 */
3566#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
3567/* @} */
3568
3569/* @name RX14MASK - Rx Buffer 14 Mask Register..Rx 14 Mask register */
3570/* @{ */
3571#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
3572#define CAN_RX14MASK_RX14M_SHIFT (0U)
3573/* RX14M - Rx Buffer 14 Mask Bits
3574 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3575 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3576 */
3577#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
3578/* @} */
3579
3580/* @name RX15MASK - Rx Buffer 15 Mask Register..Rx 15 Mask register */
3581/* @{ */
3582#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
3583#define CAN_RX15MASK_RX15M_SHIFT (0U)
3584/* RX15M - Rx Buffer 15 Mask Bits
3585 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3586 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3587 */
3588#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
3589/* @} */
3590
3591/* @name ECR - Error Counter Register..Error Counter */
3592/* @{ */
3593#define CAN_ECR_TXERRCNT_MASK (0xFFU)
3594#define CAN_ECR_TXERRCNT_SHIFT (0U)
3595#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
3596#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
3597#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
3598#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
3599#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
3600#define CAN_ECR_RXERRCNT_SHIFT (8U)
3601#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
3602#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
3603#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
3604#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
3605#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
3606#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
3607#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
3608#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
3609#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
3610#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
3611/* @} */
3612
3613/* @name ESR1 - Error and Status 1 Register..Error and Status 1 register */
3614/* @{ */
3615#define CAN_ESR1_WAKINT_MASK (0x1U)
3616#define CAN_ESR1_WAKINT_SHIFT (0U)
3617/* WAKINT - Wake-Up Interrupt
3618 * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode
3619 * 0b0..No such occurrence
3620 */
3621#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
3622#define CAN_ESR1_ERRINT_MASK (0x2U)
3623#define CAN_ESR1_ERRINT_SHIFT (1U)
3624/* ERRINT - Error Interrupt
3625 * 0b1..Indicates setting of any Error Bit in the Error and Status Register
3626 * 0b0..No such occurrence
3627 */
3628#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
3629#define CAN_ESR1_BOFFINT_MASK (0x4U)
3630#define CAN_ESR1_BOFFINT_SHIFT (2U)
3631/* BOFFINT - Bus Off Interrupt
3632 * 0b1..FLEXCAN module entered 'Bus Off' state
3633 * 0b0..No such occurrence
3634 */
3635#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
3636#define CAN_ESR1_RX_MASK (0x8U)
3637#define CAN_ESR1_RX_SHIFT (3U)
3638/* RX - FlexCAN In Reception
3639 * 0b1..FLEXCAN is transmitting a message
3640 * 0b0..FLEXCAN is receiving a message
3641 */
3642#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
3643#define CAN_ESR1_FLTCONF_MASK (0x30U)
3644#define CAN_ESR1_FLTCONF_SHIFT (4U)
3645/* FLTCONF - Fault Confinement State
3646 * 0b00..Error Active
3647 * 0b01..Error Passive
3648 * 0b1x..Bus off
3649 */
3650#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
3651#define CAN_ESR1_TX_MASK (0x40U)
3652#define CAN_ESR1_TX_SHIFT (6U)
3653/* TX - FlexCAN In Transmission
3654 * 0b1..FLEXCAN is transmitting a message
3655 * 0b0..FLEXCAN is receiving a message
3656 */
3657#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
3658#define CAN_ESR1_IDLE_MASK (0x80U)
3659#define CAN_ESR1_IDLE_SHIFT (7U)
3660/* IDLE - IDLE
3661 * 0b1..CAN bus is now IDLE
3662 * 0b0..No such occurrence
3663 */
3664#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
3665#define CAN_ESR1_RXWRN_MASK (0x100U)
3666#define CAN_ESR1_RXWRN_SHIFT (8U)
3667/* RXWRN - Rx Error Warning
3668 * 0b1..Rx_Err_Counter >= 96
3669 * 0b0..No such occurrence
3670 */
3671#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
3672#define CAN_ESR1_TXWRN_MASK (0x200U)
3673#define CAN_ESR1_TXWRN_SHIFT (9U)
3674/* TXWRN - TX Error Warning
3675 * 0b1..TX_Err_Counter >= 96
3676 * 0b0..No such occurrence
3677 */
3678#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
3679#define CAN_ESR1_STFERR_MASK (0x400U)
3680#define CAN_ESR1_STFERR_SHIFT (10U)
3681/* STFERR - Stuffing Error
3682 * 0b1..A Stuffing Error occurred since last read of this register.
3683 * 0b0..No such occurrence.
3684 */
3685#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
3686#define CAN_ESR1_FRMERR_MASK (0x800U)
3687#define CAN_ESR1_FRMERR_SHIFT (11U)
3688/* FRMERR - Form Error
3689 * 0b1..A Form Error occurred since last read of this register
3690 * 0b0..No such occurrence
3691 */
3692#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
3693#define CAN_ESR1_CRCERR_MASK (0x1000U)
3694#define CAN_ESR1_CRCERR_SHIFT (12U)
3695/* CRCERR - Cyclic Redundancy Check Error
3696 * 0b1..A CRC error occurred since last read of this register.
3697 * 0b0..No such occurrence
3698 */
3699#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
3700#define CAN_ESR1_ACKERR_MASK (0x2000U)
3701#define CAN_ESR1_ACKERR_SHIFT (13U)
3702/* ACKERR - Acknowledge Error
3703 * 0b1..An ACK error occurred since last read of this register
3704 * 0b0..No such occurrence
3705 */
3706#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
3707#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
3708#define CAN_ESR1_BIT0ERR_SHIFT (14U)
3709/* BIT0ERR - Bit0 Error
3710 * 0b1..At least one bit sent as dominant is received as recessive
3711 * 0b0..No such occurrence
3712 */
3713#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
3714#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
3715#define CAN_ESR1_BIT1ERR_SHIFT (15U)
3716/* BIT1ERR - Bit1 Error
3717 * 0b1..At least one bit sent as recessive is received as dominant
3718 * 0b0..No such occurrence
3719 */
3720#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
3721#define CAN_ESR1_RWRNINT_MASK (0x10000U)
3722#define CAN_ESR1_RWRNINT_SHIFT (16U)
3723/* RWRNINT - Rx Warning Interrupt Flag
3724 * 0b1..The Rx error counter transition from < 96 to >= 96
3725 * 0b0..No such occurrence
3726 */
3727#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
3728#define CAN_ESR1_TWRNINT_MASK (0x20000U)
3729#define CAN_ESR1_TWRNINT_SHIFT (17U)
3730/* TWRNINT - Tx Warning Interrupt Flag
3731 * 0b1..The Tx error counter transition from < 96 to >= 96
3732 * 0b0..No such occurrence
3733 */
3734#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
3735#define CAN_ESR1_SYNCH_MASK (0x40000U)
3736#define CAN_ESR1_SYNCH_SHIFT (18U)
3737/* SYNCH - CAN Synchronization Status
3738 * 0b1..FlexCAN is synchronized to the CAN bus
3739 * 0b0..FlexCAN is not synchronized to the CAN bus
3740 */
3741#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
3742#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
3743#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
3744/* BOFFDONEINT - Bus Off Done Interrupt
3745 * 0b0..No such occurrence.
3746 * 0b1..FlexCAN module has completed Bus Off process.
3747 */
3748#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
3749#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
3750#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
3751/* ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set
3752 * 0b0..No such occurrence.
3753 * 0b1..Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set.
3754 */
3755#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
3756#define CAN_ESR1_ERROVR_MASK (0x200000U)
3757#define CAN_ESR1_ERROVR_SHIFT (21U)
3758/* ERROVR - Error Overrun bit
3759 * 0b0..Overrun has not occurred.
3760 * 0b1..Overrun has occurred.
3761 */
3762#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
3763#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
3764#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
3765/* STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
3766 * 0b0..No such occurrence.
3767 * 0b1..A Stuffing Error occurred since last read of this register.
3768 */
3769#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
3770#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
3771#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
3772/* FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
3773 * 0b0..No such occurrence.
3774 * 0b1..A Form Error occurred since last read of this register.
3775 */
3776#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
3777#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
3778#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
3779/* CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
3780 * 0b0..No such occurrence.
3781 * 0b1..A CRC error occurred since last read of this register.
3782 */
3783#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
3784#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
3785#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
3786/* BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
3787 * 0b0..No such occurrence.
3788 * 0b1..At least one bit sent as dominant is received as recessive.
3789 */
3790#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
3791#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
3792#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
3793/* BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
3794 * 0b0..No such occurrence.
3795 * 0b1..At least one bit sent as recessive is received as dominant.
3796 */
3797#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
3798/* @} */
3799
3800/* @name IMASK2 - Interrupt Masks 2 Register..Interrupt Masks 2 register */
3801/* @{ */
3802#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
3803#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
3804#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
3805#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
3806#define CAN_IMASK2_BUFHM_SHIFT (0U)
3807/* BUFHM
3808 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
3809 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
3810 */
3811#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
3812/* @} */
3813
3814/* @name IMASK1 - Interrupt Masks 1 Register..Interrupt Masks 1 register */
3815/* @{ */
3816#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
3817#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
3818#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
3819#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
3820#define CAN_IMASK1_BUFLM_SHIFT (0U)
3821/* BUFLM
3822 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
3823 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
3824 */
3825#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
3826/* @} */
3827
3828/* @name IFLAG2 - Interrupt Flags 2 Register..Interrupt Flags 2 register */
3829/* @{ */
3830#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
3831#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
3832#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
3833#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
3834#define CAN_IFLAG2_BUFHI_SHIFT (0U)
3835/* BUFHI
3836 * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception
3837 * 0b00000000000000000000000000000000..No such occurrence
3838 */
3839#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
3840/* @} */
3841
3842/* @name IFLAG1 - Interrupt Flags 1 Register..Interrupt Flags 1 register */
3843/* @{ */
3844#define CAN_IFLAG1_BUF0I_MASK (0x1U)
3845#define CAN_IFLAG1_BUF0I_SHIFT (0U)
3846/* BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit
3847 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0.
3848 * 0b1..The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0.
3849 */
3850#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
3851#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
3852#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
3853/* BUF4TO0I
3854 * 0b00001..Corresponding MB completed transmission/reception
3855 * 0b00000..No such occurrence
3856 */
3857#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
3858#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
3859#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
3860#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
3861#define CAN_IFLAG1_BUF5I_MASK (0x20U)
3862#define CAN_IFLAG1_BUF5I_SHIFT (5U)
3863/* BUF5I - Buffer MB5 Interrupt Or "Frames available in Legacy Rx FIFO"
3864 * 0b1..MB5 completed transmission/reception or frames available in the FIFO
3865 * 0b0..No such occurrence
3866 */
3867#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
3868#define CAN_IFLAG1_BUF6I_MASK (0x40U)
3869#define CAN_IFLAG1_BUF6I_SHIFT (6U)
3870/* BUF6I - Buffer MB6 Interrupt Or "Legacy Rx FIFO Warning"
3871 * 0b1..MB6 completed transmission/reception or FIFO almost full
3872 * 0b0..No such occurrence
3873 */
3874#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
3875#define CAN_IFLAG1_BUF7I_MASK (0x80U)
3876#define CAN_IFLAG1_BUF7I_SHIFT (7U)
3877/* BUF7I - Buffer MB7 Interrupt Or "Legacy Rx FIFO Overflow"
3878 * 0b1..MB7 completed transmission/reception or FIFO overflow
3879 * 0b0..No such occurrence
3880 */
3881#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
3882#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
3883#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
3884/* BUF31TO8I - Buffer MBi Interrupt
3885 * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception
3886 * 0b000000000000000000000000..No such occurrence
3887 */
3888#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
3889/* @} */
3890
3891/* @name CTRL2 - Control 2 Register..Control 2 register */
3892/* @{ */
3893#define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U)
3894#define CAN_CTRL2_TSTAMPCAP_SHIFT (6U)
3895/* TSTAMPCAP - Time Stamp Capture Point
3896 * 0b00..The high resolution time stamp capture is disabled
3897 * 0b01..The high resolution time stamp is captured in the end of the CAN frame
3898 * 0b10..The high resolution time stamp is captured in the start of the CAN frame
3899 * 0b11..The high resolution time stamp is captured in the start of frame for classical CAN frames and in res bit for CAN FD frames
3900 */
3901#define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK)
3902#define CAN_CTRL2_MBTSBASE_MASK (0x300U)
3903#define CAN_CTRL2_MBTSBASE_SHIFT (8U)
3904/* MBTSBASE - Message Buffer Time Stamp Base
3905 * 0b00..Message Buffer Time Stamp base is CAN_TIMER
3906 * 0b01..Message Buffer Time Stamp base is lower 16-bits of high resolution timer
3907 * 0b10..Message Buffer Time Stamp base is upper 16-bits of high resolution timerT
3908 * 0b11..Reserved.
3909 */
3910#define CAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK)
3911#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
3912#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
3913/* EDFLTDIS - Edge Filter Disable
3914 * 0b0..Edge Filter is enabled
3915 * 0b1..Edge Filter is disabled
3916 */
3917#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
3918#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
3919#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
3920/* ISOCANFDEN - ISO CAN FD Enable
3921 * 0b0..FlexCAN operates using the non-ISO CAN FD protocol.
3922 * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
3923 */
3924#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
3925#define CAN_CTRL2_BTE_MASK (0x2000U)
3926#define CAN_CTRL2_BTE_SHIFT (13U)
3927/* BTE - Bit Timing Expansion enable
3928 * 0b0..CAN Bit timing expansion is disabled.
3929 * 0b1..CAN bit timing expansion is enabled.
3930 */
3931#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)
3932#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
3933#define CAN_CTRL2_PREXCEN_SHIFT (14U)
3934/* PREXCEN - Protocol Exception Enable
3935 * 0b0..Protocol Exception is disabled.
3936 * 0b1..Protocol Exception is enabled.
3937 */
3938#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
3939#define CAN_CTRL2_TIMER_SRC_MASK (0x8000U)
3940#define CAN_CTRL2_TIMER_SRC_SHIFT (15U)
3941/* TIMER_SRC - Timer Source
3942 * 0b0..The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
3943 * 0b1..The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal
3944 * to the baud rate on the CAN bus, or a different value as required. See the device specific section for
3945 * details about the external time tick.
3946 */
3947#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
3948#define CAN_CTRL2_EACEN_MASK (0x10000U)
3949#define CAN_CTRL2_EACEN_SHIFT (16U)
3950/* EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
3951 * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within
3952 * the incoming frame. Mask bits do apply.
3953 * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
3954 */
3955#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
3956#define CAN_CTRL2_RRS_MASK (0x20000U)
3957#define CAN_CTRL2_RRS_SHIFT (17U)
3958/* RRS - Remote Request Storing
3959 * 0b1..Remote Request Frame is stored
3960 * 0b0..Remote Response Frame is generated
3961 */
3962#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
3963#define CAN_CTRL2_MRP_MASK (0x40000U)
3964#define CAN_CTRL2_MRP_SHIFT (18U)
3965/* MRP - Mailboxes Reception Priority
3966 * 0b1..Matching starts from Mailboxes and continues on Rx FIFO
3967 * 0b0..Matching starts from Rx FIFO and continues on Mailboxes
3968 */
3969#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
3970#define CAN_CTRL2_TASD_MASK (0xF80000U)
3971#define CAN_CTRL2_TASD_SHIFT (19U)
3972#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
3973#define CAN_CTRL2_RFFN_MASK (0xF000000U)
3974#define CAN_CTRL2_RFFN_SHIFT (24U)
3975#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
3976#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
3977#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
3978/* WRMFRZ
3979 * 0b1..Enable unrestricted write access to FlexCAN memory
3980 * 0b0..Keep the write access restricted in some regions of FlexCAN memory
3981 */
3982#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
3983#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
3984#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
3985/* BOFFDONEMSK - Bus Off Done Interrupt Mask
3986 * 0b0..Bus Off Done interrupt disabled.
3987 * 0b1..Bus Off Done interrupt enabled.
3988 */
3989#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
3990#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
3991#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
3992/* ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames
3993 * 0b0..ERRINT_FAST Error interrupt disabled.
3994 * 0b1..ERRINT_FAST Error interrupt enabled.
3995 */
3996#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
3997/* @} */
3998
3999/* @name ESR2 - Error and Status 2 Register..Error and Status 2 register */
4000/* @{ */
4001#define CAN_ESR2_IMB_MASK (0x2000U)
4002#define CAN_ESR2_IMB_SHIFT (13U)
4003/* IMB - Inactive Mailbox
4004 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
4005 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
4006 */
4007#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4008#define CAN_ESR2_VPS_MASK (0x4000U)
4009#define CAN_ESR2_VPS_SHIFT (14U)
4010/* VPS - Valid Priority Status
4011 * 0b1..Contents of IMB and LPTM are valid
4012 * 0b0..Contents of IMB and LPTM are invalid
4013 */
4014#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4015#define CAN_ESR2_LPTM_MASK (0x7F0000U)
4016#define CAN_ESR2_LPTM_SHIFT (16U)
4017#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4018/* @} */
4019
4020/* @name CRCR - CRC Register */
4021/* @{ */
4022#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
4023#define CAN_CRCR_TXCRC_SHIFT (0U)
4024#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4025#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
4026#define CAN_CRCR_MBCRC_SHIFT (16U)
4027#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4028/* @} */
4029
4030/* @name RXFGMASK - Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register */
4031/* @{ */
4032#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
4033#define CAN_RXFGMASK_FGM_SHIFT (0U)
4034/* FGM - Legacy Rx FIFO Global Mask Bits
4035 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
4036 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"
4037 */
4038#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4039/* @} */
4040
4041/* @name RXFIR - Rx FIFO Information Register..Legacy Rx FIFO Information Register */
4042/* @{ */
4043#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
4044#define CAN_RXFIR_IDHIT_SHIFT (0U)
4045#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4046/* @} */
4047
4048/* @name CBT - CAN Bit Timing Register */
4049/* @{ */
4050#define CAN_CBT_EPSEG2_MASK (0x1FU)
4051#define CAN_CBT_EPSEG2_SHIFT (0U)
4052#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
4053#define CAN_CBT_EPSEG1_MASK (0x3E0U)
4054#define CAN_CBT_EPSEG1_SHIFT (5U)
4055#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
4056#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
4057#define CAN_CBT_EPROPSEG_SHIFT (10U)
4058#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
4059#define CAN_CBT_ERJW_MASK (0x1F0000U)
4060#define CAN_CBT_ERJW_SHIFT (16U)
4061#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
4062#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
4063#define CAN_CBT_EPRESDIV_SHIFT (21U)
4064#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
4065#define CAN_CBT_BTF_MASK (0x80000000U)
4066#define CAN_CBT_BTF_SHIFT (31U)
4067/* BTF - Bit Timing Format Enable
4068 * 0b0..Extended bit time definitions disabled.
4069 * 0b1..Extended bit time definitions enabled.
4070 */
4071#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
4072/* @} */
4073
4074/* @name DBG1 - Debug 1 register */
4075/* @{ */
4076#define CAN_DBG1_CFSM_MASK (0x3FU)
4077#define CAN_DBG1_CFSM_SHIFT (0U)
4078#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
4079#define CAN_DBG1_CBN_MASK (0x1F000000U)
4080#define CAN_DBG1_CBN_SHIFT (24U)
4081#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
4082/* @} */
4083
4084/* @name DBG2 - Debug 2 register */
4085/* @{ */
4086#define CAN_DBG2_RMP_MASK (0x7FU)
4087#define CAN_DBG2_RMP_SHIFT (0U)
4088#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
4089#define CAN_DBG2_MPP_MASK (0x80U)
4090#define CAN_DBG2_MPP_SHIFT (7U)
4091/* MPP - Matching Process in Progress
4092 * 0b0..No matching process ongoing.
4093 * 0b1..Matching process is in progress.
4094 */
4095#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
4096#define CAN_DBG2_TAP_MASK (0x7F00U)
4097#define CAN_DBG2_TAP_SHIFT (8U)
4098#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
4099#define CAN_DBG2_APP_MASK (0x8000U)
4100#define CAN_DBG2_APP_SHIFT (15U)
4101/* APP - Arbitration Process in Progress
4102 * 0b0..No matching process ongoing.
4103 * 0b1..Matching process is in progress.
4104 */
4105#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
4106/* @} */
4107
4108/* The count of CAN_CS */
4109#define CAN_CS_COUNT_MB8B (64U)
4110
4111/* The count of CAN_ID */
4112#define CAN_ID_COUNT_MB8B (64U)
4113
4114/* The count of CAN_WORD */
4115#define CAN_WORD_COUNT_MB8B (64U)
4116
4117/* The count of CAN_WORD */
4118#define CAN_WORD_COUNT_MB8B2 (2U)
4119
4120/* The count of CAN_CS */
4121#define CAN_CS_COUNT_MB16B (42U)
4122
4123/* The count of CAN_ID */
4124#define CAN_ID_COUNT_MB16B (42U)
4125
4126/* The count of CAN_WORD */
4127#define CAN_WORD_COUNT_MB16B (42U)
4128
4129/* The count of CAN_WORD */
4130#define CAN_WORD_COUNT_MB16B2 (4U)
4131
4132/* The count of CAN_CS */
4133#define CAN_CS_COUNT_MB32B (24U)
4134
4135/* The count of CAN_ID */
4136#define CAN_ID_COUNT_MB32B (24U)
4137
4138/* The count of CAN_WORD */
4139#define CAN_WORD_COUNT_MB32B (24U)
4140
4141/* The count of CAN_WORD */
4142#define CAN_WORD_COUNT_MB32B2 (8U)
4143
4144/* @name CS - Message Buffer 0 CS Register..Message Buffer 13 CS Register */
4145/* @{ */
4146#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
4147#define CAN_CS_TIME_STAMP_SHIFT (0U)
4148#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4149#define CAN_CS_DLC_MASK (0xF0000U)
4150#define CAN_CS_DLC_SHIFT (16U)
4151#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4152#define CAN_CS_RTR_MASK (0x100000U)
4153#define CAN_CS_RTR_SHIFT (20U)
4154#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4155#define CAN_CS_IDE_MASK (0x200000U)
4156#define CAN_CS_IDE_SHIFT (21U)
4157#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4158#define CAN_CS_SRR_MASK (0x400000U)
4159#define CAN_CS_SRR_SHIFT (22U)
4160#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4161#define CAN_CS_CODE_MASK (0xF000000U)
4162#define CAN_CS_CODE_SHIFT (24U)
4163#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4164#define CAN_CS_ESI_MASK (0x20000000U)
4165#define CAN_CS_ESI_SHIFT (29U)
4166#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
4167#define CAN_CS_BRS_MASK (0x40000000U)
4168#define CAN_CS_BRS_SHIFT (30U)
4169#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
4170#define CAN_CS_EDL_MASK (0x80000000U)
4171#define CAN_CS_EDL_SHIFT (31U)
4172#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
4173/* @} */
4174
4175/* The count of CAN_CS */
4176#define CAN_CS_COUNT_MB64B (14U)
4177
4178/* @name ID - Message Buffer 0 ID Register..Message Buffer 13 ID Register */
4179/* @{ */
4180#define CAN_ID_EXT_MASK (0x3FFFFU)
4181#define CAN_ID_EXT_SHIFT (0U)
4182#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4183#define CAN_ID_STD_MASK (0x1FFC0000U)
4184#define CAN_ID_STD_SHIFT (18U)
4185#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4186#define CAN_ID_PRIO_MASK (0xE0000000U)
4187#define CAN_ID_PRIO_SHIFT (29U)
4188#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4189/* @} */
4190
4191/* The count of CAN_ID */
4192#define CAN_ID_COUNT_MB64B (14U)
4193
4194/* @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register */
4195/* @{ */
4196#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU)
4197#define CAN_WORD_DATA_BYTE_3_SHIFT (0U)
4198#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
4199#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU)
4200#define CAN_WORD_DATA_BYTE_7_SHIFT (0U)
4201#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
4202#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU)
4203#define CAN_WORD_DATA_BYTE_11_SHIFT (0U)
4204#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
4205#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU)
4206#define CAN_WORD_DATA_BYTE_15_SHIFT (0U)
4207#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
4208#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU)
4209#define CAN_WORD_DATA_BYTE_19_SHIFT (0U)
4210#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
4211#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU)
4212#define CAN_WORD_DATA_BYTE_23_SHIFT (0U)
4213#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
4214#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU)
4215#define CAN_WORD_DATA_BYTE_27_SHIFT (0U)
4216#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
4217#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU)
4218#define CAN_WORD_DATA_BYTE_31_SHIFT (0U)
4219#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
4220#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU)
4221#define CAN_WORD_DATA_BYTE_35_SHIFT (0U)
4222#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
4223#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU)
4224#define CAN_WORD_DATA_BYTE_39_SHIFT (0U)
4225#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
4226#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU)
4227#define CAN_WORD_DATA_BYTE_43_SHIFT (0U)
4228#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
4229#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU)
4230#define CAN_WORD_DATA_BYTE_47_SHIFT (0U)
4231#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
4232#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU)
4233#define CAN_WORD_DATA_BYTE_51_SHIFT (0U)
4234#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
4235#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU)
4236#define CAN_WORD_DATA_BYTE_55_SHIFT (0U)
4237#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
4238#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU)
4239#define CAN_WORD_DATA_BYTE_59_SHIFT (0U)
4240#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
4241#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU)
4242#define CAN_WORD_DATA_BYTE_63_SHIFT (0U)
4243#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
4244#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)
4245#define CAN_WORD_DATA_BYTE_2_SHIFT (8U)
4246#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
4247#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)
4248#define CAN_WORD_DATA_BYTE_6_SHIFT (8U)
4249#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
4250#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)
4251#define CAN_WORD_DATA_BYTE_10_SHIFT (8U)
4252#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
4253#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)
4254#define CAN_WORD_DATA_BYTE_14_SHIFT (8U)
4255#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
4256#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)
4257#define CAN_WORD_DATA_BYTE_18_SHIFT (8U)
4258#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
4259#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)
4260#define CAN_WORD_DATA_BYTE_22_SHIFT (8U)
4261#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
4262#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)
4263#define CAN_WORD_DATA_BYTE_26_SHIFT (8U)
4264#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
4265#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)
4266#define CAN_WORD_DATA_BYTE_30_SHIFT (8U)
4267#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
4268#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)
4269#define CAN_WORD_DATA_BYTE_34_SHIFT (8U)
4270#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
4271#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)
4272#define CAN_WORD_DATA_BYTE_38_SHIFT (8U)
4273#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
4274#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)
4275#define CAN_WORD_DATA_BYTE_42_SHIFT (8U)
4276#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
4277#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)
4278#define CAN_WORD_DATA_BYTE_46_SHIFT (8U)
4279#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
4280#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)
4281#define CAN_WORD_DATA_BYTE_50_SHIFT (8U)
4282#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
4283#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)
4284#define CAN_WORD_DATA_BYTE_54_SHIFT (8U)
4285#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
4286#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)
4287#define CAN_WORD_DATA_BYTE_58_SHIFT (8U)
4288#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
4289#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)
4290#define CAN_WORD_DATA_BYTE_62_SHIFT (8U)
4291#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
4292#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)
4293#define CAN_WORD_DATA_BYTE_1_SHIFT (16U)
4294#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
4295#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)
4296#define CAN_WORD_DATA_BYTE_5_SHIFT (16U)
4297#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
4298#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)
4299#define CAN_WORD_DATA_BYTE_9_SHIFT (16U)
4300#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
4301#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)
4302#define CAN_WORD_DATA_BYTE_13_SHIFT (16U)
4303#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
4304#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)
4305#define CAN_WORD_DATA_BYTE_17_SHIFT (16U)
4306#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
4307#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)
4308#define CAN_WORD_DATA_BYTE_21_SHIFT (16U)
4309#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
4310#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)
4311#define CAN_WORD_DATA_BYTE_25_SHIFT (16U)
4312#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
4313#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)
4314#define CAN_WORD_DATA_BYTE_29_SHIFT (16U)
4315#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
4316#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)
4317#define CAN_WORD_DATA_BYTE_33_SHIFT (16U)
4318#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
4319#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)
4320#define CAN_WORD_DATA_BYTE_37_SHIFT (16U)
4321#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
4322#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)
4323#define CAN_WORD_DATA_BYTE_41_SHIFT (16U)
4324#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
4325#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)
4326#define CAN_WORD_DATA_BYTE_45_SHIFT (16U)
4327#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
4328#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)
4329#define CAN_WORD_DATA_BYTE_49_SHIFT (16U)
4330#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
4331#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)
4332#define CAN_WORD_DATA_BYTE_53_SHIFT (16U)
4333#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
4334#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)
4335#define CAN_WORD_DATA_BYTE_57_SHIFT (16U)
4336#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
4337#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)
4338#define CAN_WORD_DATA_BYTE_61_SHIFT (16U)
4339#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
4340#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)
4341#define CAN_WORD_DATA_BYTE_0_SHIFT (24U)
4342#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
4343#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)
4344#define CAN_WORD_DATA_BYTE_4_SHIFT (24U)
4345#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
4346#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)
4347#define CAN_WORD_DATA_BYTE_8_SHIFT (24U)
4348#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
4349#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)
4350#define CAN_WORD_DATA_BYTE_12_SHIFT (24U)
4351#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
4352#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)
4353#define CAN_WORD_DATA_BYTE_16_SHIFT (24U)
4354#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
4355#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)
4356#define CAN_WORD_DATA_BYTE_20_SHIFT (24U)
4357#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
4358#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)
4359#define CAN_WORD_DATA_BYTE_24_SHIFT (24U)
4360#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
4361#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)
4362#define CAN_WORD_DATA_BYTE_28_SHIFT (24U)
4363#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
4364#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)
4365#define CAN_WORD_DATA_BYTE_32_SHIFT (24U)
4366#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
4367#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)
4368#define CAN_WORD_DATA_BYTE_36_SHIFT (24U)
4369#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
4370#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)
4371#define CAN_WORD_DATA_BYTE_40_SHIFT (24U)
4372#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
4373#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)
4374#define CAN_WORD_DATA_BYTE_44_SHIFT (24U)
4375#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
4376#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)
4377#define CAN_WORD_DATA_BYTE_48_SHIFT (24U)
4378#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
4379#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)
4380#define CAN_WORD_DATA_BYTE_52_SHIFT (24U)
4381#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
4382#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)
4383#define CAN_WORD_DATA_BYTE_56_SHIFT (24U)
4384#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
4385#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)
4386#define CAN_WORD_DATA_BYTE_60_SHIFT (24U)
4387#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
4388/* @} */
4389
4390/* The count of CAN_WORD */
4391#define CAN_WORD_COUNT_MB64B (14U)
4392
4393/* The count of CAN_WORD */
4394#define CAN_WORD_COUNT_MB64B2 (16U)
4395
4396/* The count of CAN_CS */
4397#define CAN_CS_COUNT (64U)
4398
4399/* The count of CAN_ID */
4400#define CAN_ID_COUNT (64U)
4401
4402/* @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
4403/* @{ */
4404#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4405#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4406#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4407#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4408#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4409#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4410#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4411#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4412#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4413#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4414#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4415#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4416/* @} */
4417
4418/* The count of CAN_WORD0 */
4419#define CAN_WORD0_COUNT (64U)
4420
4421/* @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
4422/* @{ */
4423#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4424#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4425#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4426#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4427#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4428#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4429#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4430#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4431#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4432#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4433#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4434#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4435/* @} */
4436
4437/* The count of CAN_WORD1 */
4438#define CAN_WORD1_COUNT (64U)
4439
4440/* @name RXIMR - Rx Individual Mask Registers */
4441/* @{ */
4442#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4443#define CAN_RXIMR_MI_SHIFT (0U)
4444/* MI - Individual Mask Bits
4445 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
4446 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
4447 */
4448#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
4449/* @} */
4450
4451/* The count of CAN_RXIMR */
4452#define CAN_RXIMR_COUNT (64U)
4453
4454/* @name GFWR - Glitch Filter Width Registers */
4455/* @{ */
4456#define CAN_GFWR_GFWR_MASK (0xFFU)
4457#define CAN_GFWR_GFWR_SHIFT (0U)
4458#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
4459/* @} */
4460
4461/* @name EPRS - Enhanced CAN Bit Timing Prescalers */
4462/* @{ */
4463#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU)
4464#define CAN_EPRS_ENPRESDIV_SHIFT (0U)
4465#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)
4466#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U)
4467#define CAN_EPRS_EDPRESDIV_SHIFT (16U)
4468#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
4469/* @} */
4470
4471/* @name ENCBT - Enhanced Nominal CAN Bit Timing */
4472/* @{ */
4473#define CAN_ENCBT_NTSEG1_MASK (0xFFU)
4474#define CAN_ENCBT_NTSEG1_SHIFT (0U)
4475#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)
4476#define CAN_ENCBT_NTSEG2_MASK (0x7F000U)
4477#define CAN_ENCBT_NTSEG2_SHIFT (12U)
4478#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)
4479#define CAN_ENCBT_NRJW_MASK (0x1FC00000U)
4480#define CAN_ENCBT_NRJW_SHIFT (22U)
4481#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
4482/* @} */
4483
4484/* @name EDCBT - Enhanced Data Phase CAN bit Timing */
4485/* @{ */
4486#define CAN_EDCBT_DTSEG1_MASK (0x1FU)
4487#define CAN_EDCBT_DTSEG1_SHIFT (0U)
4488#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)
4489#define CAN_EDCBT_DTSEG2_MASK (0xF000U)
4490#define CAN_EDCBT_DTSEG2_SHIFT (12U)
4491#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)
4492#define CAN_EDCBT_DRJW_MASK (0x3C00000U)
4493#define CAN_EDCBT_DRJW_SHIFT (22U)
4494#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
4495/* @} */
4496
4497/* @name ETDC - Enhanced Transceiver Delay Compensation */
4498/* @{ */
4499#define CAN_ETDC_ETDCVAL_MASK (0xFFU)
4500#define CAN_ETDC_ETDCVAL_SHIFT (0U)
4501#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)
4502#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U)
4503#define CAN_ETDC_ETDCOFF_SHIFT (16U)
4504#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)
4505#define CAN_ETDC_TDMDIS_MASK (0x80000000U)
4506#define CAN_ETDC_TDMDIS_SHIFT (31U)
4507/* TDMDIS - Transceiver Delay Measurement Disable
4508 * 0b0..TDC measurement is enabled
4509 * 0b1..TDC measurement is disabled
4510 */
4511#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)
4512/* @} */
4513
4514/* @name FDCTRL - CAN FD Control Register */
4515/* @{ */
4516#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
4517#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
4518#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
4519#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
4520#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
4521#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
4522#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
4523#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
4524/* TDCFAIL - Transceiver Delay Compensation Fail
4525 * 0b0..Measured loop delay is in range.
4526 * 0b1..Measured loop delay is out of range.
4527 */
4528#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
4529#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
4530#define CAN_FDCTRL_TDCEN_SHIFT (15U)
4531/* TDCEN - Transceiver Delay Compensation Enable
4532 * 0b0..TDC is disabled
4533 * 0b1..TDC is enabled
4534 */
4535#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
4536#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
4537#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
4538/* MBDSR0 - Message Buffer Data Size for Region 0
4539 * 0b00..Selects 8 bytes per Message Buffer.
4540 * 0b01..Selects 16 bytes per Message Buffer.
4541 * 0b10..Selects 32 bytes per Message Buffer.
4542 * 0b11..Selects 64 bytes per Message Buffer.
4543 */
4544#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
4545#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
4546#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
4547/* MBDSR1 - Message Buffer Data Size for Region 1
4548 * 0b00..Selects 8 bytes per Message Buffer.
4549 * 0b01..Selects 16 bytes per Message Buffer.
4550 * 0b10..Selects 32 bytes per Message Buffer.
4551 * 0b11..Selects 64 bytes per Message Buffer.
4552 */
4553#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
4554#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
4555#define CAN_FDCTRL_FDRATE_SHIFT (31U)
4556/* FDRATE - Bit Rate Switch Enable
4557 * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
4558 * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
4559 */
4560#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
4561/* @} */
4562
4563/* @name FDCBT - CAN FD Bit Timing Register */
4564/* @{ */
4565#define CAN_FDCBT_FPSEG2_MASK (0x7U)
4566#define CAN_FDCBT_FPSEG2_SHIFT (0U)
4567#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
4568#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
4569#define CAN_FDCBT_FPSEG1_SHIFT (5U)
4570#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
4571#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
4572#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
4573#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
4574#define CAN_FDCBT_FRJW_MASK (0x70000U)
4575#define CAN_FDCBT_FRJW_SHIFT (16U)
4576#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
4577#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
4578#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
4579#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
4580/* @} */
4581
4582/* @name FDCRC - CAN FD CRC Register */
4583/* @{ */
4584#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
4585#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
4586#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
4587#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
4588#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
4589#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
4590/* @} */
4591
4592/* @name ERFCR - Enhanced Rx FIFO Control Register */
4593/* @{ */
4594#define CAN_ERFCR_ERFWM_MASK (0x1FU)
4595#define CAN_ERFCR_ERFWM_SHIFT (0U)
4596#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)
4597#define CAN_ERFCR_NFE_MASK (0x3F00U)
4598#define CAN_ERFCR_NFE_SHIFT (8U)
4599#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)
4600#define CAN_ERFCR_NEXIF_MASK (0x7F0000U)
4601#define CAN_ERFCR_NEXIF_SHIFT (16U)
4602#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)
4603#define CAN_ERFCR_DMALW_MASK (0x7C000000U)
4604#define CAN_ERFCR_DMALW_SHIFT (26U)
4605#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)
4606#define CAN_ERFCR_ERFEN_MASK (0x80000000U)
4607#define CAN_ERFCR_ERFEN_SHIFT (31U)
4608/* ERFEN - Enhanced Rx FIFO enable
4609 * 0b0..Enhanced Rx FIFO is disabled
4610 * 0b1..Enhanced Rx FIFO is enabled
4611 */
4612#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
4613/* @} */
4614
4615/* @name ERFIER - Enhanced Rx FIFO Interrupt Enable register */
4616/* @{ */
4617#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U)
4618#define CAN_ERFIER_ERFDAIE_SHIFT (28U)
4619/* ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable
4620 * 0b0..Enhanced Rx FIFO Data Available Interrupt is disabled
4621 * 0b1..Enhanced Rx FIFO Data Available Interrupt is enabled
4622 */
4623#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)
4624#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U)
4625#define CAN_ERFIER_ERFWMIIE_SHIFT (29U)
4626/* ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable
4627 * 0b0..Enhanced Rx FIFO Watermark Interrupt is disabled
4628 * 0b1..Enhanced Rx FIFO Watermark Interrupt is enabled
4629 */
4630#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)
4631#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U)
4632#define CAN_ERFIER_ERFOVFIE_SHIFT (30U)
4633/* ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable
4634 * 0b0..Enhanced Rx FIFO Overflow is disabled
4635 * 0b1..Enhanced Rx FIFO Overflow is enabled
4636 */
4637#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)
4638#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U)
4639#define CAN_ERFIER_ERFUFWIE_SHIFT (31U)
4640/* ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable
4641 * 0b0..Enhanced Rx FIFO Underflow interrupt is disabled
4642 * 0b1..Enhanced Rx FIFO Underflow interrupt is enabled
4643 */
4644#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
4645/* @} */
4646
4647/* @name ERFSR - Enhanced Rx FIFO Status Register */
4648/* @{ */
4649#define CAN_ERFSR_ERFEL_MASK (0x3FU)
4650#define CAN_ERFSR_ERFEL_SHIFT (0U)
4651#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)
4652#define CAN_ERFSR_ERFF_MASK (0x10000U)
4653#define CAN_ERFSR_ERFF_SHIFT (16U)
4654/* ERFF - Enhanced Rx FIFO full
4655 * 0b0..Enhanced Rx FIFO is not full
4656 * 0b1..Enhanced Rx FIFO is full
4657 */
4658#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)
4659#define CAN_ERFSR_ERFE_MASK (0x20000U)
4660#define CAN_ERFSR_ERFE_SHIFT (17U)
4661/* ERFE - Enhanced Rx FIFO empty
4662 * 0b0..Enhanced Rx FIFO is not empty
4663 * 0b1..Enhanced Rx FIFO is empty
4664 */
4665#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)
4666#define CAN_ERFSR_ERFCLR_MASK (0x8000000U)
4667#define CAN_ERFSR_ERFCLR_SHIFT (27U)
4668/* ERFCLR - Enhanced Rx FIFO Clear
4669 * 0b0..No effect
4670 * 0b1..Clear Enhanced Rx FIFO content
4671 */
4672#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)
4673#define CAN_ERFSR_ERFDA_MASK (0x10000000U)
4674#define CAN_ERFSR_ERFDA_SHIFT (28U)
4675/* ERFDA - Enhanced Rx FIFO Data Available
4676 * 0b0..No such occurrence
4677 * 0b1..There is at least one message stored in Enhanced Rx FIFO
4678 */
4679#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)
4680#define CAN_ERFSR_ERFWMI_MASK (0x20000000U)
4681#define CAN_ERFSR_ERFWMI_SHIFT (29U)
4682/* ERFWMI - Enhanced Rx FIFO Watermark Indication
4683 * 0b0..No such occurrence
4684 * 0b1..The number of messages in FIFO is greater than the watermark
4685 */
4686#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
4687#define CAN_ERFSR_ERFOVF_MASK (0x40000000U)
4688#define CAN_ERFSR_ERFOVF_SHIFT (30U)
4689/* ERFOVF - Enhanced Rx FIFO Overflow
4690 * 0b0..No such occurrence
4691 * 0b1..Enhanced Rx FIFO overflow
4692 */
4693#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)
4694#define CAN_ERFSR_ERFUFW_MASK (0x80000000U)
4695#define CAN_ERFSR_ERFUFW_SHIFT (31U)
4696/* ERFUFW - Enhanced Rx FIFO Underflow
4697 * 0b0..No such occurrence
4698 * 0b1..Enhanced Rx FIFO underflow
4699 */
4700#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
4701/* @} */
4702
4703/* @name HR_TIME_STAMP - High Resolution Time Stamp */
4704/* @{ */
4705#define CAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU)
4706#define CAN_HR_TIME_STAMP_TS_SHIFT (0U)
4707#define CAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK)
4708/* @} */
4709
4710/* The count of CAN_HR_TIME_STAMP */
4711#define CAN_HR_TIME_STAMP_COUNT (64U)
4712
4713/* @name ERFFEL - Enhanced Rx FIFO Filter Element */
4714/* @{ */
4715#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU)
4716#define CAN_ERFFEL_FEL_SHIFT (0U)
4717#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
4718/* @} */
4719
4720/* The count of CAN_ERFFEL */
4721#define CAN_ERFFEL_COUNT (128U)
4722
4723
4724/*
4725 * @}
4726 */ /* end of group CAN_Register_Masks */
4727
4728
4729/* CAN - Peripheral instance base addresses */
4730/* Peripheral CAN1 base address */
4731#define CAN1_BASE (0x401D0000u)
4732/* Peripheral CAN1 base pointer */
4733#define CAN1 ((CAN_Type *)CAN1_BASE)
4734/* Peripheral CAN2 base address */
4735#define CAN2_BASE (0x401D4000u)
4736/* Peripheral CAN2 base pointer */
4737#define CAN2 ((CAN_Type *)CAN2_BASE)
4738/* Peripheral CAN3 base address */
4739#define CAN3_BASE (0x401D8000u)
4740/* Peripheral CAN3 base pointer */
4741#define CAN3 ((CAN_Type *)CAN3_BASE)
4742/* Array initializer of CAN peripheral base addresses */
4743#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
4744/* Array initializer of CAN peripheral base pointers */
4745#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
4746/* Interrupt vectors for the CAN peripheral type */
4747#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
4748#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
4749#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
4750#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
4751#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
4752#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
4753
4754/*
4755 * @}
4756 */ /* end of group CAN_Peripheral_Access_Layer */
4757
4758
4759/* ----------------------------------------------------------------------------
4760 -- CCM Peripheral Access Layer
4761 ---------------------------------------------------------------------------- */
4762
4763/*
4764 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
4765 * @{
4766 */
4767
4768/* CCM - Register Layout Typedef */
4769typedef struct {
4770 __IO uint32_t CCR;
4771 uint8_t RESERVED_0[4];
4772 __I uint32_t CSR;
4773 __IO uint32_t CCSR;
4774 __IO uint32_t CACRR;
4775 __IO uint32_t CBCDR;
4776 __IO uint32_t CBCMR;
4777 __IO uint32_t CSCMR1;
4778 __IO uint32_t CSCMR2;
4779 __IO uint32_t CSCDR1;
4780 __IO uint32_t CS1CDR;
4781 __IO uint32_t CS2CDR;
4782 __IO uint32_t CDCDR;
4783 uint8_t RESERVED_1[4];
4784 __IO uint32_t CSCDR2;
4785 __IO uint32_t CSCDR3;
4786 uint8_t RESERVED_2[8];
4787 __I uint32_t CDHIPR;
4788 uint8_t RESERVED_3[8];
4789 __IO uint32_t CLPCR;
4790 __IO uint32_t CISR;
4791 __IO uint32_t CIMR;
4792 __IO uint32_t CCOSR;
4793 __IO uint32_t CGPR;
4794 __IO uint32_t CCGR0;
4795 __IO uint32_t CCGR1;
4796 __IO uint32_t CCGR2;
4797 __IO uint32_t CCGR3;
4798 __IO uint32_t CCGR4;
4799 __IO uint32_t CCGR5;
4800 __IO uint32_t CCGR6;
4801 __IO uint32_t CCGR7;
4802 __IO uint32_t CMEOR;
4803} CCM_Type;
4804
4805/* ----------------------------------------------------------------------------
4806 -- CCM Register Masks
4807 ---------------------------------------------------------------------------- */
4808
4809/*
4810 * @addtogroup CCM_Register_Masks CCM Register Masks
4811 * @{
4812 */
4813
4814/* @name CCR - CCM Control Register */
4815/* @{ */
4816#define CCM_CCR_OSCNT_MASK (0xFFU)
4817#define CCM_CCR_OSCNT_SHIFT (0U)
4818#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
4819#define CCM_CCR_COSC_EN_MASK (0x1000U)
4820#define CCM_CCR_COSC_EN_SHIFT (12U)
4821/* COSC_EN
4822 * 0b0..disable on chip oscillator
4823 * 0b1..enable on chip oscillator
4824 */
4825#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
4826#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
4827#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
4828/* REG_BYPASS_COUNT
4829 * 0b000000..no delay
4830 * 0b000001..1 CKIL clock period delay
4831 * 0b111111..63 CKIL clock periods delay
4832 */
4833#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
4834#define CCM_CCR_RBC_EN_MASK (0x8000000U)
4835#define CCM_CCR_RBC_EN_SHIFT (27U)
4836/* RBC_EN
4837 * 0b1..REG_BYPASS_COUNTER enabled.
4838 * 0b0..REG_BYPASS_COUNTER disabled
4839 */
4840#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
4841/* @} */
4842
4843/* @name CSR - CCM Status Register */
4844/* @{ */
4845#define CCM_CSR_REF_EN_B_MASK (0x1U)
4846#define CCM_CSR_REF_EN_B_SHIFT (0U)
4847/* REF_EN_B
4848 * 0b0..value of CCM_REF_EN_B is '0'
4849 * 0b1..value of CCM_REF_EN_B is '1'
4850 */
4851#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
4852#define CCM_CSR_CAMP2_READY_MASK (0x8U)
4853#define CCM_CSR_CAMP2_READY_SHIFT (3U)
4854/* CAMP2_READY
4855 * 0b0..CAMP2 is not ready.
4856 * 0b1..CAMP2 is ready.
4857 */
4858#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
4859#define CCM_CSR_COSC_READY_MASK (0x20U)
4860#define CCM_CSR_COSC_READY_SHIFT (5U)
4861/* COSC_READY
4862 * 0b0..on board oscillator is not ready.
4863 * 0b1..on board oscillator is ready.
4864 */
4865#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
4866/* @} */
4867
4868/* @name CCSR - CCM Clock Switcher Register */
4869/* @{ */
4870#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
4871#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
4872/* PLL3_SW_CLK_SEL
4873 * 0b0..pll3_main_clk
4874 * 0b1..pll3 bypass clock
4875 */
4876#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
4877/* @} */
4878
4879/* @name CACRR - CCM Arm Clock Root Register */
4880/* @{ */
4881#define CCM_CACRR_ARM_PODF_MASK (0x7U)
4882#define CCM_CACRR_ARM_PODF_SHIFT (0U)
4883/* ARM_PODF
4884 * 0b000..divide by 1
4885 * 0b001..divide by 2
4886 * 0b010..divide by 3
4887 * 0b011..divide by 4
4888 * 0b100..divide by 5
4889 * 0b101..divide by 6
4890 * 0b110..divide by 7
4891 * 0b111..divide by 8
4892 */
4893#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
4894/* @} */
4895
4896/* @name CBCDR - CCM Bus Clock Divider Register */
4897/* @{ */
4898#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
4899#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
4900/* SEMC_CLK_SEL
4901 * 0b0..Periph_clk output will be used as SEMC clock root
4902 * 0b1..SEMC alternative clock will be used as SEMC clock root
4903 */
4904#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
4905#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
4906#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
4907/* SEMC_ALT_CLK_SEL
4908 * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock
4909 * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock
4910 */
4911#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
4912#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
4913#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
4914/* IPG_PODF
4915 * 0b00..divide by 1
4916 * 0b01..divide by 2
4917 * 0b10..divide by 3
4918 * 0b11..divide by 4
4919 */
4920#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
4921#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
4922#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
4923/* AHB_PODF
4924 * 0b000..divide by 1
4925 * 0b001..divide by 2
4926 * 0b010..divide by 3
4927 * 0b011..divide by 4
4928 * 0b100..divide by 5
4929 * 0b101..divide by 6
4930 * 0b110..divide by 7
4931 * 0b111..divide by 8
4932 */
4933#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
4934#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
4935#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
4936/* SEMC_PODF
4937 * 0b000..divide by 1
4938 * 0b001..divide by 2
4939 * 0b010..divide by 3
4940 * 0b011..divide by 4
4941 * 0b100..divide by 5
4942 * 0b101..divide by 6
4943 * 0b110..divide by 7
4944 * 0b111..divide by 8
4945 */
4946#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
4947#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
4948#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
4949/* PERIPH_CLK_SEL
4950 * 0b0..derive clock from pre_periph_clk_sel
4951 * 0b1..derive clock from periph_clk2_clk_divided
4952 */
4953#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
4954#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
4955#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
4956/* PERIPH_CLK2_PODF
4957 * 0b000..divide by 1
4958 * 0b001..divide by 2
4959 * 0b010..divide by 3
4960 * 0b011..divide by 4
4961 * 0b100..divide by 5
4962 * 0b101..divide by 6
4963 * 0b110..divide by 7
4964 * 0b111..divide by 8
4965 */
4966#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
4967/* @} */
4968
4969/* @name CBCMR - CCM Bus Clock Multiplexer Register */
4970/* @{ */
4971#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
4972#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
4973/* LPSPI_CLK_SEL
4974 * 0b00..derive clock from PLL3 PFD1 clk
4975 * 0b01..derive clock from PLL3 PFD0
4976 * 0b10..derive clock from PLL2
4977 * 0b11..derive clock from PLL2 PFD2
4978 */
4979#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
4980#define CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK (0x300U)
4981#define CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT (8U)
4982/* FLEXSPI2_CLK_SEL
4983 * 0b00..derive clock from PLL2 PFD2
4984 * 0b01..derive clock from PLL3 PFD0
4985 * 0b10..derive clock from PLL3 PFD1
4986 * 0b11..derive clock from PLL2 (pll2_main_clk)
4987 */
4988#define CCM_CBCMR_FLEXSPI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT)) & CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK)
4989#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
4990#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
4991/* PERIPH_CLK2_SEL
4992 * 0b00..derive clock from pll3_sw_clk
4993 * 0b01..derive clock from osc_clk (pll1_ref_clk)
4994 * 0b10..derive clock from pll2_bypass_clk
4995 * 0b11..reserved
4996 */
4997#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
4998#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
4999#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
5000/* TRACE_CLK_SEL
5001 * 0b00..derive clock from PLL2
5002 * 0b01..derive clock from PLL2 PFD2
5003 * 0b10..derive clock from PLL2 PFD0
5004 * 0b11..derive clock from PLL2 PFD1
5005 */
5006#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
5007#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
5008#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
5009/* PRE_PERIPH_CLK_SEL
5010 * 0b00..derive clock from PLL2
5011 * 0b01..derive clock from PLL2 PFD2
5012 * 0b10..derive clock from PLL2 PFD0
5013 * 0b11..derive clock from divided PLL1
5014 */
5015#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
5016#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
5017#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
5018/* LCDIF_PODF
5019 * 0b000..divide by 1
5020 * 0b001..divide by 2
5021 * 0b010..divide by 3
5022 * 0b011..divide by 4
5023 * 0b100..divide by 5
5024 * 0b101..divide by 6
5025 * 0b110..divide by 7
5026 * 0b111..divide by 8
5027 */
5028#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
5029#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
5030#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
5031/* LPSPI_PODF
5032 * 0b000..divide by 1
5033 * 0b001..divide by 2
5034 * 0b010..divide by 3
5035 * 0b011..divide by 4
5036 * 0b100..divide by 5
5037 * 0b101..divide by 6
5038 * 0b110..divide by 7
5039 * 0b111..divide by 8
5040 */
5041#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
5042#define CCM_CBCMR_FLEXSPI2_PODF_MASK (0xE0000000U)
5043#define CCM_CBCMR_FLEXSPI2_PODF_SHIFT (29U)
5044/* FLEXSPI2_PODF
5045 * 0b000..divide by 1
5046 * 0b001..divide by 2
5047 * 0b010..divide by 3
5048 * 0b011..divide by 4
5049 * 0b100..divide by 5
5050 * 0b101..divide by 6
5051 * 0b110..divide by 7
5052 * 0b111..divide by 8
5053 */
5054#define CCM_CBCMR_FLEXSPI2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_PODF_SHIFT)) & CCM_CBCMR_FLEXSPI2_PODF_MASK)
5055/* @} */
5056
5057/* @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
5058/* @{ */
5059#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
5060#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
5061/* PERCLK_PODF - Divider for perclk podf.
5062 * 0b000000..Divide by 1
5063 * 0b000001..Divide by 2
5064 * 0b000010..Divide by 3
5065 * 0b000011..Divide by 4
5066 * 0b000100..Divide by 5
5067 * 0b000101..Divide by 6
5068 * 0b000110..Divide by 7
5069 * 0b000111..Divide by 8
5070 * 0b001000..Divide by 9
5071 * 0b001001..Divide by 10
5072 * 0b001010..Divide by 11
5073 * 0b001011..Divide by 12
5074 * 0b001100..Divide by 13
5075 * 0b001101..Divide by 14
5076 * 0b001110..Divide by 15
5077 * 0b001111..Divide by 16
5078 * 0b010000..Divide by 17
5079 * 0b010001..Divide by 18
5080 * 0b010010..Divide by 19
5081 * 0b010011..Divide by 20
5082 * 0b010100..Divide by 21
5083 * 0b010101..Divide by 22
5084 * 0b010110..Divide by 23
5085 * 0b010111..Divide by 24
5086 * 0b011000..Divide by 25
5087 * 0b011001..Divide by 26
5088 * 0b011010..Divide by 27
5089 * 0b011011..Divide by 28
5090 * 0b011100..Divide by 29
5091 * 0b011101..Divide by 30
5092 * 0b011110..Divide by 31
5093 * 0b011111..Divide by 32
5094 * 0b100000..Divide by 33
5095 * 0b100001..Divide by 34
5096 * 0b100010..Divide by 35
5097 * 0b100011..Divide by 36
5098 * 0b100100..Divide by 37
5099 * 0b100101..Divide by 38
5100 * 0b100110..Divide by 39
5101 * 0b100111..Divide by 40
5102 * 0b101000..Divide by 41
5103 * 0b101001..Divide by 42
5104 * 0b101010..Divide by 43
5105 * 0b101011..Divide by 44
5106 * 0b101100..Divide by 45
5107 * 0b101101..Divide by 46
5108 * 0b101110..Divide by 47
5109 * 0b101111..Divide by 48
5110 * 0b110000..Divide by 49
5111 * 0b110001..Divide by 50
5112 * 0b110010..Divide by 51
5113 * 0b110011..Divide by 52
5114 * 0b110100..Divide by 53
5115 * 0b110101..Divide by 54
5116 * 0b110110..Divide by 55
5117 * 0b110111..Divide by 56
5118 * 0b111000..Divide by 57
5119 * 0b111001..Divide by 58
5120 * 0b111010..Divide by 59
5121 * 0b111011..Divide by 60
5122 * 0b111100..Divide by 61
5123 * 0b111101..Divide by 62
5124 * 0b111110..Divide by 63
5125 * 0b111111..Divide by 64
5126 */
5127#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
5128#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
5129#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
5130/* PERCLK_CLK_SEL
5131 * 0b0..derive clock from ipg clk root
5132 * 0b1..derive clock from osc_clk
5133 */
5134#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
5135#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
5136#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
5137/* SAI1_CLK_SEL
5138 * 0b00..derive clock from PLL3 PFD2
5139 * 0b01..derive clock from PLL5
5140 * 0b10..derive clock from PLL4
5141 * 0b11..Reserved
5142 */
5143#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
5144#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
5145#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
5146/* SAI2_CLK_SEL
5147 * 0b00..derive clock from PLL3 PFD2
5148 * 0b01..derive clock from PLL5
5149 * 0b10..derive clock from PLL4
5150 * 0b11..Reserved
5151 */
5152#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
5153#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
5154#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
5155/* SAI3_CLK_SEL
5156 * 0b00..derive clock from PLL3 PFD2
5157 * 0b01..derive clock from PLL5
5158 * 0b10..derive clock from PLL4
5159 * 0b11..Reserved
5160 */
5161#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
5162#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
5163#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
5164/* USDHC1_CLK_SEL
5165 * 0b0..derive clock from PLL2 PFD2
5166 * 0b1..derive clock from PLL2 PFD0
5167 */
5168#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
5169#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
5170#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
5171/* USDHC2_CLK_SEL
5172 * 0b0..derive clock from PLL2 PFD2
5173 * 0b1..derive clock from PLL2 PFD0
5174 */
5175#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
5176#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
5177#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
5178/* FLEXSPI_PODF
5179 * 0b000..divide by 1
5180 * 0b001..divide by 2
5181 * 0b010..divide by 3
5182 * 0b011..divide by 4
5183 * 0b100..divide by 5
5184 * 0b101..divide by 6
5185 * 0b110..divide by 7
5186 * 0b111..divide by 8
5187 */
5188#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
5189#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
5190#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
5191/* FLEXSPI_CLK_SEL
5192 * 0b00..derive clock from semc_clk_root_pre
5193 * 0b01..derive clock from pll3_sw_clk
5194 * 0b10..derive clock from PLL2 PFD2
5195 * 0b11..derive clock from PLL3 PFD0
5196 */
5197#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
5198/* @} */
5199
5200/* @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
5201/* @{ */
5202#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
5203#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
5204/* CAN_CLK_PODF - Divider for CAN/CANFD clock podf.
5205 * 0b000000..Divide by 1
5206 * 0b000001..Divide by 2
5207 * 0b000010..Divide by 3
5208 * 0b000011..Divide by 4
5209 * 0b000100..Divide by 5
5210 * 0b000101..Divide by 6
5211 * 0b000110..Divide by 7
5212 * 0b000111..Divide by 8
5213 * 0b001000..Divide by 9
5214 * 0b001001..Divide by 10
5215 * 0b001010..Divide by 11
5216 * 0b001011..Divide by 12
5217 * 0b001100..Divide by 13
5218 * 0b001101..Divide by 14
5219 * 0b001110..Divide by 15
5220 * 0b001111..Divide by 16
5221 * 0b010000..Divide by 17
5222 * 0b010001..Divide by 18
5223 * 0b010010..Divide by 19
5224 * 0b010011..Divide by 20
5225 * 0b010100..Divide by 21
5226 * 0b010101..Divide by 22
5227 * 0b010110..Divide by 23
5228 * 0b010111..Divide by 24
5229 * 0b011000..Divide by 25
5230 * 0b011001..Divide by 26
5231 * 0b011010..Divide by 27
5232 * 0b011011..Divide by 28
5233 * 0b011100..Divide by 29
5234 * 0b011101..Divide by 30
5235 * 0b011110..Divide by 31
5236 * 0b011111..Divide by 32
5237 * 0b100000..Divide by 33
5238 * 0b100001..Divide by 34
5239 * 0b100010..Divide by 35
5240 * 0b100011..Divide by 36
5241 * 0b100100..Divide by 37
5242 * 0b100101..Divide by 38
5243 * 0b100110..Divide by 39
5244 * 0b100111..Divide by 40
5245 * 0b101000..Divide by 41
5246 * 0b101001..Divide by 42
5247 * 0b101010..Divide by 43
5248 * 0b101011..Divide by 44
5249 * 0b101100..Divide by 45
5250 * 0b101101..Divide by 46
5251 * 0b101110..Divide by 47
5252 * 0b101111..Divide by 48
5253 * 0b110000..Divide by 49
5254 * 0b110001..Divide by 50
5255 * 0b110010..Divide by 51
5256 * 0b110011..Divide by 52
5257 * 0b110100..Divide by 53
5258 * 0b110101..Divide by 54
5259 * 0b110110..Divide by 55
5260 * 0b110111..Divide by 56
5261 * 0b111000..Divide by 57
5262 * 0b111001..Divide by 58
5263 * 0b111010..Divide by 59
5264 * 0b111011..Divide by 60
5265 * 0b111100..Divide by 61
5266 * 0b111101..Divide by 62
5267 * 0b111110..Divide by 63
5268 * 0b111111..Divide by 64
5269 */
5270#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
5271#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
5272#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
5273/* CAN_CLK_SEL
5274 * 0b00..derive clock from pll3_sw_clk divided clock (60M)
5275 * 0b01..derive clock from osc_clk (24M)
5276 * 0b10..derive clock from pll3_sw_clk divided clock (80M)
5277 * 0b11..Disable FlexCAN clock
5278 */
5279#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
5280#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
5281#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
5282/* FLEXIO2_CLK_SEL
5283 * 0b00..derive clock from PLL4 divided clock
5284 * 0b01..derive clock from PLL3 PFD2 clock
5285 * 0b10..derive clock from PLL5 clock
5286 * 0b11..derive clock from pll3_sw_clk
5287 */
5288#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
5289/* @} */
5290
5291/* @name CSCDR1 - CCM Serial Clock Divider Register 1 */
5292/* @{ */
5293#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
5294#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
5295/* UART_CLK_PODF - Divider for uart clock podf.
5296 * 0b000000..Divide by 1
5297 * 0b000001..Divide by 2
5298 * 0b000010..Divide by 3
5299 * 0b000011..Divide by 4
5300 * 0b000100..Divide by 5
5301 * 0b000101..Divide by 6
5302 * 0b000110..Divide by 7
5303 * 0b000111..Divide by 8
5304 * 0b001000..Divide by 9
5305 * 0b001001..Divide by 10
5306 * 0b001010..Divide by 11
5307 * 0b001011..Divide by 12
5308 * 0b001100..Divide by 13
5309 * 0b001101..Divide by 14
5310 * 0b001110..Divide by 15
5311 * 0b001111..Divide by 16
5312 * 0b010000..Divide by 17
5313 * 0b010001..Divide by 18
5314 * 0b010010..Divide by 19
5315 * 0b010011..Divide by 20
5316 * 0b010100..Divide by 21
5317 * 0b010101..Divide by 22
5318 * 0b010110..Divide by 23
5319 * 0b010111..Divide by 24
5320 * 0b011000..Divide by 25
5321 * 0b011001..Divide by 26
5322 * 0b011010..Divide by 27
5323 * 0b011011..Divide by 28
5324 * 0b011100..Divide by 29
5325 * 0b011101..Divide by 30
5326 * 0b011110..Divide by 31
5327 * 0b011111..Divide by 32
5328 * 0b100000..Divide by 33
5329 * 0b100001..Divide by 34
5330 * 0b100010..Divide by 35
5331 * 0b100011..Divide by 36
5332 * 0b100100..Divide by 37
5333 * 0b100101..Divide by 38
5334 * 0b100110..Divide by 39
5335 * 0b100111..Divide by 40
5336 * 0b101000..Divide by 41
5337 * 0b101001..Divide by 42
5338 * 0b101010..Divide by 43
5339 * 0b101011..Divide by 44
5340 * 0b101100..Divide by 45
5341 * 0b101101..Divide by 46
5342 * 0b101110..Divide by 47
5343 * 0b101111..Divide by 48
5344 * 0b110000..Divide by 49
5345 * 0b110001..Divide by 50
5346 * 0b110010..Divide by 51
5347 * 0b110011..Divide by 52
5348 * 0b110100..Divide by 53
5349 * 0b110101..Divide by 54
5350 * 0b110110..Divide by 55
5351 * 0b110111..Divide by 56
5352 * 0b111000..Divide by 57
5353 * 0b111001..Divide by 58
5354 * 0b111010..Divide by 59
5355 * 0b111011..Divide by 60
5356 * 0b111100..Divide by 61
5357 * 0b111101..Divide by 62
5358 * 0b111110..Divide by 63
5359 * 0b111111..Divide by 64
5360 */
5361#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
5362#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
5363#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
5364/* UART_CLK_SEL
5365 * 0b0..derive clock from pll3_80m
5366 * 0b1..derive clock from osc_clk
5367 */
5368#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
5369#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
5370#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
5371/* USDHC1_PODF
5372 * 0b000..divide by 1
5373 * 0b001..divide by 2
5374 * 0b010..divide by 3
5375 * 0b011..divide by 4
5376 * 0b100..divide by 5
5377 * 0b101..divide by 6
5378 * 0b110..divide by 7
5379 * 0b111..divide by 8
5380 */
5381#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
5382#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
5383#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
5384/* USDHC2_PODF
5385 * 0b000..divide by 1
5386 * 0b001..divide by 2
5387 * 0b010..divide by 3
5388 * 0b011..divide by 4
5389 * 0b100..divide by 5
5390 * 0b101..divide by 6
5391 * 0b110..divide by 7
5392 * 0b111..divide by 8
5393 */
5394#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
5395#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
5396#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
5397/* TRACE_PODF
5398 * 0b00..divide by 1
5399 * 0b01..divide by 2
5400 * 0b10..divide by 3
5401 * 0b11..divide by 4
5402 */
5403#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
5404/* @} */
5405
5406/* @name CS1CDR - CCM Clock Divider Register */
5407/* @{ */
5408#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
5409#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
5410/* SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower
5411 * than 300Mhz, the predivider can be used to achieve this.
5412 * 0b000000..Divide by 1
5413 * 0b000001..Divide by 2
5414 * 0b000010..Divide by 3
5415 * 0b000011..Divide by 4
5416 * 0b000100..Divide by 5
5417 * 0b000101..Divide by 6
5418 * 0b000110..Divide by 7
5419 * 0b000111..Divide by 8
5420 * 0b001000..Divide by 9
5421 * 0b001001..Divide by 10
5422 * 0b001010..Divide by 11
5423 * 0b001011..Divide by 12
5424 * 0b001100..Divide by 13
5425 * 0b001101..Divide by 14
5426 * 0b001110..Divide by 15
5427 * 0b001111..Divide by 16
5428 * 0b010000..Divide by 17
5429 * 0b010001..Divide by 18
5430 * 0b010010..Divide by 19
5431 * 0b010011..Divide by 20
5432 * 0b010100..Divide by 21
5433 * 0b010101..Divide by 22
5434 * 0b010110..Divide by 23
5435 * 0b010111..Divide by 24
5436 * 0b011000..Divide by 25
5437 * 0b011001..Divide by 26
5438 * 0b011010..Divide by 27
5439 * 0b011011..Divide by 28
5440 * 0b011100..Divide by 29
5441 * 0b011101..Divide by 30
5442 * 0b011110..Divide by 31
5443 * 0b011111..Divide by 32
5444 * 0b100000..Divide by 33
5445 * 0b100001..Divide by 34
5446 * 0b100010..Divide by 35
5447 * 0b100011..Divide by 36
5448 * 0b100100..Divide by 37
5449 * 0b100101..Divide by 38
5450 * 0b100110..Divide by 39
5451 * 0b100111..Divide by 40
5452 * 0b101000..Divide by 41
5453 * 0b101001..Divide by 42
5454 * 0b101010..Divide by 43
5455 * 0b101011..Divide by 44
5456 * 0b101100..Divide by 45
5457 * 0b101101..Divide by 46
5458 * 0b101110..Divide by 47
5459 * 0b101111..Divide by 48
5460 * 0b110000..Divide by 49
5461 * 0b110001..Divide by 50
5462 * 0b110010..Divide by 51
5463 * 0b110011..Divide by 52
5464 * 0b110100..Divide by 53
5465 * 0b110101..Divide by 54
5466 * 0b110110..Divide by 55
5467 * 0b110111..Divide by 56
5468 * 0b111000..Divide by 57
5469 * 0b111001..Divide by 58
5470 * 0b111010..Divide by 59
5471 * 0b111011..Divide by 60
5472 * 0b111100..Divide by 61
5473 * 0b111101..Divide by 62
5474 * 0b111110..Divide by 63
5475 * 0b111111..Divide by 64
5476 */
5477#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
5478#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
5479#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
5480/* SAI1_CLK_PRED
5481 * 0b000..divide by 1
5482 * 0b001..divide by 2
5483 * 0b010..divide by 3
5484 * 0b011..divide by 4
5485 * 0b100..divide by 5
5486 * 0b101..divide by 6
5487 * 0b110..divide by 7
5488 * 0b111..divide by 8
5489 */
5490#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
5491#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
5492#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
5493/* FLEXIO2_CLK_PRED
5494 * 0b000..divide by 1
5495 * 0b001..divide by 2
5496 * 0b010..divide by 3
5497 * 0b011..divide by 4
5498 * 0b100..divide by 5
5499 * 0b101..divide by 6
5500 * 0b110..divide by 7
5501 * 0b111..divide by 8
5502 */
5503#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
5504#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
5505#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
5506/* SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower
5507 * than 300Mhz, the predivider can be used to achieve this.
5508 * 0b000000..Divide by 1
5509 * 0b000001..Divide by 2
5510 * 0b000010..Divide by 3
5511 * 0b000011..Divide by 4
5512 * 0b000100..Divide by 5
5513 * 0b000101..Divide by 6
5514 * 0b000110..Divide by 7
5515 * 0b000111..Divide by 8
5516 * 0b001000..Divide by 9
5517 * 0b001001..Divide by 10
5518 * 0b001010..Divide by 11
5519 * 0b001011..Divide by 12
5520 * 0b001100..Divide by 13
5521 * 0b001101..Divide by 14
5522 * 0b001110..Divide by 15
5523 * 0b001111..Divide by 16
5524 * 0b010000..Divide by 17
5525 * 0b010001..Divide by 18
5526 * 0b010010..Divide by 19
5527 * 0b010011..Divide by 20
5528 * 0b010100..Divide by 21
5529 * 0b010101..Divide by 22
5530 * 0b010110..Divide by 23
5531 * 0b010111..Divide by 24
5532 * 0b011000..Divide by 25
5533 * 0b011001..Divide by 26
5534 * 0b011010..Divide by 27
5535 * 0b011011..Divide by 28
5536 * 0b011100..Divide by 29
5537 * 0b011101..Divide by 30
5538 * 0b011110..Divide by 31
5539 * 0b011111..Divide by 32
5540 * 0b100000..Divide by 33
5541 * 0b100001..Divide by 34
5542 * 0b100010..Divide by 35
5543 * 0b100011..Divide by 36
5544 * 0b100100..Divide by 37
5545 * 0b100101..Divide by 38
5546 * 0b100110..Divide by 39
5547 * 0b100111..Divide by 40
5548 * 0b101000..Divide by 41
5549 * 0b101001..Divide by 42
5550 * 0b101010..Divide by 43
5551 * 0b101011..Divide by 44
5552 * 0b101100..Divide by 45
5553 * 0b101101..Divide by 46
5554 * 0b101110..Divide by 47
5555 * 0b101111..Divide by 48
5556 * 0b110000..Divide by 49
5557 * 0b110001..Divide by 50
5558 * 0b110010..Divide by 51
5559 * 0b110011..Divide by 52
5560 * 0b110100..Divide by 53
5561 * 0b110101..Divide by 54
5562 * 0b110110..Divide by 55
5563 * 0b110111..Divide by 56
5564 * 0b111000..Divide by 57
5565 * 0b111001..Divide by 58
5566 * 0b111010..Divide by 59
5567 * 0b111011..Divide by 60
5568 * 0b111100..Divide by 61
5569 * 0b111101..Divide by 62
5570 * 0b111110..Divide by 63
5571 * 0b111111..Divide by 64
5572 */
5573#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
5574#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
5575#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
5576/* SAI3_CLK_PRED
5577 * 0b000..divide by 1
5578 * 0b001..divide by 2
5579 * 0b010..divide by 3
5580 * 0b011..divide by 4
5581 * 0b100..divide by 5
5582 * 0b101..divide by 6
5583 * 0b110..divide by 7
5584 * 0b111..divide by 8
5585 */
5586#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
5587#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
5588#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
5589/* FLEXIO2_CLK_PODF - Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated.
5590 * 0b000..Divide by 1
5591 * 0b001..Divide by 2
5592 * 0b010..Divide by 3
5593 * 0b011..Divide by 4
5594 * 0b100..Divide by 5
5595 * 0b101..Divide by 6
5596 * 0b110..Divide by 7
5597 * 0b111..Divide by 8
5598 */
5599#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
5600/* @} */
5601
5602/* @name CS2CDR - CCM Clock Divider Register */
5603/* @{ */
5604#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
5605#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
5606/* SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower
5607 * than 300Mhz, the predivider can be used to achieve this.
5608 * 0b000000..Divide by 1
5609 * 0b000001..Divide by 2
5610 * 0b000010..Divide by 3
5611 * 0b000011..Divide by 4
5612 * 0b000100..Divide by 5
5613 * 0b000101..Divide by 6
5614 * 0b000110..Divide by 7
5615 * 0b000111..Divide by 8
5616 * 0b001000..Divide by 9
5617 * 0b001001..Divide by 10
5618 * 0b001010..Divide by 11
5619 * 0b001011..Divide by 12
5620 * 0b001100..Divide by 13
5621 * 0b001101..Divide by 14
5622 * 0b001110..Divide by 15
5623 * 0b001111..Divide by 16
5624 * 0b010000..Divide by 17
5625 * 0b010001..Divide by 18
5626 * 0b010010..Divide by 19
5627 * 0b010011..Divide by 20
5628 * 0b010100..Divide by 21
5629 * 0b010101..Divide by 22
5630 * 0b010110..Divide by 23
5631 * 0b010111..Divide by 24
5632 * 0b011000..Divide by 25
5633 * 0b011001..Divide by 26
5634 * 0b011010..Divide by 27
5635 * 0b011011..Divide by 28
5636 * 0b011100..Divide by 29
5637 * 0b011101..Divide by 30
5638 * 0b011110..Divide by 31
5639 * 0b011111..Divide by 32
5640 * 0b100000..Divide by 33
5641 * 0b100001..Divide by 34
5642 * 0b100010..Divide by 35
5643 * 0b100011..Divide by 36
5644 * 0b100100..Divide by 37
5645 * 0b100101..Divide by 38
5646 * 0b100110..Divide by 39
5647 * 0b100111..Divide by 40
5648 * 0b101000..Divide by 41
5649 * 0b101001..Divide by 42
5650 * 0b101010..Divide by 43
5651 * 0b101011..Divide by 44
5652 * 0b101100..Divide by 45
5653 * 0b101101..Divide by 46
5654 * 0b101110..Divide by 47
5655 * 0b101111..Divide by 48
5656 * 0b110000..Divide by 49
5657 * 0b110001..Divide by 50
5658 * 0b110010..Divide by 51
5659 * 0b110011..Divide by 52
5660 * 0b110100..Divide by 53
5661 * 0b110101..Divide by 54
5662 * 0b110110..Divide by 55
5663 * 0b110111..Divide by 56
5664 * 0b111000..Divide by 57
5665 * 0b111001..Divide by 58
5666 * 0b111010..Divide by 59
5667 * 0b111011..Divide by 60
5668 * 0b111100..Divide by 61
5669 * 0b111101..Divide by 62
5670 * 0b111110..Divide by 63
5671 * 0b111111..Divide by 64
5672 */
5673#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
5674#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
5675#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
5676/* SAI2_CLK_PRED
5677 * 0b000..divide by 1
5678 * 0b001..divide by 2
5679 * 0b010..divide by 3
5680 * 0b011..divide by 4
5681 * 0b100..divide by 5
5682 * 0b101..divide by 6
5683 * 0b110..divide by 7
5684 * 0b111..divide by 8
5685 */
5686#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
5687/* @} */
5688
5689/* @name CDCDR - CCM D1 Clock Divider Register */
5690/* @{ */
5691#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
5692#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
5693/* FLEXIO1_CLK_SEL
5694 * 0b00..derive clock from PLL4
5695 * 0b01..derive clock from PLL3 PFD2
5696 * 0b10..derive clock from PLL5
5697 * 0b11..derive clock from pll3_sw_clk
5698 */
5699#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
5700#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
5701#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
5702/* FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
5703 * 0b000..Divide by 1
5704 * 0b001..Divide by 2
5705 * 0b010..Divide by 3
5706 * 0b011..Divide by 4
5707 * 0b100..Divide by 5
5708 * 0b101..Divide by 6
5709 * 0b110..Divide by 7
5710 * 0b111..Divide by 8
5711 */
5712#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
5713#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
5714#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
5715/* FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
5716 * 0b000..Divide by 1
5717 * 0b001..Divide by 2
5718 * 0b010..Divide by 3
5719 * 0b011..Divide by 4
5720 * 0b100..Divide by 5
5721 * 0b101..Divide by 6
5722 * 0b110..Divide by 7
5723 * 0b111..Divide by 8
5724 */
5725#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
5726#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
5727#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
5728/* SPDIF0_CLK_SEL
5729 * 0b00..derive clock from PLL4
5730 * 0b01..derive clock from PLL3 PFD2
5731 * 0b10..derive clock from PLL5
5732 * 0b11..derive clock from pll3_sw_clk
5733 */
5734#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
5735#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
5736#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
5737/* SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
5738 * 0b000..Divide by 1
5739 * 0b001..Divide by 2
5740 * 0b010..Divide by 3
5741 * 0b011..Divide by 4
5742 * 0b100..Divide by 5
5743 * 0b101..Divide by 6
5744 * 0b110..Divide by 7
5745 * 0b111..Divide by 8
5746 */
5747#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
5748#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
5749#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
5750/* SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
5751 * 0b000..Divide by 1
5752 * 0b001..Divide by 2
5753 * 0b010..Divide by 3
5754 * 0b011..Divide by 4
5755 * 0b100..Divide by 5
5756 * 0b101..Divide by 6
5757 * 0b110..Divide by 7
5758 * 0b111..Divide by 8
5759 */
5760#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
5761/* @} */
5762
5763/* @name CSCDR2 - CCM Serial Clock Divider Register 2 */
5764/* @{ */
5765#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
5766#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
5767/* LCDIF_PRED
5768 * 0b000..divide by 1
5769 * 0b001..divide by 2
5770 * 0b010..divide by 3
5771 * 0b011..divide by 4
5772 * 0b100..divide by 5
5773 * 0b101..divide by 6
5774 * 0b110..divide by 7
5775 * 0b111..divide by 8
5776 */
5777#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
5778#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
5779#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
5780/* LCDIF_PRE_CLK_SEL
5781 * 0b000..derive clock from PLL2
5782 * 0b001..derive clock from PLL3 PFD3
5783 * 0b010..derive clock from PLL5
5784 * 0b011..derive clock from PLL2 PFD0
5785 * 0b100..derive clock from PLL2 PFD1
5786 * 0b101..derive clock from PLL3 PFD1
5787 */
5788#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
5789#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
5790#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
5791/* LPI2C_CLK_SEL
5792 * 0b0..derive clock from pll3_60m
5793 * 0b1..derive clock from osc_clk
5794 */
5795#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
5796#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
5797#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
5798/* LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is
5799 * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used
5800 * to achieve this.
5801 * 0b000000..Divide by 1
5802 * 0b000001..Divide by 2
5803 * 0b000010..Divide by 3
5804 * 0b000011..Divide by 4
5805 * 0b000100..Divide by 5
5806 * 0b000101..Divide by 6
5807 * 0b000110..Divide by 7
5808 * 0b000111..Divide by 8
5809 * 0b001000..Divide by 9
5810 * 0b001001..Divide by 10
5811 * 0b001010..Divide by 11
5812 * 0b001011..Divide by 12
5813 * 0b001100..Divide by 13
5814 * 0b001101..Divide by 14
5815 * 0b001110..Divide by 15
5816 * 0b001111..Divide by 16
5817 * 0b010000..Divide by 17
5818 * 0b010001..Divide by 18
5819 * 0b010010..Divide by 19
5820 * 0b010011..Divide by 20
5821 * 0b010100..Divide by 21
5822 * 0b010101..Divide by 22
5823 * 0b010110..Divide by 23
5824 * 0b010111..Divide by 24
5825 * 0b011000..Divide by 25
5826 * 0b011001..Divide by 26
5827 * 0b011010..Divide by 27
5828 * 0b011011..Divide by 28
5829 * 0b011100..Divide by 29
5830 * 0b011101..Divide by 30
5831 * 0b011110..Divide by 31
5832 * 0b011111..Divide by 32
5833 * 0b100000..Divide by 33
5834 * 0b100001..Divide by 34
5835 * 0b100010..Divide by 35
5836 * 0b100011..Divide by 36
5837 * 0b100100..Divide by 37
5838 * 0b100101..Divide by 38
5839 * 0b100110..Divide by 39
5840 * 0b100111..Divide by 40
5841 * 0b101000..Divide by 41
5842 * 0b101001..Divide by 42
5843 * 0b101010..Divide by 43
5844 * 0b101011..Divide by 44
5845 * 0b101100..Divide by 45
5846 * 0b101101..Divide by 46
5847 * 0b101110..Divide by 47
5848 * 0b101111..Divide by 48
5849 * 0b110000..Divide by 49
5850 * 0b110001..Divide by 50
5851 * 0b110010..Divide by 51
5852 * 0b110011..Divide by 52
5853 * 0b110100..Divide by 53
5854 * 0b110101..Divide by 54
5855 * 0b110110..Divide by 55
5856 * 0b110111..Divide by 56
5857 * 0b111000..Divide by 57
5858 * 0b111001..Divide by 58
5859 * 0b111010..Divide by 59
5860 * 0b111011..Divide by 60
5861 * 0b111100..Divide by 61
5862 * 0b111101..Divide by 62
5863 * 0b111110..Divide by 63
5864 * 0b111111..Divide by 64
5865 */
5866#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
5867/* @} */
5868
5869/* @name CSCDR3 - CCM Serial Clock Divider Register 3 */
5870/* @{ */
5871#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
5872#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
5873/* CSI_CLK_SEL
5874 * 0b00..derive clock from osc_clk (24M)
5875 * 0b01..derive clock from PLL2 PFD2
5876 * 0b10..derive clock from pll3_120M
5877 * 0b11..derive clock from PLL3 PFD1
5878 */
5879#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
5880#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
5881#define CCM_CSCDR3_CSI_PODF_SHIFT (11U)
5882/* CSI_PODF
5883 * 0b000..divide by 1
5884 * 0b001..divide by 2
5885 * 0b010..divide by 3
5886 * 0b011..divide by 4
5887 * 0b100..divide by 5
5888 * 0b101..divide by 6
5889 * 0b110..divide by 7
5890 * 0b111..divide by 8
5891 */
5892#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
5893/* @} */
5894
5895/* @name CDHIPR - CCM Divider Handshake In-Process Register */
5896/* @{ */
5897#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
5898#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
5899/* SEMC_PODF_BUSY
5900 * 0b0..divider is not busy and its value represents the actual division.
5901 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
5902 * value of the division factor, and after the handshake the written value of the semc_podf will be applied.
5903 */
5904#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
5905#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
5906#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
5907/* AHB_PODF_BUSY
5908 * 0b0..divider is not busy and its value represents the actual division.
5909 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
5910 * value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
5911 */
5912#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
5913#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
5914#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
5915/* PERIPH2_CLK_SEL_BUSY
5916 * 0b0..mux is not busy and its value represents the actual division.
5917 * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the
5918 * previous value of select, and after the handshake periph2_clk_sel value will be applied.
5919 */
5920#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
5921#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
5922#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
5923/* PERIPH_CLK_SEL_BUSY
5924 * 0b0..mux is not busy and its value represents the actual division.
5925 * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
5926 * previous value of select, and after the handshake periph_clk_sel value will be applied.
5927 */
5928#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
5929#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
5930#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
5931/* ARM_PODF_BUSY
5932 * 0b0..divider is not busy and its value represents the actual division.
5933 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
5934 * value of the division factor, and after the handshake the written value of the arm_podf will be applied.
5935 */
5936#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
5937/* @} */
5938
5939/* @name CLPCR - CCM Low Power Control Register */
5940/* @{ */
5941#define CCM_CLPCR_LPM_MASK (0x3U)
5942#define CCM_CLPCR_LPM_SHIFT (0U)
5943/* LPM
5944 * 0b00..Remain in run mode
5945 * 0b01..Transfer to wait mode
5946 * 0b10..Transfer to stop mode
5947 * 0b11..Reserved
5948 */
5949#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
5950#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
5951#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
5952/* ARM_CLK_DIS_ON_LPM
5953 * 0b0..ARM clock enabled on wait mode.
5954 * 0b1..ARM clock disabled on wait mode. .
5955 */
5956#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
5957#define CCM_CLPCR_SBYOS_MASK (0x40U)
5958#define CCM_CLPCR_SBYOS_SHIFT (6U)
5959/* SBYOS
5960 * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain
5961 * asserted - '0' and cosc_pwrdown will remain de asserted - '0')
5962 * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be
5963 * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will
5964 * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will
5965 * continue with the exit from the STOP mode process.
5966 */
5967#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
5968#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
5969#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
5970/* DIS_REF_OSC
5971 * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
5972 * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
5973 */
5974#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
5975#define CCM_CLPCR_VSTBY_MASK (0x100U)
5976#define CCM_CLPCR_VSTBY_SHIFT (8U)
5977/* VSTBY
5978 * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
5979 * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
5980 */
5981#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
5982#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
5983#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
5984/* STBY_COUNT
5985 * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
5986 * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
5987 * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
5988 * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
5989 */
5990#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
5991#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
5992#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
5993/* COSC_PWRDOWN
5994 * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
5995 * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
5996 */
5997#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
5998#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
5999#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
6000#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
6001#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
6002#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
6003#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
6004#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
6005#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
6006/* MASK_CORE0_WFI
6007 * 0b0..WFI of core0 is not masked
6008 * 0b1..WFI of core0 is masked
6009 */
6010#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
6011#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
6012#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
6013/* MASK_SCU_IDLE
6014 * 0b1..SCU IDLE is masked
6015 * 0b0..SCU IDLE is not masked
6016 */
6017#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
6018#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
6019#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
6020/* MASK_L2CC_IDLE
6021 * 0b1..L2CC IDLE is masked
6022 * 0b0..L2CC IDLE is not masked
6023 */
6024#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
6025/* @} */
6026
6027/* @name CISR - CCM Interrupt Status Register */
6028/* @{ */
6029#define CCM_CISR_LRF_PLL_MASK (0x1U)
6030#define CCM_CISR_LRF_PLL_SHIFT (0U)
6031/* LRF_PLL
6032 * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
6033 * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
6034 */
6035#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
6036#define CCM_CISR_COSC_READY_MASK (0x40U)
6037#define CCM_CISR_COSC_READY_SHIFT (6U)
6038/* COSC_READY
6039 * 0b0..interrupt is not generated due to on board oscillator ready
6040 * 0b1..interrupt generated due to on board oscillator ready
6041 */
6042#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
6043#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
6044#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
6045/* SEMC_PODF_LOADED
6046 * 0b0..interrupt is not generated due to frequency change of semc_podf
6047 * 0b1..interrupt generated due to frequency change of semc_podf
6048 */
6049#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
6050#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6051#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6052/* PERIPH2_CLK_SEL_LOADED
6053 * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel
6054 * 0b1..interrupt generated due to frequency change of periph2_clk_sel
6055 */
6056#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
6057#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
6058#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
6059/* AHB_PODF_LOADED
6060 * 0b0..interrupt is not generated due to frequency change of ahb_podf
6061 * 0b1..interrupt generated due to frequency change of ahb_podf
6062 */
6063#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
6064#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6065#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6066/* PERIPH_CLK_SEL_LOADED
6067 * 0b0..interrupt is not generated due to update of periph_clk_sel.
6068 * 0b1..interrupt generated due to update of periph_clk_sel.
6069 */
6070#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
6071#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
6072#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
6073/* ARM_PODF_LOADED
6074 * 0b0..interrupt is not generated due to frequency change of arm_podf
6075 * 0b1..interrupt generated due to frequency change of arm_podf
6076 */
6077#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
6078/* @} */
6079
6080/* @name CIMR - CCM Interrupt Mask Register */
6081/* @{ */
6082#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
6083#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
6084/* MASK_LRF_PLL
6085 * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
6086 * 0b1..mask interrupt due to lrf of PLLs
6087 */
6088#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
6089#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
6090#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
6091/* MASK_COSC_READY
6092 * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
6093 * 0b1..mask interrupt due to on board oscillator ready
6094 */
6095#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
6096#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
6097#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
6098/* MASK_SEMC_PODF_LOADED
6099 * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created
6100 * 0b1..mask interrupt due to frequency change of semc_podf
6101 */
6102#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
6103#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6104#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6105/* MASK_PERIPH2_CLK_SEL_LOADED
6106 * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
6107 * 0b1..mask interrupt due to update of periph2_clk_sel
6108 */
6109#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
6110#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
6111#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
6112/* MASK_AHB_PODF_LOADED
6113 * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
6114 * 0b1..mask interrupt due to frequency change of ahb_podf
6115 */
6116#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
6117#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6118#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6119/* MASK_PERIPH_CLK_SEL_LOADED
6120 * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
6121 * 0b1..mask interrupt due to update of periph_clk_sel
6122 */
6123#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
6124#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
6125#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
6126/* ARM_PODF_LOADED
6127 * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created
6128 * 0b1..mask interrupt due to frequency change of arm_podf
6129 */
6130#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
6131/* @} */
6132
6133/* @name CCOSR - CCM Clock Output Source Register */
6134/* @{ */
6135#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
6136#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
6137/* CLKO1_SEL
6138 * 0b0000..USB1 PLL clock (divided by 2)
6139 * 0b0001..SYS PLL clock (divided by 2)
6140 * 0b0011..VIDEO PLL clock (divided by 2)
6141 * 0b0101..semc_clk_root
6142 * 0b0110..Reserved
6143 * 0b1010..lcdif_pix_clk_root
6144 * 0b1011..ahb_clk_root
6145 * 0b1100..ipg_clk_root
6146 * 0b1101..perclk_root
6147 * 0b1110..ckil_sync_clk_root
6148 * 0b1111..pll4_main_clk
6149 */
6150#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
6151#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
6152#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
6153/* CLKO1_DIV
6154 * 0b000..divide by 1
6155 * 0b001..divide by 2
6156 * 0b010..divide by 3
6157 * 0b011..divide by 4
6158 * 0b100..divide by 5
6159 * 0b101..divide by 6
6160 * 0b110..divide by 7
6161 * 0b111..divide by 8
6162 */
6163#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
6164#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
6165#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
6166/* CLKO1_EN
6167 * 0b0..CCM_CLKO1 disabled.
6168 * 0b1..CCM_CLKO1 enabled.
6169 */
6170#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
6171#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
6172#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
6173/* CLK_OUT_SEL
6174 * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
6175 * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
6176 */
6177#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
6178#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
6179#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
6180/* CLKO2_SEL
6181 * 0b00011..usdhc1_clk_root
6182 * 0b00110..lpi2c_clk_root
6183 * 0b01011..csi_clk_root
6184 * 0b01110..osc_clk
6185 * 0b10001..usdhc2_clk_root
6186 * 0b10010..sai1_clk_root
6187 * 0b10011..sai2_clk_root
6188 * 0b10100..sai3_clk_root (shared with ADC1 and ADC2 alt_clk root)
6189 * 0b10111..can_clk_root (FlexCAN, shared with CANFD)
6190 * 0b11011..flexspi_clk_root
6191 * 0b11100..uart_clk_root
6192 * 0b11101..spdif0_clk_root
6193 * 0b11111..Reserved
6194 */
6195#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
6196#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
6197#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
6198/* CLKO2_DIV
6199 * 0b000..divide by 1
6200 * 0b001..divide by 2
6201 * 0b010..divide by 3
6202 * 0b011..divide by 4
6203 * 0b100..divide by 5
6204 * 0b101..divide by 6
6205 * 0b110..divide by 7
6206 * 0b111..divide by 8
6207 */
6208#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
6209#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
6210#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
6211/* CLKO2_EN
6212 * 0b0..CCM_CLKO2 disabled.
6213 * 0b1..CCM_CLKO2 enabled.
6214 */
6215#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
6216/* @} */
6217
6218/* @name CGPR - CCM General Purpose Register */
6219/* @{ */
6220#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
6221#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
6222/* PMIC_DELAY_SCALER
6223 * 0b0..clock is not divided
6224 * 0b1..clock is divided /8
6225 */
6226#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
6227#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
6228#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
6229/* EFUSE_PROG_SUPPLY_GATE
6230 * 0b0..fuse programing supply voltage is gated off to the efuse module
6231 * 0b1..allow fuse programing.
6232 */
6233#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
6234#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
6235#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
6236/* SYS_MEM_DS_CTRL
6237 * 0b00..Disable memory DS mode always
6238 * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled
6239 * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode
6240 */
6241#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
6242#define CCM_CGPR_FPL_MASK (0x10000U)
6243#define CCM_CGPR_FPL_SHIFT (16U)
6244/* FPL - Fast PLL enable.
6245 * 0b0..Engage PLL enable default way.
6246 * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
6247 */
6248#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
6249#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
6250#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
6251/* INT_MEM_CLK_LPM
6252 * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode
6253 * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low
6254 * Power Modes (WAIT and STOP without power gating)
6255 */
6256#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
6257/* @} */
6258
6259/* @name CCGR0 - CCM Clock Gating Register 0 */
6260/* @{ */
6261#define CCM_CCGR0_CG0_MASK (0x3U)
6262#define CCM_CCGR0_CG0_SHIFT (0U)
6263#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
6264#define CCM_CCGR0_CG1_MASK (0xCU)
6265#define CCM_CCGR0_CG1_SHIFT (2U)
6266#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
6267#define CCM_CCGR0_CG2_MASK (0x30U)
6268#define CCM_CCGR0_CG2_SHIFT (4U)
6269#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
6270#define CCM_CCGR0_CG3_MASK (0xC0U)
6271#define CCM_CCGR0_CG3_SHIFT (6U)
6272#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
6273#define CCM_CCGR0_CG4_MASK (0x300U)
6274#define CCM_CCGR0_CG4_SHIFT (8U)
6275#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
6276#define CCM_CCGR0_CG5_MASK (0xC00U)
6277#define CCM_CCGR0_CG5_SHIFT (10U)
6278#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
6279#define CCM_CCGR0_CG6_MASK (0x3000U)
6280#define CCM_CCGR0_CG6_SHIFT (12U)
6281#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
6282#define CCM_CCGR0_CG7_MASK (0xC000U)
6283#define CCM_CCGR0_CG7_SHIFT (14U)
6284#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
6285#define CCM_CCGR0_CG8_MASK (0x30000U)
6286#define CCM_CCGR0_CG8_SHIFT (16U)
6287#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
6288#define CCM_CCGR0_CG9_MASK (0xC0000U)
6289#define CCM_CCGR0_CG9_SHIFT (18U)
6290#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
6291#define CCM_CCGR0_CG10_MASK (0x300000U)
6292#define CCM_CCGR0_CG10_SHIFT (20U)
6293#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
6294#define CCM_CCGR0_CG11_MASK (0xC00000U)
6295#define CCM_CCGR0_CG11_SHIFT (22U)
6296#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
6297#define CCM_CCGR0_CG12_MASK (0x3000000U)
6298#define CCM_CCGR0_CG12_SHIFT (24U)
6299#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
6300#define CCM_CCGR0_CG13_MASK (0xC000000U)
6301#define CCM_CCGR0_CG13_SHIFT (26U)
6302#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
6303#define CCM_CCGR0_CG14_MASK (0x30000000U)
6304#define CCM_CCGR0_CG14_SHIFT (28U)
6305#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
6306#define CCM_CCGR0_CG15_MASK (0xC0000000U)
6307#define CCM_CCGR0_CG15_SHIFT (30U)
6308#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
6309/* @} */
6310
6311/* @name CCGR1 - CCM Clock Gating Register 1 */
6312/* @{ */
6313#define CCM_CCGR1_CG0_MASK (0x3U)
6314#define CCM_CCGR1_CG0_SHIFT (0U)
6315#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
6316#define CCM_CCGR1_CG1_MASK (0xCU)
6317#define CCM_CCGR1_CG1_SHIFT (2U)
6318#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
6319#define CCM_CCGR1_CG2_MASK (0x30U)
6320#define CCM_CCGR1_CG2_SHIFT (4U)
6321#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
6322#define CCM_CCGR1_CG3_MASK (0xC0U)
6323#define CCM_CCGR1_CG3_SHIFT (6U)
6324#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
6325#define CCM_CCGR1_CG4_MASK (0x300U)
6326#define CCM_CCGR1_CG4_SHIFT (8U)
6327#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
6328#define CCM_CCGR1_CG5_MASK (0xC00U)
6329#define CCM_CCGR1_CG5_SHIFT (10U)
6330#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
6331#define CCM_CCGR1_CG6_MASK (0x3000U)
6332#define CCM_CCGR1_CG6_SHIFT (12U)
6333#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
6334#define CCM_CCGR1_CG7_MASK (0xC000U)
6335#define CCM_CCGR1_CG7_SHIFT (14U)
6336#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
6337#define CCM_CCGR1_CG8_MASK (0x30000U)
6338#define CCM_CCGR1_CG8_SHIFT (16U)
6339#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
6340#define CCM_CCGR1_CG9_MASK (0xC0000U)
6341#define CCM_CCGR1_CG9_SHIFT (18U)
6342#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
6343#define CCM_CCGR1_CG10_MASK (0x300000U)
6344#define CCM_CCGR1_CG10_SHIFT (20U)
6345#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
6346#define CCM_CCGR1_CG11_MASK (0xC00000U)
6347#define CCM_CCGR1_CG11_SHIFT (22U)
6348#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
6349#define CCM_CCGR1_CG12_MASK (0x3000000U)
6350#define CCM_CCGR1_CG12_SHIFT (24U)
6351#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
6352#define CCM_CCGR1_CG13_MASK (0xC000000U)
6353#define CCM_CCGR1_CG13_SHIFT (26U)
6354#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
6355#define CCM_CCGR1_CG14_MASK (0x30000000U)
6356#define CCM_CCGR1_CG14_SHIFT (28U)
6357#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
6358#define CCM_CCGR1_CG15_MASK (0xC0000000U)
6359#define CCM_CCGR1_CG15_SHIFT (30U)
6360#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
6361/* @} */
6362
6363/* @name CCGR2 - CCM Clock Gating Register 2 */
6364/* @{ */
6365#define CCM_CCGR2_CG0_MASK (0x3U)
6366#define CCM_CCGR2_CG0_SHIFT (0U)
6367#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
6368#define CCM_CCGR2_CG1_MASK (0xCU)
6369#define CCM_CCGR2_CG1_SHIFT (2U)
6370#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
6371#define CCM_CCGR2_CG2_MASK (0x30U)
6372#define CCM_CCGR2_CG2_SHIFT (4U)
6373#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
6374#define CCM_CCGR2_CG3_MASK (0xC0U)
6375#define CCM_CCGR2_CG3_SHIFT (6U)
6376#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
6377#define CCM_CCGR2_CG4_MASK (0x300U)
6378#define CCM_CCGR2_CG4_SHIFT (8U)
6379#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
6380#define CCM_CCGR2_CG5_MASK (0xC00U)
6381#define CCM_CCGR2_CG5_SHIFT (10U)
6382#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
6383#define CCM_CCGR2_CG6_MASK (0x3000U)
6384#define CCM_CCGR2_CG6_SHIFT (12U)
6385#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
6386#define CCM_CCGR2_CG7_MASK (0xC000U)
6387#define CCM_CCGR2_CG7_SHIFT (14U)
6388#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
6389#define CCM_CCGR2_CG8_MASK (0x30000U)
6390#define CCM_CCGR2_CG8_SHIFT (16U)
6391#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
6392#define CCM_CCGR2_CG9_MASK (0xC0000U)
6393#define CCM_CCGR2_CG9_SHIFT (18U)
6394#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
6395#define CCM_CCGR2_CG10_MASK (0x300000U)
6396#define CCM_CCGR2_CG10_SHIFT (20U)
6397#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
6398#define CCM_CCGR2_CG11_MASK (0xC00000U)
6399#define CCM_CCGR2_CG11_SHIFT (22U)
6400#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
6401#define CCM_CCGR2_CG12_MASK (0x3000000U)
6402#define CCM_CCGR2_CG12_SHIFT (24U)
6403#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
6404#define CCM_CCGR2_CG13_MASK (0xC000000U)
6405#define CCM_CCGR2_CG13_SHIFT (26U)
6406#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
6407#define CCM_CCGR2_CG14_MASK (0x30000000U)
6408#define CCM_CCGR2_CG14_SHIFT (28U)
6409#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
6410#define CCM_CCGR2_CG15_MASK (0xC0000000U)
6411#define CCM_CCGR2_CG15_SHIFT (30U)
6412#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
6413/* @} */
6414
6415/* @name CCGR3 - CCM Clock Gating Register 3 */
6416/* @{ */
6417#define CCM_CCGR3_CG0_MASK (0x3U)
6418#define CCM_CCGR3_CG0_SHIFT (0U)
6419#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
6420#define CCM_CCGR3_CG1_MASK (0xCU)
6421#define CCM_CCGR3_CG1_SHIFT (2U)
6422#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
6423#define CCM_CCGR3_CG2_MASK (0x30U)
6424#define CCM_CCGR3_CG2_SHIFT (4U)
6425#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
6426#define CCM_CCGR3_CG3_MASK (0xC0U)
6427#define CCM_CCGR3_CG3_SHIFT (6U)
6428#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
6429#define CCM_CCGR3_CG4_MASK (0x300U)
6430#define CCM_CCGR3_CG4_SHIFT (8U)
6431#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
6432#define CCM_CCGR3_CG5_MASK (0xC00U)
6433#define CCM_CCGR3_CG5_SHIFT (10U)
6434#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
6435#define CCM_CCGR3_CG6_MASK (0x3000U)
6436#define CCM_CCGR3_CG6_SHIFT (12U)
6437#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
6438#define CCM_CCGR3_CG7_MASK (0xC000U)
6439#define CCM_CCGR3_CG7_SHIFT (14U)
6440#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
6441#define CCM_CCGR3_CG8_MASK (0x30000U)
6442#define CCM_CCGR3_CG8_SHIFT (16U)
6443#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
6444#define CCM_CCGR3_CG9_MASK (0xC0000U)
6445#define CCM_CCGR3_CG9_SHIFT (18U)
6446#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
6447#define CCM_CCGR3_CG10_MASK (0x300000U)
6448#define CCM_CCGR3_CG10_SHIFT (20U)
6449#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
6450#define CCM_CCGR3_CG11_MASK (0xC00000U)
6451#define CCM_CCGR3_CG11_SHIFT (22U)
6452#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
6453#define CCM_CCGR3_CG12_MASK (0x3000000U)
6454#define CCM_CCGR3_CG12_SHIFT (24U)
6455#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
6456#define CCM_CCGR3_CG13_MASK (0xC000000U)
6457#define CCM_CCGR3_CG13_SHIFT (26U)
6458#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
6459#define CCM_CCGR3_CG14_MASK (0x30000000U)
6460#define CCM_CCGR3_CG14_SHIFT (28U)
6461#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
6462#define CCM_CCGR3_CG15_MASK (0xC0000000U)
6463#define CCM_CCGR3_CG15_SHIFT (30U)
6464#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
6465/* @} */
6466
6467/* @name CCGR4 - CCM Clock Gating Register 4 */
6468/* @{ */
6469#define CCM_CCGR4_CG0_MASK (0x3U)
6470#define CCM_CCGR4_CG0_SHIFT (0U)
6471#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
6472#define CCM_CCGR4_CG1_MASK (0xCU)
6473#define CCM_CCGR4_CG1_SHIFT (2U)
6474#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
6475#define CCM_CCGR4_CG2_MASK (0x30U)
6476#define CCM_CCGR4_CG2_SHIFT (4U)
6477#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
6478#define CCM_CCGR4_CG3_MASK (0xC0U)
6479#define CCM_CCGR4_CG3_SHIFT (6U)
6480#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
6481#define CCM_CCGR4_CG4_MASK (0x300U)
6482#define CCM_CCGR4_CG4_SHIFT (8U)
6483#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
6484#define CCM_CCGR4_CG5_MASK (0xC00U)
6485#define CCM_CCGR4_CG5_SHIFT (10U)
6486#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
6487#define CCM_CCGR4_CG6_MASK (0x3000U)
6488#define CCM_CCGR4_CG6_SHIFT (12U)
6489#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
6490#define CCM_CCGR4_CG7_MASK (0xC000U)
6491#define CCM_CCGR4_CG7_SHIFT (14U)
6492#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
6493#define CCM_CCGR4_CG8_MASK (0x30000U)
6494#define CCM_CCGR4_CG8_SHIFT (16U)
6495#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
6496#define CCM_CCGR4_CG9_MASK (0xC0000U)
6497#define CCM_CCGR4_CG9_SHIFT (18U)
6498#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
6499#define CCM_CCGR4_CG10_MASK (0x300000U)
6500#define CCM_CCGR4_CG10_SHIFT (20U)
6501#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
6502#define CCM_CCGR4_CG11_MASK (0xC00000U)
6503#define CCM_CCGR4_CG11_SHIFT (22U)
6504#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
6505#define CCM_CCGR4_CG12_MASK (0x3000000U)
6506#define CCM_CCGR4_CG12_SHIFT (24U)
6507#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
6508#define CCM_CCGR4_CG13_MASK (0xC000000U)
6509#define CCM_CCGR4_CG13_SHIFT (26U)
6510#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
6511#define CCM_CCGR4_CG14_MASK (0x30000000U)
6512#define CCM_CCGR4_CG14_SHIFT (28U)
6513#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
6514#define CCM_CCGR4_CG15_MASK (0xC0000000U)
6515#define CCM_CCGR4_CG15_SHIFT (30U)
6516#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
6517/* @} */
6518
6519/* @name CCGR5 - CCM Clock Gating Register 5 */
6520/* @{ */
6521#define CCM_CCGR5_CG0_MASK (0x3U)
6522#define CCM_CCGR5_CG0_SHIFT (0U)
6523#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
6524#define CCM_CCGR5_CG1_MASK (0xCU)
6525#define CCM_CCGR5_CG1_SHIFT (2U)
6526#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
6527#define CCM_CCGR5_CG2_MASK (0x30U)
6528#define CCM_CCGR5_CG2_SHIFT (4U)
6529#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
6530#define CCM_CCGR5_CG3_MASK (0xC0U)
6531#define CCM_CCGR5_CG3_SHIFT (6U)
6532#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
6533#define CCM_CCGR5_CG4_MASK (0x300U)
6534#define CCM_CCGR5_CG4_SHIFT (8U)
6535#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
6536#define CCM_CCGR5_CG5_MASK (0xC00U)
6537#define CCM_CCGR5_CG5_SHIFT (10U)
6538#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
6539#define CCM_CCGR5_CG6_MASK (0x3000U)
6540#define CCM_CCGR5_CG6_SHIFT (12U)
6541#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
6542#define CCM_CCGR5_CG7_MASK (0xC000U)
6543#define CCM_CCGR5_CG7_SHIFT (14U)
6544#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
6545#define CCM_CCGR5_CG8_MASK (0x30000U)
6546#define CCM_CCGR5_CG8_SHIFT (16U)
6547#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
6548#define CCM_CCGR5_CG9_MASK (0xC0000U)
6549#define CCM_CCGR5_CG9_SHIFT (18U)
6550#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
6551#define CCM_CCGR5_CG10_MASK (0x300000U)
6552#define CCM_CCGR5_CG10_SHIFT (20U)
6553#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
6554#define CCM_CCGR5_CG11_MASK (0xC00000U)
6555#define CCM_CCGR5_CG11_SHIFT (22U)
6556#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
6557#define CCM_CCGR5_CG12_MASK (0x3000000U)
6558#define CCM_CCGR5_CG12_SHIFT (24U)
6559#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
6560#define CCM_CCGR5_CG13_MASK (0xC000000U)
6561#define CCM_CCGR5_CG13_SHIFT (26U)
6562#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
6563#define CCM_CCGR5_CG14_MASK (0x30000000U)
6564#define CCM_CCGR5_CG14_SHIFT (28U)
6565#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
6566#define CCM_CCGR5_CG15_MASK (0xC0000000U)
6567#define CCM_CCGR5_CG15_SHIFT (30U)
6568#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
6569/* @} */
6570
6571/* @name CCGR6 - CCM Clock Gating Register 6 */
6572/* @{ */
6573#define CCM_CCGR6_CG0_MASK (0x3U)
6574#define CCM_CCGR6_CG0_SHIFT (0U)
6575#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
6576#define CCM_CCGR6_CG1_MASK (0xCU)
6577#define CCM_CCGR6_CG1_SHIFT (2U)
6578#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
6579#define CCM_CCGR6_CG2_MASK (0x30U)
6580#define CCM_CCGR6_CG2_SHIFT (4U)
6581#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
6582#define CCM_CCGR6_CG3_MASK (0xC0U)
6583#define CCM_CCGR6_CG3_SHIFT (6U)
6584#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
6585#define CCM_CCGR6_CG4_MASK (0x300U)
6586#define CCM_CCGR6_CG4_SHIFT (8U)
6587#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
6588#define CCM_CCGR6_CG5_MASK (0xC00U)
6589#define CCM_CCGR6_CG5_SHIFT (10U)
6590#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
6591#define CCM_CCGR6_CG6_MASK (0x3000U)
6592#define CCM_CCGR6_CG6_SHIFT (12U)
6593#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
6594#define CCM_CCGR6_CG7_MASK (0xC000U)
6595#define CCM_CCGR6_CG7_SHIFT (14U)
6596#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
6597#define CCM_CCGR6_CG8_MASK (0x30000U)
6598#define CCM_CCGR6_CG8_SHIFT (16U)
6599#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
6600#define CCM_CCGR6_CG9_MASK (0xC0000U)
6601#define CCM_CCGR6_CG9_SHIFT (18U)
6602#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
6603#define CCM_CCGR6_CG10_MASK (0x300000U)
6604#define CCM_CCGR6_CG10_SHIFT (20U)
6605#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
6606#define CCM_CCGR6_CG11_MASK (0xC00000U)
6607#define CCM_CCGR6_CG11_SHIFT (22U)
6608#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
6609#define CCM_CCGR6_CG12_MASK (0x3000000U)
6610#define CCM_CCGR6_CG12_SHIFT (24U)
6611#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
6612#define CCM_CCGR6_CG13_MASK (0xC000000U)
6613#define CCM_CCGR6_CG13_SHIFT (26U)
6614#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
6615#define CCM_CCGR6_CG14_MASK (0x30000000U)
6616#define CCM_CCGR6_CG14_SHIFT (28U)
6617#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
6618#define CCM_CCGR6_CG15_MASK (0xC0000000U)
6619#define CCM_CCGR6_CG15_SHIFT (30U)
6620#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
6621/* @} */
6622
6623/* @name CCGR7 - CCM Clock Gating Register 7 */
6624/* @{ */
6625#define CCM_CCGR7_CG0_MASK (0x3U)
6626#define CCM_CCGR7_CG0_SHIFT (0U)
6627#define CCM_CCGR7_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG0_SHIFT)) & CCM_CCGR7_CG0_MASK)
6628#define CCM_CCGR7_CG1_MASK (0xCU)
6629#define CCM_CCGR7_CG1_SHIFT (2U)
6630#define CCM_CCGR7_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG1_SHIFT)) & CCM_CCGR7_CG1_MASK)
6631#define CCM_CCGR7_CG2_MASK (0x30U)
6632#define CCM_CCGR7_CG2_SHIFT (4U)
6633#define CCM_CCGR7_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG2_SHIFT)) & CCM_CCGR7_CG2_MASK)
6634#define CCM_CCGR7_CG3_MASK (0xC0U)
6635#define CCM_CCGR7_CG3_SHIFT (6U)
6636#define CCM_CCGR7_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG3_SHIFT)) & CCM_CCGR7_CG3_MASK)
6637#define CCM_CCGR7_CG4_MASK (0x300U)
6638#define CCM_CCGR7_CG4_SHIFT (8U)
6639#define CCM_CCGR7_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG4_SHIFT)) & CCM_CCGR7_CG4_MASK)
6640#define CCM_CCGR7_CG5_MASK (0xC00U)
6641#define CCM_CCGR7_CG5_SHIFT (10U)
6642#define CCM_CCGR7_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG5_SHIFT)) & CCM_CCGR7_CG5_MASK)
6643#define CCM_CCGR7_CG6_MASK (0x3000U)
6644#define CCM_CCGR7_CG6_SHIFT (12U)
6645#define CCM_CCGR7_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG6_SHIFT)) & CCM_CCGR7_CG6_MASK)
6646/* @} */
6647
6648/* @name CMEOR - CCM Module Enable Overide Register */
6649/* @{ */
6650#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
6651#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
6652/* MOD_EN_OV_GPT
6653 * 0b0..don't override module enable signal
6654 * 0b1..override module enable signal
6655 */
6656#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
6657#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
6658#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
6659/* MOD_EN_OV_PIT
6660 * 0b0..don't override module enable signal
6661 * 0b1..override module enable signal
6662 */
6663#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
6664#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
6665#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
6666/* MOD_EN_USDHC
6667 * 0b0..don't override module enable signal
6668 * 0b1..override module enable signal
6669 */
6670#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
6671#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
6672#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
6673/* MOD_EN_OV_TRNG
6674 * 0b0..don't override module enable signal
6675 * 0b1..override module enable signal
6676 */
6677#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
6678#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK (0x400U)
6679#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT (10U)
6680/* MOD_EN_OV_CANFD_CPI
6681 * 0b0..don't override module enable signal
6682 * 0b1..override module enable signal
6683 */
6684#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK)
6685#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
6686#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
6687/* MOD_EN_OV_CAN2_CPI
6688 * 0b0..don't override module enable signal
6689 * 0b1..override module enable signal
6690 */
6691#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
6692#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
6693#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
6694/* MOD_EN_OV_CAN1_CPI
6695 * 0b0..don't overide module enable signal
6696 * 0b1..overide module enable signal
6697 */
6698#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
6699/* @} */
6700
6701
6702/*
6703 * @}
6704 */ /* end of group CCM_Register_Masks */
6705
6706
6707/* CCM - Peripheral instance base addresses */
6708/* Peripheral CCM base address */
6709#define CCM_BASE (0x400FC000u)
6710/* Peripheral CCM base pointer */
6711#define CCM ((CCM_Type *)CCM_BASE)
6712/* Array initializer of CCM peripheral base addresses */
6713#define CCM_BASE_ADDRS { CCM_BASE }
6714/* Array initializer of CCM peripheral base pointers */
6715#define CCM_BASE_PTRS { CCM }
6716/* Interrupt vectors for the CCM peripheral type */
6717#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
6718
6719/*
6720 * @}
6721 */ /* end of group CCM_Peripheral_Access_Layer */
6722
6723
6724/* ----------------------------------------------------------------------------
6725 -- CCM_ANALOG Peripheral Access Layer
6726 ---------------------------------------------------------------------------- */
6727
6728/*
6729 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
6730 * @{
6731 */
6732
6733/* CCM_ANALOG - Register Layout Typedef */
6734typedef struct {
6735 __IO uint32_t PLL_ARM;
6736 __IO uint32_t PLL_ARM_SET;
6737 __IO uint32_t PLL_ARM_CLR;
6738 __IO uint32_t PLL_ARM_TOG;
6739 __IO uint32_t PLL_USB1;
6740 __IO uint32_t PLL_USB1_SET;
6741 __IO uint32_t PLL_USB1_CLR;
6742 __IO uint32_t PLL_USB1_TOG;
6743 __IO uint32_t PLL_USB2;
6744 __IO uint32_t PLL_USB2_SET;
6745 __IO uint32_t PLL_USB2_CLR;
6746 __IO uint32_t PLL_USB2_TOG;
6747 __IO uint32_t PLL_SYS;
6748 __IO uint32_t PLL_SYS_SET;
6749 __IO uint32_t PLL_SYS_CLR;
6750 __IO uint32_t PLL_SYS_TOG;
6751 __IO uint32_t PLL_SYS_SS;
6752 uint8_t RESERVED_0[12];
6753 __IO uint32_t PLL_SYS_NUM;
6754 uint8_t RESERVED_1[12];
6755 __IO uint32_t PLL_SYS_DENOM;
6756 uint8_t RESERVED_2[12];
6757 __IO uint32_t PLL_AUDIO;
6758 __IO uint32_t PLL_AUDIO_SET;
6759 __IO uint32_t PLL_AUDIO_CLR;
6760 __IO uint32_t PLL_AUDIO_TOG;
6761 __IO uint32_t PLL_AUDIO_NUM;
6762 uint8_t RESERVED_3[12];
6763 __IO uint32_t PLL_AUDIO_DENOM;
6764 uint8_t RESERVED_4[12];
6765 __IO uint32_t PLL_VIDEO;
6766 __IO uint32_t PLL_VIDEO_SET;
6767 __IO uint32_t PLL_VIDEO_CLR;
6768 __IO uint32_t PLL_VIDEO_TOG;
6769 __IO uint32_t PLL_VIDEO_NUM;
6770 uint8_t RESERVED_5[12];
6771 __IO uint32_t PLL_VIDEO_DENOM;
6772 uint8_t RESERVED_6[28];
6773 __IO uint32_t PLL_ENET;
6774 __IO uint32_t PLL_ENET_SET;
6775 __IO uint32_t PLL_ENET_CLR;
6776 __IO uint32_t PLL_ENET_TOG;
6777 __IO uint32_t PFD_480;
6778 __IO uint32_t PFD_480_SET;
6779 __IO uint32_t PFD_480_CLR;
6780 __IO uint32_t PFD_480_TOG;
6781 __IO uint32_t PFD_528;
6782 __IO uint32_t PFD_528_SET;
6783 __IO uint32_t PFD_528_CLR;
6784 __IO uint32_t PFD_528_TOG;
6785 uint8_t RESERVED_7[64];
6786 __IO uint32_t MISC0;
6787 __IO uint32_t MISC0_SET;
6788 __IO uint32_t MISC0_CLR;
6789 __IO uint32_t MISC0_TOG;
6790 __IO uint32_t MISC1;
6791 __IO uint32_t MISC1_SET;
6792 __IO uint32_t MISC1_CLR;
6793 __IO uint32_t MISC1_TOG;
6794 __IO uint32_t MISC2;
6795 __IO uint32_t MISC2_SET;
6796 __IO uint32_t MISC2_CLR;
6797 __IO uint32_t MISC2_TOG;
6798} CCM_ANALOG_Type;
6799
6800/* ----------------------------------------------------------------------------
6801 -- CCM_ANALOG Register Masks
6802 ---------------------------------------------------------------------------- */
6803
6804/*
6805 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
6806 * @{
6807 */
6808
6809/* @name PLL_ARM - Analog ARM PLL control Register */
6810/* @{ */
6811#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
6812#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
6813#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
6814#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
6815#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
6816#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
6817#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
6818#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
6819#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
6820#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
6821#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
6822/* BYPASS_CLK_SRC
6823 * 0b00..Select the 24MHz oscillator as source.
6824 * 0b01..Select the CLK1_N / CLK1_P as source.
6825 * 0b10..Reserved1
6826 * 0b11..Reserved2
6827 */
6828#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
6829#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
6830#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
6831#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
6832#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
6833#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
6834#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
6835#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
6836#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
6837#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
6838/* @} */
6839
6840/* @name PLL_ARM_SET - Analog ARM PLL control Register */
6841/* @{ */
6842#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
6843#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
6844#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
6845#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
6846#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
6847#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
6848#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
6849#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
6850#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
6851#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6852#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
6853/* BYPASS_CLK_SRC
6854 * 0b00..Select the 24MHz oscillator as source.
6855 * 0b01..Select the CLK1_N / CLK1_P as source.
6856 * 0b10..Reserved1
6857 * 0b11..Reserved2
6858 */
6859#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
6860#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
6861#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
6862#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
6863#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
6864#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
6865#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
6866#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
6867#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
6868#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
6869/* @} */
6870
6871/* @name PLL_ARM_CLR - Analog ARM PLL control Register */
6872/* @{ */
6873#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
6874#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
6875#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
6876#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
6877#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
6878#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
6879#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
6880#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
6881#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
6882#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6883#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6884/* BYPASS_CLK_SRC
6885 * 0b00..Select the 24MHz oscillator as source.
6886 * 0b01..Select the CLK1_N / CLK1_P as source.
6887 * 0b10..Reserved1
6888 * 0b11..Reserved2
6889 */
6890#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
6891#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
6892#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
6893#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
6894#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
6895#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
6896#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
6897#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
6898#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
6899#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
6900/* @} */
6901
6902/* @name PLL_ARM_TOG - Analog ARM PLL control Register */
6903/* @{ */
6904#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
6905#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
6906#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
6907#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
6908#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
6909#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
6910#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
6911#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
6912#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
6913#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6914#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6915/* BYPASS_CLK_SRC
6916 * 0b00..Select the 24MHz oscillator as source.
6917 * 0b01..Select the CLK1_N / CLK1_P as source.
6918 * 0b10..Reserved1
6919 * 0b11..Reserved2
6920 */
6921#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
6922#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
6923#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
6924#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
6925#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
6926#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
6927#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
6928#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
6929#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
6930#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
6931/* @} */
6932
6933/* @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
6934/* @{ */
6935#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
6936#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
6937#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
6938#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
6939#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
6940/* EN_USB_CLKS
6941 * 0b0..PLL outputs for USBPHYn off.
6942 * 0b1..PLL outputs for USBPHYn on.
6943 */
6944#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
6945#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
6946#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
6947#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
6948#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
6949#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
6950#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
6951#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
6952#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
6953/* BYPASS_CLK_SRC
6954 * 0b00..Select the 24MHz oscillator as source.
6955 * 0b01..Select the CLK1_N / CLK1_P as source.
6956 */
6957#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
6958#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
6959#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
6960#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
6961#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
6962#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
6963#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
6964/* @} */
6965
6966/* @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
6967/* @{ */
6968#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
6969#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
6970#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
6971#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
6972#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
6973/* EN_USB_CLKS
6974 * 0b0..PLL outputs for USBPHYn off.
6975 * 0b1..PLL outputs for USBPHYn on.
6976 */
6977#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
6978#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
6979#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
6980#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
6981#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
6982#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
6983#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
6984#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6985#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
6986/* BYPASS_CLK_SRC
6987 * 0b00..Select the 24MHz oscillator as source.
6988 * 0b01..Select the CLK1_N / CLK1_P as source.
6989 */
6990#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
6991#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
6992#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
6993#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
6994#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
6995#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
6996#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
6997/* @} */
6998
6999/* @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
7000/* @{ */
7001#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
7002#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
7003#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
7004#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
7005#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
7006/* EN_USB_CLKS
7007 * 0b0..PLL outputs for USBPHYn off.
7008 * 0b1..PLL outputs for USBPHYn on.
7009 */
7010#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
7011#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
7012#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
7013#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
7014#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
7015#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
7016#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
7017#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7018#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7019/* BYPASS_CLK_SRC
7020 * 0b00..Select the 24MHz oscillator as source.
7021 * 0b01..Select the CLK1_N / CLK1_P as source.
7022 */
7023#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
7024#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
7025#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
7026#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
7027#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
7028#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
7029#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
7030/* @} */
7031
7032/* @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
7033/* @{ */
7034#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
7035#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
7036#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
7037#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
7038#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
7039/* EN_USB_CLKS
7040 * 0b0..PLL outputs for USBPHYn off.
7041 * 0b1..PLL outputs for USBPHYn on.
7042 */
7043#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
7044#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
7045#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
7046#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
7047#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
7048#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
7049#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
7050#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7051#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7052/* BYPASS_CLK_SRC
7053 * 0b00..Select the 24MHz oscillator as source.
7054 * 0b01..Select the CLK1_N / CLK1_P as source.
7055 */
7056#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
7057#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
7058#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
7059#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
7060#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
7061#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
7062#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
7063/* @} */
7064
7065/* @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */
7066/* @{ */
7067#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
7068#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
7069#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
7070#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
7071#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
7072#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
7073#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
7074#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
7075#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
7076#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
7077#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
7078#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
7079#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
7080#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
7081/* BYPASS_CLK_SRC
7082 * 0b00..Select the 24MHz oscillator as source.
7083 * 0b01..Select the CLK1_N / CLK1_P as source.
7084 * 0b10..Reserved1
7085 * 0b11..Reserved2
7086 */
7087#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
7088#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
7089#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
7090#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
7091#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
7092#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
7093#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
7094/* @} */
7095
7096/* @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */
7097/* @{ */
7098#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
7099#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
7100#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
7101#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
7102#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
7103#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
7104#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
7105#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
7106#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
7107#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
7108#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
7109#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
7110#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7111#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
7112/* BYPASS_CLK_SRC
7113 * 0b00..Select the 24MHz oscillator as source.
7114 * 0b01..Select the CLK1_N / CLK1_P as source.
7115 * 0b10..Reserved1
7116 * 0b11..Reserved2
7117 */
7118#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
7119#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
7120#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
7121#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
7122#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
7123#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
7124#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
7125/* @} */
7126
7127/* @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */
7128/* @{ */
7129#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
7130#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
7131#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
7132#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
7133#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
7134#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
7135#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
7136#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
7137#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
7138#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
7139#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
7140#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
7141#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7142#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7143/* BYPASS_CLK_SRC
7144 * 0b00..Select the 24MHz oscillator as source.
7145 * 0b01..Select the CLK1_N / CLK1_P as source.
7146 * 0b10..Reserved1
7147 * 0b11..Reserved2
7148 */
7149#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
7150#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
7151#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
7152#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
7153#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
7154#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
7155#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
7156/* @} */
7157
7158/* @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */
7159/* @{ */
7160#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
7161#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
7162#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
7163#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
7164#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
7165#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
7166#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
7167#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
7168#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
7169#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
7170#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
7171#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
7172#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7173#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7174/* BYPASS_CLK_SRC
7175 * 0b00..Select the 24MHz oscillator as source.
7176 * 0b01..Select the CLK1_N / CLK1_P as source.
7177 * 0b10..Reserved1
7178 * 0b11..Reserved2
7179 */
7180#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
7181#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
7182#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
7183#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
7184#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
7185#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
7186#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
7187/* @} */
7188
7189/* @name PLL_SYS - Analog System PLL Control Register */
7190/* @{ */
7191#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
7192#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
7193#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
7194#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
7195#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
7196#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
7197#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
7198#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
7199#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
7200#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
7201#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
7202/* BYPASS_CLK_SRC
7203 * 0b00..Select the 24MHz oscillator as source.
7204 * 0b01..Select the CLK1_N / CLK1_P as source.
7205 */
7206#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
7207#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
7208#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
7209#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
7210#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
7211#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
7212#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
7213/* @} */
7214
7215/* @name PLL_SYS_SET - Analog System PLL Control Register */
7216/* @{ */
7217#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
7218#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
7219#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
7220#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
7221#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
7222#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
7223#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
7224#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
7225#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
7226#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7227#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
7228/* BYPASS_CLK_SRC
7229 * 0b00..Select the 24MHz oscillator as source.
7230 * 0b01..Select the CLK1_N / CLK1_P as source.
7231 */
7232#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
7233#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
7234#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
7235#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
7236#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
7237#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
7238#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
7239/* @} */
7240
7241/* @name PLL_SYS_CLR - Analog System PLL Control Register */
7242/* @{ */
7243#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
7244#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
7245#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
7246#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
7247#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
7248#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
7249#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
7250#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
7251#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
7252#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7253#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7254/* BYPASS_CLK_SRC
7255 * 0b00..Select the 24MHz oscillator as source.
7256 * 0b01..Select the CLK1_N / CLK1_P as source.
7257 */
7258#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
7259#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
7260#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
7261#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
7262#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
7263#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
7264#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
7265/* @} */
7266
7267/* @name PLL_SYS_TOG - Analog System PLL Control Register */
7268/* @{ */
7269#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
7270#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
7271#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
7272#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
7273#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
7274#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
7275#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
7276#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
7277#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
7278#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7279#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7280/* BYPASS_CLK_SRC
7281 * 0b00..Select the 24MHz oscillator as source.
7282 * 0b01..Select the CLK1_N / CLK1_P as source.
7283 */
7284#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
7285#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
7286#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
7287#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
7288#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
7289#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
7290#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
7291/* @} */
7292
7293/* @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
7294/* @{ */
7295#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
7296#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
7297#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
7298#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
7299#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
7300/* ENABLE - Enable bit
7301 * 0b0..Spread spectrum modulation disabled
7302 * 0b1..Soread spectrum modulation enabled
7303 */
7304#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
7305#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
7306#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
7307#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
7308/* @} */
7309
7310/* @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
7311/* @{ */
7312#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
7313#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
7314#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
7315/* @} */
7316
7317/* @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
7318/* @{ */
7319#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
7320#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
7321#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
7322/* @} */
7323
7324/* @name PLL_AUDIO - Analog Audio PLL control Register */
7325/* @{ */
7326#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
7327#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
7328#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
7329#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
7330#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
7331#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
7332#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
7333#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
7334#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
7335#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
7336#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
7337/* BYPASS_CLK_SRC
7338 * 0b00..Select the 24MHz oscillator as source.
7339 * 0b01..Select the CLK1_N / CLK1_P as source.
7340 * 0b10..Reserved1
7341 * 0b11..Reserved2
7342 */
7343#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
7344#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
7345#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
7346#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
7347#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
7348#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
7349/* POST_DIV_SELECT
7350 * 0b00..Divide by 4.
7351 * 0b01..Divide by 2.
7352 * 0b10..Divide by 1.
7353 * 0b11..Reserved
7354 */
7355#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
7356#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
7357#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
7358#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
7359/* @} */
7360
7361/* @name PLL_AUDIO_SET - Analog Audio PLL control Register */
7362/* @{ */
7363#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
7364#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
7365#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
7366#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
7367#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
7368#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
7369#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
7370#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
7371#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
7372#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7373#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
7374/* BYPASS_CLK_SRC
7375 * 0b00..Select the 24MHz oscillator as source.
7376 * 0b01..Select the CLK1_N / CLK1_P as source.
7377 * 0b10..Reserved1
7378 * 0b11..Reserved2
7379 */
7380#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
7381#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
7382#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
7383#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
7384#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
7385#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
7386/* POST_DIV_SELECT
7387 * 0b00..Divide by 4.
7388 * 0b01..Divide by 2.
7389 * 0b10..Divide by 1.
7390 * 0b11..Reserved
7391 */
7392#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
7393#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
7394#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
7395#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
7396/* @} */
7397
7398/* @name PLL_AUDIO_CLR - Analog Audio PLL control Register */
7399/* @{ */
7400#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
7401#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
7402#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
7403#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
7404#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
7405#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
7406#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
7407#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
7408#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
7409#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7410#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7411/* BYPASS_CLK_SRC
7412 * 0b00..Select the 24MHz oscillator as source.
7413 * 0b01..Select the CLK1_N / CLK1_P as source.
7414 * 0b10..Reserved1
7415 * 0b11..Reserved2
7416 */
7417#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
7418#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
7419#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
7420#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
7421#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
7422#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
7423/* POST_DIV_SELECT
7424 * 0b00..Divide by 4.
7425 * 0b01..Divide by 2.
7426 * 0b10..Divide by 1.
7427 * 0b11..Reserved
7428 */
7429#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
7430#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
7431#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
7432#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
7433/* @} */
7434
7435/* @name PLL_AUDIO_TOG - Analog Audio PLL control Register */
7436/* @{ */
7437#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
7438#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
7439#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
7440#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
7441#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
7442#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
7443#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
7444#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
7445#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
7446#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7447#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7448/* BYPASS_CLK_SRC
7449 * 0b00..Select the 24MHz oscillator as source.
7450 * 0b01..Select the CLK1_N / CLK1_P as source.
7451 * 0b10..Reserved1
7452 * 0b11..Reserved2
7453 */
7454#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
7455#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
7456#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
7457#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
7458#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
7459#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
7460/* POST_DIV_SELECT
7461 * 0b00..Divide by 4.
7462 * 0b01..Divide by 2.
7463 * 0b10..Divide by 1.
7464 * 0b11..Reserved
7465 */
7466#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
7467#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
7468#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
7469#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
7470/* @} */
7471
7472/* @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */
7473/* @{ */
7474#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
7475#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
7476#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
7477/* @} */
7478
7479/* @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */
7480/* @{ */
7481#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
7482#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
7483#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
7484/* @} */
7485
7486/* @name PLL_VIDEO - Analog Video PLL control Register */
7487/* @{ */
7488#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
7489#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
7490#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
7491#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
7492#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
7493#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
7494#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
7495#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
7496#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
7497#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
7498#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
7499/* BYPASS_CLK_SRC
7500 * 0b00..Select the 24MHz oscillator as source.
7501 * 0b01..Select the CLK1_N / CLK1_P as source.
7502 * 0b10..Reserved1
7503 * 0b11..Reserved2
7504 */
7505#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
7506#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
7507#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
7508#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
7509#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
7510#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
7511/* POST_DIV_SELECT
7512 * 0b00..Divide by 4.
7513 * 0b01..Divide by 2.
7514 * 0b10..Divide by 1.
7515 * 0b11..Reserved
7516 */
7517#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
7518#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
7519#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
7520#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
7521/* @} */
7522
7523/* @name PLL_VIDEO_SET - Analog Video PLL control Register */
7524/* @{ */
7525#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
7526#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
7527#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
7528#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
7529#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
7530#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
7531#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
7532#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
7533#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
7534#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7535#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
7536/* BYPASS_CLK_SRC
7537 * 0b00..Select the 24MHz oscillator as source.
7538 * 0b01..Select the CLK1_N / CLK1_P as source.
7539 * 0b10..Reserved1
7540 * 0b11..Reserved2
7541 */
7542#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
7543#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
7544#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
7545#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
7546#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
7547#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
7548/* POST_DIV_SELECT
7549 * 0b00..Divide by 4.
7550 * 0b01..Divide by 2.
7551 * 0b10..Divide by 1.
7552 * 0b11..Reserved
7553 */
7554#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
7555#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
7556#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
7557#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
7558/* @} */
7559
7560/* @name PLL_VIDEO_CLR - Analog Video PLL control Register */
7561/* @{ */
7562#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
7563#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
7564#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
7565#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
7566#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
7567#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
7568#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
7569#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
7570#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
7571#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7572#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7573/* BYPASS_CLK_SRC
7574 * 0b00..Select the 24MHz oscillator as source.
7575 * 0b01..Select the CLK1_N / CLK1_P as source.
7576 * 0b10..Reserved1
7577 * 0b11..Reserved2
7578 */
7579#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
7580#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
7581#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
7582#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
7583#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
7584#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
7585/* POST_DIV_SELECT
7586 * 0b00..Divide by 4.
7587 * 0b01..Divide by 2.
7588 * 0b10..Divide by 1.
7589 * 0b11..Reserved
7590 */
7591#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
7592#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
7593#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
7594#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
7595/* @} */
7596
7597/* @name PLL_VIDEO_TOG - Analog Video PLL control Register */
7598/* @{ */
7599#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
7600#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
7601#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
7602#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
7603#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
7604#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
7605#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
7606#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
7607#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
7608#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7609#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7610/* BYPASS_CLK_SRC
7611 * 0b00..Select the 24MHz oscillator as source.
7612 * 0b01..Select the CLK1_N / CLK1_P as source.
7613 * 0b10..Reserved1
7614 * 0b11..Reserved2
7615 */
7616#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
7617#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
7618#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
7619#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
7620#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
7621#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
7622/* POST_DIV_SELECT
7623 * 0b00..Divide by 4.
7624 * 0b01..Divide by 2.
7625 * 0b10..Divide by 1.
7626 * 0b11..Reserved
7627 */
7628#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
7629#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
7630#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
7631#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
7632/* @} */
7633
7634/* @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */
7635/* @{ */
7636#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
7637#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
7638#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
7639/* @} */
7640
7641/* @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */
7642/* @{ */
7643#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
7644#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
7645#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
7646/* @} */
7647
7648/* @name PLL_ENET - Analog ENET PLL Control Register */
7649/* @{ */
7650#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
7651#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
7652#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
7653#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK (0xCU)
7654#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT (2U)
7655/* ENET2_DIV_SELECT
7656 * 0b00..25MHz
7657 * 0b01..50MHz
7658 * 0b10..100MHz (not 50% duty cycle)
7659 * 0b11..125MHz
7660 */
7661#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)
7662#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
7663#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
7664#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
7665#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
7666#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
7667#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
7668#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
7669#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
7670/* BYPASS_CLK_SRC
7671 * 0b00..Select the 24MHz oscillator as source.
7672 * 0b01..Select the CLK1_N / CLK1_P as source.
7673 * 0b10..Reserved1
7674 * 0b11..Reserved2
7675 */
7676#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
7677#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
7678#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
7679#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
7680#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK (0x100000U)
7681#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT (20U)
7682#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK)
7683#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
7684#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
7685#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
7686#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
7687#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
7688#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
7689/* @} */
7690
7691/* @name PLL_ENET_SET - Analog ENET PLL Control Register */
7692/* @{ */
7693#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
7694#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
7695#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
7696#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK (0xCU)
7697#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT (2U)
7698/* ENET2_DIV_SELECT
7699 * 0b00..25MHz
7700 * 0b01..50MHz
7701 * 0b10..100MHz (not 50% duty cycle)
7702 * 0b11..125MHz
7703 */
7704#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK)
7705#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
7706#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
7707#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
7708#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
7709#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
7710#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
7711#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7712#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
7713/* BYPASS_CLK_SRC
7714 * 0b00..Select the 24MHz oscillator as source.
7715 * 0b01..Select the CLK1_N / CLK1_P as source.
7716 * 0b10..Reserved1
7717 * 0b11..Reserved2
7718 */
7719#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
7720#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
7721#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
7722#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
7723#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK (0x100000U)
7724#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT (20U)
7725#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK)
7726#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
7727#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
7728#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
7729#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
7730#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
7731#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
7732/* @} */
7733
7734/* @name PLL_ENET_CLR - Analog ENET PLL Control Register */
7735/* @{ */
7736#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
7737#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
7738#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
7739#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK (0xCU)
7740#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT (2U)
7741/* ENET2_DIV_SELECT
7742 * 0b00..25MHz
7743 * 0b01..50MHz
7744 * 0b10..100MHz (not 50% duty cycle)
7745 * 0b11..125MHz
7746 */
7747#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK)
7748#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
7749#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
7750#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
7751#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
7752#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
7753#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
7754#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7755#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7756/* BYPASS_CLK_SRC
7757 * 0b00..Select the 24MHz oscillator as source.
7758 * 0b01..Select the CLK1_N / CLK1_P as source.
7759 * 0b10..Reserved1
7760 * 0b11..Reserved2
7761 */
7762#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
7763#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
7764#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
7765#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
7766#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK (0x100000U)
7767#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT (20U)
7768#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK)
7769#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
7770#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
7771#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
7772#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
7773#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
7774#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
7775/* @} */
7776
7777/* @name PLL_ENET_TOG - Analog ENET PLL Control Register */
7778/* @{ */
7779#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
7780#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
7781#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
7782#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK (0xCU)
7783#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT (2U)
7784/* ENET2_DIV_SELECT
7785 * 0b00..25MHz
7786 * 0b01..50MHz
7787 * 0b10..100MHz (not 50% duty cycle)
7788 * 0b11..125MHz
7789 */
7790#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK)
7791#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
7792#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
7793#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
7794#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
7795#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
7796#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
7797#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7798#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7799/* BYPASS_CLK_SRC
7800 * 0b00..Select the 24MHz oscillator as source.
7801 * 0b01..Select the CLK1_N / CLK1_P as source.
7802 * 0b10..Reserved1
7803 * 0b11..Reserved2
7804 */
7805#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
7806#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
7807#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
7808#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
7809#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK (0x100000U)
7810#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT (20U)
7811#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK)
7812#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
7813#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
7814#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
7815#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
7816#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
7817#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
7818/* @} */
7819
7820/* @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
7821/* @{ */
7822#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
7823#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
7824#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
7825#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
7826#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
7827#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
7828#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
7829#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
7830#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
7831#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
7832#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
7833#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
7834#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
7835#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
7836#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
7837#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
7838#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
7839#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
7840#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
7841#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
7842#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
7843#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
7844#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
7845#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
7846#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
7847#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
7848#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
7849#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
7850#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
7851#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
7852#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
7853#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
7854#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
7855#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
7856#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
7857#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
7858/* @} */
7859
7860/* @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
7861/* @{ */
7862#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
7863#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
7864#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
7865#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
7866#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
7867#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
7868#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
7869#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
7870#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
7871#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
7872#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
7873#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
7874#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
7875#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
7876#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
7877#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
7878#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
7879#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
7880#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
7881#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
7882#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
7883#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
7884#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
7885#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
7886#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
7887#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
7888#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
7889#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
7890#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
7891#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
7892#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
7893#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
7894#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
7895#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
7896#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
7897#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
7898/* @} */
7899
7900/* @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
7901/* @{ */
7902#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
7903#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
7904#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
7905#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
7906#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
7907#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
7908#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
7909#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
7910#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
7911#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
7912#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
7913#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
7914#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
7915#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
7916#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
7917#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
7918#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
7919#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
7920#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
7921#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
7922#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
7923#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
7924#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
7925#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
7926#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
7927#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
7928#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
7929#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
7930#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
7931#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
7932#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
7933#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
7934#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
7935#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
7936#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
7937#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
7938/* @} */
7939
7940/* @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
7941/* @{ */
7942#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
7943#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
7944#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
7945#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
7946#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
7947#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
7948#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
7949#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
7950#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
7951#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
7952#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
7953#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
7954#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
7955#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
7956#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
7957#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
7958#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
7959#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
7960#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
7961#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
7962#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
7963#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
7964#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
7965#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
7966#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
7967#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
7968#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
7969#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
7970#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
7971#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
7972#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
7973#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
7974#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
7975#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
7976#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
7977#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
7978/* @} */
7979
7980/* @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
7981/* @{ */
7982#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
7983#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
7984#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
7985#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
7986#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
7987#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
7988#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
7989#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
7990#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
7991#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
7992#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
7993#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
7994#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
7995#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
7996#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
7997#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
7998#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
7999#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
8000#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
8001#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
8002#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
8003#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
8004#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
8005#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
8006#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
8007#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
8008#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
8009#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
8010#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
8011#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
8012#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
8013#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
8014#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
8015#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
8016#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
8017#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
8018/* @} */
8019
8020/* @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8021/* @{ */
8022#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
8023#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
8024#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
8025#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
8026#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
8027#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
8028#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
8029#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
8030#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
8031#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
8032#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
8033#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
8034#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
8035#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
8036#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
8037#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
8038#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
8039#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
8040#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
8041#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
8042#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
8043#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
8044#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
8045#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
8046#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
8047#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
8048#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
8049#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
8050#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
8051#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
8052#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
8053#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
8054#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
8055#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
8056#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
8057#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
8058/* @} */
8059
8060/* @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8061/* @{ */
8062#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
8063#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
8064#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
8065#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
8066#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
8067#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
8068#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
8069#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
8070#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
8071#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
8072#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
8073#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
8074#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
8075#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
8076#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
8077#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
8078#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
8079#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
8080#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
8081#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
8082#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
8083#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
8084#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
8085#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
8086#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
8087#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
8088#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
8089#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
8090#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
8091#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
8092#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
8093#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
8094#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
8095#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8096#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
8097#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
8098/* @} */
8099
8100/* @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8101/* @{ */
8102#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
8103#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
8104#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
8105#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
8106#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
8107#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
8108#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
8109#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
8110#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
8111#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
8112#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
8113#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
8114#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
8115#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
8116#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
8117#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
8118#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
8119#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
8120#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
8121#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
8122#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
8123#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
8124#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
8125#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
8126#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
8127#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
8128#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
8129#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
8130#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
8131#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
8132#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
8133#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
8134#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
8135#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8136#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
8137#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
8138/* @} */
8139
8140/* @name MISC0 - Miscellaneous Register 0 */
8141/* @{ */
8142#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
8143#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
8144#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
8145#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
8146#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
8147/* REFTOP_SELFBIASOFF
8148 * 0b0..Uses coarse bias currents for startup
8149 * 0b1..Uses bandgap-based bias currents for best performance.
8150 */
8151#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
8152#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
8153#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
8154/* REFTOP_VBGADJ
8155 * 0b000..Nominal VBG
8156 * 0b001..VBG+0.78%
8157 * 0b010..VBG+1.56%
8158 * 0b011..VBG+2.34%
8159 * 0b100..VBG-0.78%
8160 * 0b101..VBG-1.56%
8161 * 0b110..VBG-2.34%
8162 * 0b111..VBG-3.12%
8163 */
8164#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
8165#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
8166#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
8167#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
8168#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
8169#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
8170/* STOP_MODE_CONFIG
8171 * 0b00..All analog except RTC powered down on stop mode assertion.
8172 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8173 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8174 * bandgap together with the rest analog is powered down.
8175 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8176 */
8177#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
8178#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
8179#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
8180/* DISCON_HIGH_SNVS
8181 * 0b0..Turn on the switch
8182 * 0b1..Turn off the switch
8183 */
8184#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
8185#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
8186#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
8187/* OSC_I
8188 * 0b00..Nominal
8189 * 0b01..Decrease current by 12.5%
8190 * 0b10..Decrease current by 25.0%
8191 * 0b11..Decrease current by 37.5%
8192 */
8193#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
8194#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
8195#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
8196#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
8197#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
8198#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
8199#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
8200#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
8201#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
8202/* CLKGATE_CTRL
8203 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
8204 * 0b1..Prevent the logic from ever gating off the clock.
8205 */
8206#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
8207#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
8208#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
8209/* CLKGATE_DELAY
8210 * 0b000..0.5ms
8211 * 0b001..1.0ms
8212 * 0b010..2.0ms
8213 * 0b011..3.0ms
8214 * 0b100..4.0ms
8215 * 0b101..5.0ms
8216 * 0b110..6.0ms
8217 * 0b111..7.0ms
8218 */
8219#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
8220#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
8221#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
8222/* RTC_XTAL_SOURCE
8223 * 0b0..Internal ring oscillator
8224 * 0b1..RTC_XTAL
8225 */
8226#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
8227#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
8228#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
8229#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
8230/* @} */
8231
8232/* @name MISC0_SET - Miscellaneous Register 0 */
8233/* @{ */
8234#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
8235#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
8236#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
8237#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
8238#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
8239/* REFTOP_SELFBIASOFF
8240 * 0b0..Uses coarse bias currents for startup
8241 * 0b1..Uses bandgap-based bias currents for best performance.
8242 */
8243#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
8244#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
8245#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
8246/* REFTOP_VBGADJ
8247 * 0b000..Nominal VBG
8248 * 0b001..VBG+0.78%
8249 * 0b010..VBG+1.56%
8250 * 0b011..VBG+2.34%
8251 * 0b100..VBG-0.78%
8252 * 0b101..VBG-1.56%
8253 * 0b110..VBG-2.34%
8254 * 0b111..VBG-3.12%
8255 */
8256#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
8257#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
8258#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
8259#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
8260#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
8261#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
8262/* STOP_MODE_CONFIG
8263 * 0b00..All analog except RTC powered down on stop mode assertion.
8264 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8265 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8266 * bandgap together with the rest analog is powered down.
8267 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8268 */
8269#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
8270#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
8271#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
8272/* DISCON_HIGH_SNVS
8273 * 0b0..Turn on the switch
8274 * 0b1..Turn off the switch
8275 */
8276#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
8277#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
8278#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
8279/* OSC_I
8280 * 0b00..Nominal
8281 * 0b01..Decrease current by 12.5%
8282 * 0b10..Decrease current by 25.0%
8283 * 0b11..Decrease current by 37.5%
8284 */
8285#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
8286#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
8287#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
8288#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
8289#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
8290#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
8291#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
8292#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
8293#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
8294/* CLKGATE_CTRL
8295 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
8296 * 0b1..Prevent the logic from ever gating off the clock.
8297 */
8298#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
8299#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
8300#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
8301/* CLKGATE_DELAY
8302 * 0b000..0.5ms
8303 * 0b001..1.0ms
8304 * 0b010..2.0ms
8305 * 0b011..3.0ms
8306 * 0b100..4.0ms
8307 * 0b101..5.0ms
8308 * 0b110..6.0ms
8309 * 0b111..7.0ms
8310 */
8311#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
8312#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
8313#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
8314/* RTC_XTAL_SOURCE
8315 * 0b0..Internal ring oscillator
8316 * 0b1..RTC_XTAL
8317 */
8318#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
8319#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
8320#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
8321#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
8322/* @} */
8323
8324/* @name MISC0_CLR - Miscellaneous Register 0 */
8325/* @{ */
8326#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
8327#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
8328#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
8329#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
8330#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
8331/* REFTOP_SELFBIASOFF
8332 * 0b0..Uses coarse bias currents for startup
8333 * 0b1..Uses bandgap-based bias currents for best performance.
8334 */
8335#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
8336#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
8337#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
8338/* REFTOP_VBGADJ
8339 * 0b000..Nominal VBG
8340 * 0b001..VBG+0.78%
8341 * 0b010..VBG+1.56%
8342 * 0b011..VBG+2.34%
8343 * 0b100..VBG-0.78%
8344 * 0b101..VBG-1.56%
8345 * 0b110..VBG-2.34%
8346 * 0b111..VBG-3.12%
8347 */
8348#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
8349#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
8350#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
8351#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
8352#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
8353#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
8354/* STOP_MODE_CONFIG
8355 * 0b00..All analog except RTC powered down on stop mode assertion.
8356 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8357 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8358 * bandgap together with the rest analog is powered down.
8359 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8360 */
8361#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
8362#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
8363#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
8364/* DISCON_HIGH_SNVS
8365 * 0b0..Turn on the switch
8366 * 0b1..Turn off the switch
8367 */
8368#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
8369#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
8370#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
8371/* OSC_I
8372 * 0b00..Nominal
8373 * 0b01..Decrease current by 12.5%
8374 * 0b10..Decrease current by 25.0%
8375 * 0b11..Decrease current by 37.5%
8376 */
8377#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
8378#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
8379#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
8380#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
8381#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
8382#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
8383#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
8384#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
8385#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
8386/* CLKGATE_CTRL
8387 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
8388 * 0b1..Prevent the logic from ever gating off the clock.
8389 */
8390#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
8391#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
8392#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
8393/* CLKGATE_DELAY
8394 * 0b000..0.5ms
8395 * 0b001..1.0ms
8396 * 0b010..2.0ms
8397 * 0b011..3.0ms
8398 * 0b100..4.0ms
8399 * 0b101..5.0ms
8400 * 0b110..6.0ms
8401 * 0b111..7.0ms
8402 */
8403#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
8404#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
8405#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
8406/* RTC_XTAL_SOURCE
8407 * 0b0..Internal ring oscillator
8408 * 0b1..RTC_XTAL
8409 */
8410#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
8411#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
8412#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
8413#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
8414/* @} */
8415
8416/* @name MISC0_TOG - Miscellaneous Register 0 */
8417/* @{ */
8418#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
8419#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
8420#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
8421#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
8422#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
8423/* REFTOP_SELFBIASOFF
8424 * 0b0..Uses coarse bias currents for startup
8425 * 0b1..Uses bandgap-based bias currents for best performance.
8426 */
8427#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
8428#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
8429#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
8430/* REFTOP_VBGADJ
8431 * 0b000..Nominal VBG
8432 * 0b001..VBG+0.78%
8433 * 0b010..VBG+1.56%
8434 * 0b011..VBG+2.34%
8435 * 0b100..VBG-0.78%
8436 * 0b101..VBG-1.56%
8437 * 0b110..VBG-2.34%
8438 * 0b111..VBG-3.12%
8439 */
8440#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
8441#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
8442#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
8443#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
8444#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
8445#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
8446/* STOP_MODE_CONFIG
8447 * 0b00..All analog except RTC powered down on stop mode assertion.
8448 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8449 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8450 * bandgap together with the rest analog is powered down.
8451 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8452 */
8453#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
8454#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
8455#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
8456/* DISCON_HIGH_SNVS
8457 * 0b0..Turn on the switch
8458 * 0b1..Turn off the switch
8459 */
8460#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
8461#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
8462#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
8463/* OSC_I
8464 * 0b00..Nominal
8465 * 0b01..Decrease current by 12.5%
8466 * 0b10..Decrease current by 25.0%
8467 * 0b11..Decrease current by 37.5%
8468 */
8469#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
8470#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
8471#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
8472#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
8473#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
8474#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
8475#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
8476#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
8477#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
8478/* CLKGATE_CTRL
8479 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
8480 * 0b1..Prevent the logic from ever gating off the clock.
8481 */
8482#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
8483#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
8484#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
8485/* CLKGATE_DELAY
8486 * 0b000..0.5ms
8487 * 0b001..1.0ms
8488 * 0b010..2.0ms
8489 * 0b011..3.0ms
8490 * 0b100..4.0ms
8491 * 0b101..5.0ms
8492 * 0b110..6.0ms
8493 * 0b111..7.0ms
8494 */
8495#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
8496#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
8497#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
8498/* RTC_XTAL_SOURCE
8499 * 0b0..Internal ring oscillator
8500 * 0b1..RTC_XTAL
8501 */
8502#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
8503#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
8504#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
8505#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
8506/* @} */
8507
8508/* @name MISC1 - Miscellaneous Register 1 */
8509/* @{ */
8510#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
8511#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
8512/* LVDS1_CLK_SEL
8513 * 0b00000..Arm PLL
8514 * 0b00001..System PLL
8515 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
8516 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
8517 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
8518 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
8519 * 0b00110..Audio PLL
8520 * 0b00111..Video PLL
8521 * 0b01001..ethernet ref clock (ENET_PLL)
8522 * 0b01100..USB1 PLL clock
8523 * 0b01101..USB2 PLL clock
8524 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
8525 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
8526 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
8527 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
8528 * 0b10010..xtal (24M)
8529 */
8530#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
8531#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
8532#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
8533#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
8534#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
8535#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
8536#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
8537#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
8538#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
8539#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
8540#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
8541#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
8542#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
8543#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
8544#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
8545#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
8546#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
8547#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
8548#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
8549#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
8550#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
8551#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
8552#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
8553#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
8554#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
8555#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
8556#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
8557#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
8558/* @} */
8559
8560/* @name MISC1_SET - Miscellaneous Register 1 */
8561/* @{ */
8562#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
8563#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
8564/* LVDS1_CLK_SEL
8565 * 0b00000..Arm PLL
8566 * 0b00001..System PLL
8567 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
8568 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
8569 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
8570 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
8571 * 0b00110..Audio PLL
8572 * 0b00111..Video PLL
8573 * 0b01001..ethernet ref clock (ENET_PLL)
8574 * 0b01100..USB1 PLL clock
8575 * 0b01101..USB2 PLL clock
8576 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
8577 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
8578 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
8579 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
8580 * 0b10010..xtal (24M)
8581 */
8582#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
8583#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
8584#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
8585#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
8586#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
8587#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
8588#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
8589#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
8590#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
8591#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
8592#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
8593#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
8594#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
8595#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
8596#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
8597#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
8598#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
8599#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
8600#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
8601#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
8602#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
8603#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
8604#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
8605#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
8606#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
8607#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
8608#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
8609#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
8610/* @} */
8611
8612/* @name MISC1_CLR - Miscellaneous Register 1 */
8613/* @{ */
8614#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
8615#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
8616/* LVDS1_CLK_SEL
8617 * 0b00000..Arm PLL
8618 * 0b00001..System PLL
8619 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
8620 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
8621 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
8622 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
8623 * 0b00110..Audio PLL
8624 * 0b00111..Video PLL
8625 * 0b01001..ethernet ref clock (ENET_PLL)
8626 * 0b01100..USB1 PLL clock
8627 * 0b01101..USB2 PLL clock
8628 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
8629 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
8630 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
8631 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
8632 * 0b10010..xtal (24M)
8633 */
8634#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
8635#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
8636#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
8637#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
8638#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
8639#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
8640#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
8641#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
8642#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
8643#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
8644#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
8645#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
8646#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
8647#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
8648#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
8649#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
8650#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
8651#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
8652#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
8653#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
8654#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
8655#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
8656#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
8657#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
8658#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
8659#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
8660#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
8661#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
8662/* @} */
8663
8664/* @name MISC1_TOG - Miscellaneous Register 1 */
8665/* @{ */
8666#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
8667#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
8668/* LVDS1_CLK_SEL
8669 * 0b00000..Arm PLL
8670 * 0b00001..System PLL
8671 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
8672 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
8673 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
8674 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
8675 * 0b00110..Audio PLL
8676 * 0b00111..Video PLL
8677 * 0b01001..ethernet ref clock (ENET_PLL)
8678 * 0b01100..USB1 PLL clock
8679 * 0b01101..USB2 PLL clock
8680 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
8681 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
8682 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
8683 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
8684 * 0b10010..xtal (24M)
8685 */
8686#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
8687#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
8688#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
8689#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
8690#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
8691#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
8692#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
8693#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
8694#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
8695#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
8696#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
8697#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
8698#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
8699#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
8700#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
8701#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
8702#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
8703#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
8704#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
8705#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
8706#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
8707#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
8708#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
8709#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
8710#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
8711#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
8712#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
8713#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
8714/* @} */
8715
8716/* @name MISC2 - Miscellaneous Register 2 */
8717/* @{ */
8718#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
8719#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
8720/* REG0_BO_OFFSET
8721 * 0b100..Brownout offset = 0.100V
8722 * 0b111..Brownout offset = 0.175V
8723 */
8724#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
8725#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
8726#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
8727/* REG0_BO_STATUS
8728 * 0b1..Brownout, supply is below target minus brownout offset.
8729 */
8730#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
8731#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
8732#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
8733#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
8734#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
8735#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
8736#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
8737#define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U)
8738#define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U)
8739/* PLL3_DISABLE
8740 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
8741 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
8742 */
8743#define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)
8744#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
8745#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
8746/* REG1_BO_OFFSET
8747 * 0b100..Brownout offset = 0.100V
8748 * 0b111..Brownout offset = 0.175V
8749 */
8750#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
8751#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
8752#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
8753/* REG1_BO_STATUS
8754 * 0b1..Brownout, supply is below target minus brownout offset.
8755 */
8756#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
8757#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
8758#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
8759#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
8760#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
8761#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
8762#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
8763#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
8764#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
8765/* AUDIO_DIV_LSB
8766 * 0b0..divide by 1 (Default)
8767 * 0b1..divide by 2
8768 */
8769#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
8770#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
8771#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
8772/* REG2_BO_OFFSET
8773 * 0b100..Brownout offset = 0.100V
8774 * 0b111..Brownout offset = 0.175V
8775 */
8776#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
8777#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
8778#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
8779#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
8780#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
8781#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
8782#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
8783#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
8784#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
8785#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
8786#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
8787#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
8788/* AUDIO_DIV_MSB
8789 * 0b0..divide by 1 (Default)
8790 * 0b1..divide by 2
8791 */
8792#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
8793#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
8794#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
8795/* REG0_STEP_TIME
8796 * 0b00..64
8797 * 0b01..128
8798 * 0b10..256
8799 * 0b11..512
8800 */
8801#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
8802#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
8803#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
8804/* REG1_STEP_TIME
8805 * 0b00..64
8806 * 0b01..128
8807 * 0b10..256
8808 * 0b11..512
8809 */
8810#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
8811#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
8812#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
8813/* REG2_STEP_TIME
8814 * 0b00..64
8815 * 0b01..128
8816 * 0b10..256
8817 * 0b11..512
8818 */
8819#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
8820#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
8821#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
8822/* VIDEO_DIV
8823 * 0b00..divide by 1 (Default)
8824 * 0b01..divide by 2
8825 * 0b10..divide by 1
8826 * 0b11..divide by 4
8827 */
8828#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
8829/* @} */
8830
8831/* @name MISC2_SET - Miscellaneous Register 2 */
8832/* @{ */
8833#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
8834#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
8835/* REG0_BO_OFFSET
8836 * 0b100..Brownout offset = 0.100V
8837 * 0b111..Brownout offset = 0.175V
8838 */
8839#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
8840#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
8841#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
8842/* REG0_BO_STATUS
8843 * 0b1..Brownout, supply is below target minus brownout offset.
8844 */
8845#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
8846#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
8847#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
8848#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
8849#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
8850#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
8851#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
8852#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)
8853#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)
8854/* PLL3_DISABLE
8855 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
8856 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
8857 */
8858#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)
8859#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
8860#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
8861/* REG1_BO_OFFSET
8862 * 0b100..Brownout offset = 0.100V
8863 * 0b111..Brownout offset = 0.175V
8864 */
8865#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
8866#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
8867#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
8868/* REG1_BO_STATUS
8869 * 0b1..Brownout, supply is below target minus brownout offset.
8870 */
8871#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
8872#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
8873#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
8874#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
8875#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
8876#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
8877#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
8878#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
8879#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
8880/* AUDIO_DIV_LSB
8881 * 0b0..divide by 1 (Default)
8882 * 0b1..divide by 2
8883 */
8884#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
8885#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
8886#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
8887/* REG2_BO_OFFSET
8888 * 0b100..Brownout offset = 0.100V
8889 * 0b111..Brownout offset = 0.175V
8890 */
8891#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
8892#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
8893#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
8894#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
8895#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
8896#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
8897#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
8898#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
8899#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
8900#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
8901#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
8902#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
8903/* AUDIO_DIV_MSB
8904 * 0b0..divide by 1 (Default)
8905 * 0b1..divide by 2
8906 */
8907#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
8908#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
8909#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
8910/* REG0_STEP_TIME
8911 * 0b00..64
8912 * 0b01..128
8913 * 0b10..256
8914 * 0b11..512
8915 */
8916#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
8917#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
8918#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
8919/* REG1_STEP_TIME
8920 * 0b00..64
8921 * 0b01..128
8922 * 0b10..256
8923 * 0b11..512
8924 */
8925#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
8926#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
8927#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
8928/* REG2_STEP_TIME
8929 * 0b00..64
8930 * 0b01..128
8931 * 0b10..256
8932 * 0b11..512
8933 */
8934#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
8935#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
8936#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
8937/* VIDEO_DIV
8938 * 0b00..divide by 1 (Default)
8939 * 0b01..divide by 2
8940 * 0b10..divide by 1
8941 * 0b11..divide by 4
8942 */
8943#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
8944/* @} */
8945
8946/* @name MISC2_CLR - Miscellaneous Register 2 */
8947/* @{ */
8948#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
8949#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
8950/* REG0_BO_OFFSET
8951 * 0b100..Brownout offset = 0.100V
8952 * 0b111..Brownout offset = 0.175V
8953 */
8954#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
8955#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
8956#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
8957/* REG0_BO_STATUS
8958 * 0b1..Brownout, supply is below target minus brownout offset.
8959 */
8960#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
8961#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
8962#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
8963#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
8964#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
8965#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
8966#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
8967#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)
8968#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)
8969/* PLL3_DISABLE
8970 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
8971 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
8972 */
8973#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)
8974#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
8975#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
8976/* REG1_BO_OFFSET
8977 * 0b100..Brownout offset = 0.100V
8978 * 0b111..Brownout offset = 0.175V
8979 */
8980#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
8981#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
8982#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
8983/* REG1_BO_STATUS
8984 * 0b1..Brownout, supply is below target minus brownout offset.
8985 */
8986#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
8987#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
8988#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
8989#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
8990#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
8991#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
8992#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
8993#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
8994#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
8995/* AUDIO_DIV_LSB
8996 * 0b0..divide by 1 (Default)
8997 * 0b1..divide by 2
8998 */
8999#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
9000#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
9001#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
9002/* REG2_BO_OFFSET
9003 * 0b100..Brownout offset = 0.100V
9004 * 0b111..Brownout offset = 0.175V
9005 */
9006#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
9007#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
9008#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
9009#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
9010#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
9011#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
9012#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
9013#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
9014#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
9015#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
9016#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
9017#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
9018/* AUDIO_DIV_MSB
9019 * 0b0..divide by 1 (Default)
9020 * 0b1..divide by 2
9021 */
9022#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
9023#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
9024#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
9025/* REG0_STEP_TIME
9026 * 0b00..64
9027 * 0b01..128
9028 * 0b10..256
9029 * 0b11..512
9030 */
9031#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
9032#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
9033#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
9034/* REG1_STEP_TIME
9035 * 0b00..64
9036 * 0b01..128
9037 * 0b10..256
9038 * 0b11..512
9039 */
9040#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
9041#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
9042#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
9043/* REG2_STEP_TIME
9044 * 0b00..64
9045 * 0b01..128
9046 * 0b10..256
9047 * 0b11..512
9048 */
9049#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
9050#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
9051#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
9052/* VIDEO_DIV
9053 * 0b00..divide by 1 (Default)
9054 * 0b01..divide by 2
9055 * 0b10..divide by 1
9056 * 0b11..divide by 4
9057 */
9058#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
9059/* @} */
9060
9061/* @name MISC2_TOG - Miscellaneous Register 2 */
9062/* @{ */
9063#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
9064#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
9065/* REG0_BO_OFFSET
9066 * 0b100..Brownout offset = 0.100V
9067 * 0b111..Brownout offset = 0.175V
9068 */
9069#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
9070#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
9071#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
9072/* REG0_BO_STATUS
9073 * 0b1..Brownout, supply is below target minus brownout offset.
9074 */
9075#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
9076#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
9077#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
9078#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
9079#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
9080#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
9081#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
9082#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)
9083#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)
9084/* PLL3_DISABLE
9085 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9086 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
9087 */
9088#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)
9089#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
9090#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
9091/* REG1_BO_OFFSET
9092 * 0b100..Brownout offset = 0.100V
9093 * 0b111..Brownout offset = 0.175V
9094 */
9095#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
9096#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
9097#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
9098/* REG1_BO_STATUS
9099 * 0b1..Brownout, supply is below target minus brownout offset.
9100 */
9101#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
9102#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
9103#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
9104#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
9105#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
9106#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
9107#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
9108#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
9109#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
9110/* AUDIO_DIV_LSB
9111 * 0b0..divide by 1 (Default)
9112 * 0b1..divide by 2
9113 */
9114#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
9115#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
9116#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
9117/* REG2_BO_OFFSET
9118 * 0b100..Brownout offset = 0.100V
9119 * 0b111..Brownout offset = 0.175V
9120 */
9121#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
9122#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
9123#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
9124#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
9125#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
9126#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
9127#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
9128#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
9129#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
9130#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
9131#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
9132#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
9133/* AUDIO_DIV_MSB
9134 * 0b0..divide by 1 (Default)
9135 * 0b1..divide by 2
9136 */
9137#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
9138#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
9139#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
9140/* REG0_STEP_TIME
9141 * 0b00..64
9142 * 0b01..128
9143 * 0b10..256
9144 * 0b11..512
9145 */
9146#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
9147#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
9148#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
9149/* REG1_STEP_TIME
9150 * 0b00..64
9151 * 0b01..128
9152 * 0b10..256
9153 * 0b11..512
9154 */
9155#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
9156#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
9157#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
9158/* REG2_STEP_TIME
9159 * 0b00..64
9160 * 0b01..128
9161 * 0b10..256
9162 * 0b11..512
9163 */
9164#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
9165#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
9166#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
9167/* VIDEO_DIV
9168 * 0b00..divide by 1 (Default)
9169 * 0b01..divide by 2
9170 * 0b10..divide by 1
9171 * 0b11..divide by 4
9172 */
9173#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
9174/* @} */
9175
9176
9177/*
9178 * @}
9179 */ /* end of group CCM_ANALOG_Register_Masks */
9180
9181
9182/* CCM_ANALOG - Peripheral instance base addresses */
9183/* Peripheral CCM_ANALOG base address */
9184#define CCM_ANALOG_BASE (0x400D8000u)
9185/* Peripheral CCM_ANALOG base pointer */
9186#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
9187/* Array initializer of CCM_ANALOG peripheral base addresses */
9188#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
9189/* Array initializer of CCM_ANALOG peripheral base pointers */
9190#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
9191
9192/*
9193 * @}
9194 */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
9195
9196
9197/* ----------------------------------------------------------------------------
9198 -- CMP Peripheral Access Layer
9199 ---------------------------------------------------------------------------- */
9200
9201/*
9202 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
9203 * @{
9204 */
9205
9206/* CMP - Register Layout Typedef */
9207typedef struct {
9208 __IO uint8_t CR0;
9209 __IO uint8_t CR1;
9210 __IO uint8_t FPR;
9211 __IO uint8_t SCR;
9212 __IO uint8_t DACCR;
9213 __IO uint8_t MUXCR;
9214} CMP_Type;
9215
9216/* ----------------------------------------------------------------------------
9217 -- CMP Register Masks
9218 ---------------------------------------------------------------------------- */
9219
9220/*
9221 * @addtogroup CMP_Register_Masks CMP Register Masks
9222 * @{
9223 */
9224
9225/* @name CR0 - CMP Control Register 0 */
9226/* @{ */
9227#define CMP_CR0_HYSTCTR_MASK (0x3U)
9228#define CMP_CR0_HYSTCTR_SHIFT (0U)
9229/* HYSTCTR - Comparator hard block hysteresis control
9230 * 0b00..Level 0
9231 * 0b01..Level 1
9232 * 0b10..Level 2
9233 * 0b11..Level 3
9234 */
9235#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
9236#define CMP_CR0_FILTER_CNT_MASK (0x70U)
9237#define CMP_CR0_FILTER_CNT_SHIFT (4U)
9238/* FILTER_CNT - Filter Sample Count
9239 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
9240 * 0b001..One sample must agree. The comparator output is simply sampled.
9241 * 0b010..2 consecutive samples must agree.
9242 * 0b011..3 consecutive samples must agree.
9243 * 0b100..4 consecutive samples must agree.
9244 * 0b101..5 consecutive samples must agree.
9245 * 0b110..6 consecutive samples must agree.
9246 * 0b111..7 consecutive samples must agree.
9247 */
9248#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
9249/* @} */
9250
9251/* @name CR1 - CMP Control Register 1 */
9252/* @{ */
9253#define CMP_CR1_EN_MASK (0x1U)
9254#define CMP_CR1_EN_SHIFT (0U)
9255/* EN - Comparator Module Enable
9256 * 0b0..Analog Comparator is disabled.
9257 * 0b1..Analog Comparator is enabled.
9258 */
9259#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
9260#define CMP_CR1_OPE_MASK (0x2U)
9261#define CMP_CR1_OPE_SHIFT (1U)
9262/* OPE - Comparator Output Pin Enable
9263 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
9264 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the
9265 * associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this
9266 * bit has no effect.
9267 */
9268#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
9269#define CMP_CR1_COS_MASK (0x4U)
9270#define CMP_CR1_COS_SHIFT (2U)
9271/* COS - Comparator Output Select
9272 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
9273 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
9274 */
9275#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
9276#define CMP_CR1_INV_MASK (0x8U)
9277#define CMP_CR1_INV_SHIFT (3U)
9278/* INV - Comparator INVERT
9279 * 0b0..Does not invert the comparator output.
9280 * 0b1..Inverts the comparator output.
9281 */
9282#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
9283#define CMP_CR1_PMODE_MASK (0x10U)
9284#define CMP_CR1_PMODE_SHIFT (4U)
9285/* PMODE - Power Mode Select
9286 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
9287 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
9288 */
9289#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
9290#define CMP_CR1_WE_MASK (0x40U)
9291#define CMP_CR1_WE_SHIFT (6U)
9292/* WE - Windowing Enable
9293 * 0b0..Windowing mode is not selected.
9294 * 0b1..Windowing mode is selected.
9295 */
9296#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
9297#define CMP_CR1_SE_MASK (0x80U)
9298#define CMP_CR1_SE_SHIFT (7U)
9299/* SE - Sample Enable
9300 * 0b0..Sampling mode is not selected.
9301 * 0b1..Sampling mode is selected.
9302 */
9303#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
9304/* @} */
9305
9306/* @name FPR - CMP Filter Period Register */
9307/* @{ */
9308#define CMP_FPR_FILT_PER_MASK (0xFFU)
9309#define CMP_FPR_FILT_PER_SHIFT (0U)
9310#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
9311/* @} */
9312
9313/* @name SCR - CMP Status and Control Register */
9314/* @{ */
9315#define CMP_SCR_COUT_MASK (0x1U)
9316#define CMP_SCR_COUT_SHIFT (0U)
9317#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
9318#define CMP_SCR_CFF_MASK (0x2U)
9319#define CMP_SCR_CFF_SHIFT (1U)
9320/* CFF - Analog Comparator Flag Falling
9321 * 0b0..Falling-edge on COUT has not been detected.
9322 * 0b1..Falling-edge on COUT has occurred.
9323 */
9324#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
9325#define CMP_SCR_CFR_MASK (0x4U)
9326#define CMP_SCR_CFR_SHIFT (2U)
9327/* CFR - Analog Comparator Flag Rising
9328 * 0b0..Rising-edge on COUT has not been detected.
9329 * 0b1..Rising-edge on COUT has occurred.
9330 */
9331#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
9332#define CMP_SCR_IEF_MASK (0x8U)
9333#define CMP_SCR_IEF_SHIFT (3U)
9334/* IEF - Comparator Interrupt Enable Falling
9335 * 0b0..Interrupt is disabled.
9336 * 0b1..Interrupt is enabled.
9337 */
9338#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
9339#define CMP_SCR_IER_MASK (0x10U)
9340#define CMP_SCR_IER_SHIFT (4U)
9341/* IER - Comparator Interrupt Enable Rising
9342 * 0b0..Interrupt is disabled.
9343 * 0b1..Interrupt is enabled.
9344 */
9345#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
9346#define CMP_SCR_DMAEN_MASK (0x40U)
9347#define CMP_SCR_DMAEN_SHIFT (6U)
9348/* DMAEN - DMA Enable Control
9349 * 0b0..DMA is disabled.
9350 * 0b1..DMA is enabled.
9351 */
9352#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
9353/* @} */
9354
9355/* @name DACCR - DAC Control Register */
9356/* @{ */
9357#define CMP_DACCR_VOSEL_MASK (0x3FU)
9358#define CMP_DACCR_VOSEL_SHIFT (0U)
9359#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
9360#define CMP_DACCR_VRSEL_MASK (0x40U)
9361#define CMP_DACCR_VRSEL_SHIFT (6U)
9362/* VRSEL - Supply Voltage Reference Source Select
9363 * 0b0..Vin1 is selected as resistor ladder network supply reference.
9364 * 0b1..Vin2 is selected as resistor ladder network supply reference.
9365 */
9366#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
9367#define CMP_DACCR_DACEN_MASK (0x80U)
9368#define CMP_DACCR_DACEN_SHIFT (7U)
9369/* DACEN - DAC Enable
9370 * 0b0..DAC is disabled.
9371 * 0b1..DAC is enabled.
9372 */
9373#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
9374/* @} */
9375
9376/* @name MUXCR - MUX Control Register */
9377/* @{ */
9378#define CMP_MUXCR_MSEL_MASK (0x7U)
9379#define CMP_MUXCR_MSEL_SHIFT (0U)
9380/* MSEL - Minus Input Mux Control
9381 * 0b000..IN0
9382 * 0b001..IN1
9383 * 0b010..IN2
9384 * 0b011..IN3
9385 * 0b100..IN4
9386 * 0b101..IN5
9387 * 0b110..IN6
9388 * 0b111..IN7
9389 */
9390#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
9391#define CMP_MUXCR_PSEL_MASK (0x38U)
9392#define CMP_MUXCR_PSEL_SHIFT (3U)
9393/* PSEL - Plus Input Mux Control
9394 * 0b000..IN0
9395 * 0b001..IN1
9396 * 0b010..IN2
9397 * 0b011..IN3
9398 * 0b100..IN4
9399 * 0b101..IN5
9400 * 0b110..IN6
9401 * 0b111..IN7
9402 */
9403#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
9404/* @} */
9405
9406
9407/*
9408 * @}
9409 */ /* end of group CMP_Register_Masks */
9410
9411
9412/* CMP - Peripheral instance base addresses */
9413/* Peripheral CMP1 base address */
9414#define CMP1_BASE (0x40094000u)
9415/* Peripheral CMP1 base pointer */
9416#define CMP1 ((CMP_Type *)CMP1_BASE)
9417/* Peripheral CMP2 base address */
9418#define CMP2_BASE (0x40094008u)
9419/* Peripheral CMP2 base pointer */
9420#define CMP2 ((CMP_Type *)CMP2_BASE)
9421/* Peripheral CMP3 base address */
9422#define CMP3_BASE (0x40094010u)
9423/* Peripheral CMP3 base pointer */
9424#define CMP3 ((CMP_Type *)CMP3_BASE)
9425/* Peripheral CMP4 base address */
9426#define CMP4_BASE (0x40094018u)
9427/* Peripheral CMP4 base pointer */
9428#define CMP4 ((CMP_Type *)CMP4_BASE)
9429/* Array initializer of CMP peripheral base addresses */
9430#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
9431/* Array initializer of CMP peripheral base pointers */
9432#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
9433/* Interrupt vectors for the CMP peripheral type */
9434#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
9435
9436/*
9437 * @}
9438 */ /* end of group CMP_Peripheral_Access_Layer */
9439
9440
9441/* ----------------------------------------------------------------------------
9442 -- CSU Peripheral Access Layer
9443 ---------------------------------------------------------------------------- */
9444
9445/*
9446 * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer
9447 * @{
9448 */
9449
9450/* CSU - Register Layout Typedef */
9451typedef struct {
9452 __IO uint32_t CSL[32];
9453 uint8_t RESERVED_0[384];
9454 __IO uint32_t HP0;
9455 uint8_t RESERVED_1[20];
9456 __IO uint32_t SA;
9457 uint8_t RESERVED_2[316];
9458 __IO uint32_t HPCONTROL0;
9459} CSU_Type;
9460
9461/* ----------------------------------------------------------------------------
9462 -- CSU Register Masks
9463 ---------------------------------------------------------------------------- */
9464
9465/*
9466 * @addtogroup CSU_Register_Masks CSU Register Masks
9467 * @{
9468 */
9469
9470/* @name CSL - Config security level register */
9471/* @{ */
9472#define CSU_CSL_SUR_S2_MASK (0x1U)
9473#define CSU_CSL_SUR_S2_SHIFT (0U)
9474/* SUR_S2
9475 * 0b0..The secure user read access is disabled for the second slave.
9476 * 0b1..The secure user read access is enabled for the second slave.
9477 */
9478#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
9479#define CSU_CSL_SSR_S2_MASK (0x2U)
9480#define CSU_CSL_SSR_S2_SHIFT (1U)
9481/* SSR_S2
9482 * 0b0..The secure supervisor read access is disabled for the second slave.
9483 * 0b1..The secure supervisor read access is enabled for the second slave.
9484 */
9485#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
9486#define CSU_CSL_NUR_S2_MASK (0x4U)
9487#define CSU_CSL_NUR_S2_SHIFT (2U)
9488/* NUR_S2
9489 * 0b0..The non-secure user read access is disabled for the second slave.
9490 * 0b1..The non-secure user read access is enabled for the second slave.
9491 */
9492#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
9493#define CSU_CSL_NSR_S2_MASK (0x8U)
9494#define CSU_CSL_NSR_S2_SHIFT (3U)
9495/* NSR_S2
9496 * 0b0..The non-secure supervisor read access is disabled for the second slave.
9497 * 0b1..The non-secure supervisor read access is enabled for the second slave.
9498 */
9499#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
9500#define CSU_CSL_SUW_S2_MASK (0x10U)
9501#define CSU_CSL_SUW_S2_SHIFT (4U)
9502/* SUW_S2
9503 * 0b0..The secure user write access is disabled for the second slave.
9504 * 0b1..The secure user write access is enabled for the second slave.
9505 */
9506#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
9507#define CSU_CSL_SSW_S2_MASK (0x20U)
9508#define CSU_CSL_SSW_S2_SHIFT (5U)
9509/* SSW_S2
9510 * 0b0..The secure supervisor write access is disabled for the second slave.
9511 * 0b1..The secure supervisor write access is enabled for the second slave.
9512 */
9513#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
9514#define CSU_CSL_NUW_S2_MASK (0x40U)
9515#define CSU_CSL_NUW_S2_SHIFT (6U)
9516/* NUW_S2
9517 * 0b0..The non-secure user write access is disabled for the second slave.
9518 * 0b1..The non-secure user write access is enabled for the second slave.
9519 */
9520#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
9521#define CSU_CSL_NSW_S2_MASK (0x80U)
9522#define CSU_CSL_NSW_S2_SHIFT (7U)
9523/* NSW_S2
9524 * 0b0..The non-secure supervisor write access is disabled for the second slave.
9525 * 0b1..The non-secure supervisor write access is enabled for the second slave.
9526 */
9527#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
9528#define CSU_CSL_LOCK_S2_MASK (0x100U)
9529#define CSU_CSL_LOCK_S2_SHIFT (8U)
9530/* LOCK_S2
9531 * 0b0..Not locked. Bits 7-0 can be written by the software.
9532 * 0b1..Bits 7-0 are locked and cannot be written by the software
9533 */
9534#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
9535#define CSU_CSL_SUR_S1_MASK (0x10000U)
9536#define CSU_CSL_SUR_S1_SHIFT (16U)
9537/* SUR_S1
9538 * 0b0..The secure user read access is disabled for the first slave.
9539 * 0b1..The secure user read access is enabled for the first slave.
9540 */
9541#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
9542#define CSU_CSL_SSR_S1_MASK (0x20000U)
9543#define CSU_CSL_SSR_S1_SHIFT (17U)
9544/* SSR_S1
9545 * 0b0..The secure supervisor read access is disabled for the first slave.
9546 * 0b1..The secure supervisor read access is enabled for the first slave.
9547 */
9548#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
9549#define CSU_CSL_NUR_S1_MASK (0x40000U)
9550#define CSU_CSL_NUR_S1_SHIFT (18U)
9551/* NUR_S1
9552 * 0b0..The non-secure user read access is disabled for the first slave.
9553 * 0b1..The non-secure user read access is enabled for the first slave.
9554 */
9555#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
9556#define CSU_CSL_NSR_S1_MASK (0x80000U)
9557#define CSU_CSL_NSR_S1_SHIFT (19U)
9558/* NSR_S1
9559 * 0b0..The non-secure supervisor read access is disabled for the first slave.
9560 * 0b1..The non-secure supervisor read access is enabled for the first slave.
9561 */
9562#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
9563#define CSU_CSL_SUW_S1_MASK (0x100000U)
9564#define CSU_CSL_SUW_S1_SHIFT (20U)
9565/* SUW_S1
9566 * 0b0..The secure user write access is disabled for the first slave.
9567 * 0b1..The secure user write access is enabled for the first slave.
9568 */
9569#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
9570#define CSU_CSL_SSW_S1_MASK (0x200000U)
9571#define CSU_CSL_SSW_S1_SHIFT (21U)
9572/* SSW_S1
9573 * 0b0..The secure supervisor write access is disabled for the first slave.
9574 * 0b1..The secure supervisor write access is enabled for the first slave.
9575 */
9576#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
9577#define CSU_CSL_NUW_S1_MASK (0x400000U)
9578#define CSU_CSL_NUW_S1_SHIFT (22U)
9579/* NUW_S1
9580 * 0b0..The non-secure user write access is disabled for the first slave.
9581 * 0b1..The non-secure user write access is enabled for the first slave.
9582 */
9583#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
9584#define CSU_CSL_NSW_S1_MASK (0x800000U)
9585#define CSU_CSL_NSW_S1_SHIFT (23U)
9586/* NSW_S1
9587 * 0b0..The non-secure supervisor write access is disabled for the first slave.
9588 * 0b1..The non-secure supervisor write access is enabled for the first slave
9589 */
9590#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
9591#define CSU_CSL_LOCK_S1_MASK (0x1000000U)
9592#define CSU_CSL_LOCK_S1_SHIFT (24U)
9593/* LOCK_S1
9594 * 0b0..Not locked. The bits 16-23 can be written by the software.
9595 * 0b1..The bits 16-23 are locked and can't be written by the software.
9596 */
9597#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
9598/* @} */
9599
9600/* The count of CSU_CSL */
9601#define CSU_CSL_COUNT (32U)
9602
9603/* @name HP0 - HP0 register */
9604/* @{ */
9605#define CSU_HP0_HP_DMA_MASK (0x4U)
9606#define CSU_HP0_HP_DMA_SHIFT (2U)
9607/* HP_DMA
9608 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9609 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9610 */
9611#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
9612#define CSU_HP0_L_DMA_MASK (0x8U)
9613#define CSU_HP0_L_DMA_SHIFT (3U)
9614/* L_DMA
9615 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9616 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9617 */
9618#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
9619#define CSU_HP0_HP_LCDIF_MASK (0x10U)
9620#define CSU_HP0_HP_LCDIF_SHIFT (4U)
9621/* HP_LCDIF
9622 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9623 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9624 */
9625#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
9626#define CSU_HP0_L_LCDIF_MASK (0x20U)
9627#define CSU_HP0_L_LCDIF_SHIFT (5U)
9628/* L_LCDIF
9629 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9630 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9631 */
9632#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
9633#define CSU_HP0_HP_CSI_MASK (0x40U)
9634#define CSU_HP0_HP_CSI_SHIFT (6U)
9635/* HP_CSI
9636 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9637 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9638 */
9639#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
9640#define CSU_HP0_L_CSI_MASK (0x80U)
9641#define CSU_HP0_L_CSI_SHIFT (7U)
9642/* L_CSI
9643 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9644 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9645 */
9646#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
9647#define CSU_HP0_HP_PXP_MASK (0x100U)
9648#define CSU_HP0_HP_PXP_SHIFT (8U)
9649/* HP_PXP
9650 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9651 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9652 */
9653#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
9654#define CSU_HP0_L_PXP_MASK (0x200U)
9655#define CSU_HP0_L_PXP_SHIFT (9U)
9656/* L_PXP
9657 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9658 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9659 */
9660#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
9661#define CSU_HP0_HP_DCP_MASK (0x400U)
9662#define CSU_HP0_HP_DCP_SHIFT (10U)
9663/* HP_DCP
9664 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9665 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9666 */
9667#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
9668#define CSU_HP0_L_DCP_MASK (0x800U)
9669#define CSU_HP0_L_DCP_SHIFT (11U)
9670/* L_DCP
9671 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9672 * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software.
9673 */
9674#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
9675#define CSU_HP0_HP_ENET_MASK (0x4000U)
9676#define CSU_HP0_HP_ENET_SHIFT (14U)
9677/* HP_ENET
9678 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9679 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9680 */
9681#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
9682#define CSU_HP0_L_ENET_MASK (0x8000U)
9683#define CSU_HP0_L_ENET_SHIFT (15U)
9684/* L_ENET
9685 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9686 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9687 */
9688#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
9689#define CSU_HP0_HP_USDHC1_MASK (0x10000U)
9690#define CSU_HP0_HP_USDHC1_SHIFT (16U)
9691/* HP_USDHC1
9692 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9693 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9694 */
9695#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
9696#define CSU_HP0_L_USDHC1_MASK (0x20000U)
9697#define CSU_HP0_L_USDHC1_SHIFT (17U)
9698/* L_USDHC1
9699 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9700 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9701 */
9702#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
9703#define CSU_HP0_HP_USDHC2_MASK (0x40000U)
9704#define CSU_HP0_HP_USDHC2_SHIFT (18U)
9705/* HP_USDHC2
9706 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9707 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9708 */
9709#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
9710#define CSU_HP0_L_USDHC2_MASK (0x80000U)
9711#define CSU_HP0_L_USDHC2_SHIFT (19U)
9712/* L_USDHC2
9713 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9714 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9715 */
9716#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
9717#define CSU_HP0_HP_TPSMP_MASK (0x100000U)
9718#define CSU_HP0_HP_TPSMP_SHIFT (20U)
9719/* HP_TPSMP
9720 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9721 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9722 */
9723#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
9724#define CSU_HP0_L_TPSMP_MASK (0x200000U)
9725#define CSU_HP0_L_TPSMP_SHIFT (21U)
9726/* L_TPSMP
9727 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9728 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9729 */
9730#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
9731#define CSU_HP0_HP_USB_MASK (0x400000U)
9732#define CSU_HP0_HP_USB_SHIFT (22U)
9733/* HP_USB
9734 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
9735 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
9736 */
9737#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
9738#define CSU_HP0_L_USB_MASK (0x800000U)
9739#define CSU_HP0_L_USB_SHIFT (23U)
9740/* L_USB
9741 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9742 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9743 */
9744#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
9745/* @} */
9746
9747/* @name SA - Secure access register */
9748/* @{ */
9749#define CSU_SA_NSA_DMA_MASK (0x4U)
9750#define CSU_SA_NSA_DMA_SHIFT (2U)
9751/* NSA_DMA - Non-secure access policy indicator bit
9752 * 0b0..Secure access for the corresponding type-1 master
9753 * 0b1..Non-secure access for the corresponding type-1 master
9754 */
9755#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
9756#define CSU_SA_L_DMA_MASK (0x8U)
9757#define CSU_SA_L_DMA_SHIFT (3U)
9758/* L_DMA
9759 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9760 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9761 */
9762#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
9763#define CSU_SA_NSA_LCDIF_MASK (0x10U)
9764#define CSU_SA_NSA_LCDIF_SHIFT (4U)
9765/* NSA_LCDIF - Non-secure access policy indicator bit
9766 * 0b0..Secure access for the corresponding type-1 master
9767 * 0b1..Non-secure access for the corresponding type-1 master
9768 */
9769#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
9770#define CSU_SA_L_LCDIF_MASK (0x20U)
9771#define CSU_SA_L_LCDIF_SHIFT (5U)
9772/* L_LCDIF
9773 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9774 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9775 */
9776#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
9777#define CSU_SA_NSA_CSI_MASK (0x40U)
9778#define CSU_SA_NSA_CSI_SHIFT (6U)
9779/* NSA_CSI - Non-secure access policy indicator bit
9780 * 0b0..Secure access for the corresponding type-1 master
9781 * 0b1..Non-secure access for the corresponding type-1 master
9782 */
9783#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
9784#define CSU_SA_L_CSI_MASK (0x80U)
9785#define CSU_SA_L_CSI_SHIFT (7U)
9786/* L_CSI
9787 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9788 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9789 */
9790#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
9791#define CSU_SA_NSA_PXP_MASK (0x100U)
9792#define CSU_SA_NSA_PXP_SHIFT (8U)
9793/* NSA_PXP - Non-Secure Access Policy indicator bit
9794 * 0b0..Secure access for the corresponding type-1 master
9795 * 0b1..Non-secure access for the corresponding type-1 master
9796 */
9797#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
9798#define CSU_SA_L_PXP_MASK (0x200U)
9799#define CSU_SA_L_PXP_SHIFT (9U)
9800/* L_PXP
9801 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9802 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9803 */
9804#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
9805#define CSU_SA_NSA_DCP_MASK (0x400U)
9806#define CSU_SA_NSA_DCP_SHIFT (10U)
9807/* NSA_DCP - Non-secure access policy indicator bit
9808 * 0b0..Secure access for the corresponding type-1 master
9809 * 0b1..Non-secure access for the corresponding type-1 master
9810 */
9811#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
9812#define CSU_SA_L_DCP_MASK (0x800U)
9813#define CSU_SA_L_DCP_SHIFT (11U)
9814/* L_DCP
9815 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9816 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9817 */
9818#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
9819#define CSU_SA_NSA_ENET_MASK (0x4000U)
9820#define CSU_SA_NSA_ENET_SHIFT (14U)
9821/* NSA_ENET - Non-secure access policy indicator bit
9822 * 0b0..Secure access for the corresponding type-1 master
9823 * 0b1..Non-secure access for the corresponding type-1 master
9824 */
9825#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
9826#define CSU_SA_L_ENET_MASK (0x8000U)
9827#define CSU_SA_L_ENET_SHIFT (15U)
9828/* L_ENET
9829 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9830 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9831 */
9832#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
9833#define CSU_SA_NSA_USDHC1_MASK (0x10000U)
9834#define CSU_SA_NSA_USDHC1_SHIFT (16U)
9835/* NSA_USDHC1 - Non-secure access policy indicator bit
9836 * 0b0..Secure access for the corresponding type-1 master
9837 * 0b1..Non-secure access for the corresponding type-1 master
9838 */
9839#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
9840#define CSU_SA_L_USDHC1_MASK (0x20000U)
9841#define CSU_SA_L_USDHC1_SHIFT (17U)
9842/* L_USDHC1
9843 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9844 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9845 */
9846#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
9847#define CSU_SA_NSA_USDHC2_MASK (0x40000U)
9848#define CSU_SA_NSA_USDHC2_SHIFT (18U)
9849/* NSA_USDHC2 - Non-secure access policy indicator bit
9850 * 0b0..Secure access for the corresponding type-1 master
9851 * 0b1..Non-secure access for the corresponding type-1 master
9852 */
9853#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
9854#define CSU_SA_L_USDHC2_MASK (0x80000U)
9855#define CSU_SA_L_USDHC2_SHIFT (19U)
9856/* L_USDHC2
9857 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9858 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9859 */
9860#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
9861#define CSU_SA_NSA_TPSMP_MASK (0x100000U)
9862#define CSU_SA_NSA_TPSMP_SHIFT (20U)
9863/* NSA_TPSMP - Non-secure access policy indicator bit
9864 * 0b0..Secure access for the corresponding type-1 master
9865 * 0b1..Non-secure access for the corresponding type-1 master
9866 */
9867#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
9868#define CSU_SA_L_TPSMP_MASK (0x200000U)
9869#define CSU_SA_L_TPSMP_SHIFT (21U)
9870/* L_TPSMP
9871 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9872 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9873 */
9874#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
9875#define CSU_SA_NSA_USB_MASK (0x400000U)
9876#define CSU_SA_NSA_USB_SHIFT (22U)
9877/* NSA_USB - Non-secure access policy indicator bit
9878 * 0b0..Secure access for the corresponding type-1 master
9879 * 0b1..Non-secure access for the corresponding type-1 master
9880 */
9881#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
9882#define CSU_SA_L_USB_MASK (0x800000U)
9883#define CSU_SA_L_USB_SHIFT (23U)
9884/* L_USB
9885 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9886 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9887 */
9888#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
9889/* @} */
9890
9891/* @name HPCONTROL0 - HPCONTROL0 register */
9892/* @{ */
9893#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
9894#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
9895/* HPC_DMA
9896 * 0b0..User mode for the corresponding master
9897 * 0b1..Supervisor mode for the corresponding master
9898 */
9899#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
9900#define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
9901#define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
9902/* L_DMA
9903 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9904 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9905 */
9906#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
9907#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
9908#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
9909/* HPC_LCDIF
9910 * 0b0..User mode for the corresponding master
9911 * 0b1..Supervisor mode for the corresponding master
9912 */
9913#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
9914#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
9915#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
9916/* L_LCDIF
9917 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9918 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9919 */
9920#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
9921#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
9922#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
9923/* HPC_CSI
9924 * 0b0..User mode for the corresponding master
9925 * 0b1..Supervisor mode for the corresponding master
9926 */
9927#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
9928#define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
9929#define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
9930/* L_CSI
9931 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9932 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9933 */
9934#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
9935#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
9936#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
9937/* HPC_PXP
9938 * 0b0..User mode for the corresponding master
9939 * 0b1..Supervisor mode for the corresponding master
9940 */
9941#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
9942#define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
9943#define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
9944/* L_PXP
9945 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9946 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9947 */
9948#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
9949#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
9950#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
9951/* HPC_DCP
9952 * 0b0..User mode for the corresponding master
9953 * 0b1..Supervisor mode for the corresponding master
9954 */
9955#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
9956#define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
9957#define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
9958/* L_DCP
9959 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9960 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9961 */
9962#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
9963#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
9964#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
9965/* HPC_ENET
9966 * 0b0..User mode for the corresponding master
9967 * 0b1..Supervisor mode for the corresponding master
9968 */
9969#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
9970#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
9971#define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
9972/* L_ENET
9973 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9974 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9975 */
9976#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
9977#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
9978#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
9979/* HPC_USDHC1
9980 * 0b0..User mode for the corresponding master
9981 * 0b1..Supervisor mode for the corresponding master
9982 */
9983#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
9984#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
9985#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
9986/* L_USDHC1
9987 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
9988 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
9989 */
9990#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
9991#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
9992#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
9993/* HPC_USDHC2
9994 * 0b0..User mode for the corresponding master
9995 * 0b1..Supervisor mode for the corresponding master
9996 */
9997#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
9998#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
9999#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
10000/* L_USDHC2
10001 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
10002 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
10003 */
10004#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
10005#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
10006#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
10007/* HPC_TPSMP
10008 * 0b0..User mode for the corresponding master
10009 * 0b1..Supervisor mode for the corresponding master
10010 */
10011#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
10012#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
10013#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
10014/* L_TPSMP
10015 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
10016 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
10017 */
10018#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
10019#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
10020#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
10021/* HPC_USB
10022 * 0b0..User mode for the corresponding master
10023 * 0b1..Supervisor mode for the corresponding master
10024 */
10025#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
10026#define CSU_HPCONTROL0_L_USB_MASK (0x800000U)
10027#define CSU_HPCONTROL0_L_USB_SHIFT (23U)
10028/* L_USB
10029 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
10030 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
10031 */
10032#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
10033/* @} */
10034
10035
10036/*
10037 * @}
10038 */ /* end of group CSU_Register_Masks */
10039
10040
10041/* CSU - Peripheral instance base addresses */
10042/* Peripheral CSU base address */
10043#define CSU_BASE (0x400DC000u)
10044/* Peripheral CSU base pointer */
10045#define CSU ((CSU_Type *)CSU_BASE)
10046/* Array initializer of CSU peripheral base addresses */
10047#define CSU_BASE_ADDRS { CSU_BASE }
10048/* Array initializer of CSU peripheral base pointers */
10049#define CSU_BASE_PTRS { CSU }
10050
10051/*
10052 * @}
10053 */ /* end of group CSU_Peripheral_Access_Layer */
10054
10055
10056/* ----------------------------------------------------------------------------
10057 -- DCDC Peripheral Access Layer
10058 ---------------------------------------------------------------------------- */
10059
10060/*
10061 * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
10062 * @{
10063 */
10064
10065/* DCDC - Register Layout Typedef */
10066typedef struct {
10067 __IO uint32_t REG0;
10068 __IO uint32_t REG1;
10069 __IO uint32_t REG2;
10070 __IO uint32_t REG3;
10071} DCDC_Type;
10072
10073/* ----------------------------------------------------------------------------
10074 -- DCDC Register Masks
10075 ---------------------------------------------------------------------------- */
10076
10077/*
10078 * @addtogroup DCDC_Register_Masks DCDC Register Masks
10079 * @{
10080 */
10081
10082/* @name REG0 - DCDC Register 0 */
10083/* @{ */
10084#define DCDC_REG0_PWD_ZCD_MASK (0x1U)
10085#define DCDC_REG0_PWD_ZCD_SHIFT (0U)
10086#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
10087#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
10088#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
10089#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
10090#define DCDC_REG0_SEL_CLK_MASK (0x4U)
10091#define DCDC_REG0_SEL_CLK_SHIFT (2U)
10092#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
10093#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
10094#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
10095#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
10096#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
10097#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
10098#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
10099#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
10100#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
10101#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
10102#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
10103#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
10104#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
10105#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
10106#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
10107#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
10108#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
10109#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
10110#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
10111#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)
10112#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)
10113#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)
10114#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
10115#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
10116#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
10117#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
10118#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
10119#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
10120#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
10121#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
10122#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
10123#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
10124#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
10125#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
10126#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
10127#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
10128#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
10129#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
10130#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
10131#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
10132#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
10133#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
10134#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
10135#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
10136#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
10137#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
10138#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
10139#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
10140#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
10141#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
10142#define DCDC_REG0_STS_DC_OK_SHIFT (31U)
10143#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
10144/* @} */
10145
10146/* @name REG1 - DCDC Register 1 */
10147/* @{ */
10148#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
10149#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
10150#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
10151#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
10152#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
10153#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
10154#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
10155#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
10156#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
10157#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
10158#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
10159#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
10160#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
10161#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
10162#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
10163#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
10164#define DCDC_REG1_VBG_TRIM_SHIFT (24U)
10165#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
10166/* @} */
10167
10168/* @name REG2 - DCDC Register 2 */
10169/* @{ */
10170#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
10171#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
10172#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
10173#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
10174#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
10175#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
10176#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
10177#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
10178#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
10179#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
10180#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
10181#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
10182#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
10183#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
10184#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
10185#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
10186#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
10187#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
10188#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
10189#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
10190#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
10191#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
10192#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
10193#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
10194/* @} */
10195
10196/* @name REG3 - DCDC Register 3 */
10197/* @{ */
10198#define DCDC_REG3_TRG_MASK (0x1FU)
10199#define DCDC_REG3_TRG_SHIFT (0U)
10200#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
10201#define DCDC_REG3_TARGET_LP_MASK (0x700U)
10202#define DCDC_REG3_TARGET_LP_SHIFT (8U)
10203#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
10204#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
10205#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
10206#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
10207#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
10208#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
10209#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
10210#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)
10211#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)
10212#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)
10213#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
10214#define DCDC_REG3_DISABLE_STEP_SHIFT (30U)
10215#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)
10216/* @} */
10217
10218
10219/*
10220 * @}
10221 */ /* end of group DCDC_Register_Masks */
10222
10223
10224/* DCDC - Peripheral instance base addresses */
10225/* Peripheral DCDC base address */
10226#define DCDC_BASE (0x40080000u)
10227/* Peripheral DCDC base pointer */
10228#define DCDC ((DCDC_Type *)DCDC_BASE)
10229/* Array initializer of DCDC peripheral base addresses */
10230#define DCDC_BASE_ADDRS { DCDC_BASE }
10231/* Array initializer of DCDC peripheral base pointers */
10232#define DCDC_BASE_PTRS { DCDC }
10233/* Interrupt vectors for the DCDC peripheral type */
10234#define DCDC_IRQS { DCDC_IRQn }
10235
10236/*
10237 * @}
10238 */ /* end of group DCDC_Peripheral_Access_Layer */
10239
10240
10241/* ----------------------------------------------------------------------------
10242 -- DCP Peripheral Access Layer
10243 ---------------------------------------------------------------------------- */
10244
10245/*
10246 * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer
10247 * @{
10248 */
10249
10250/* DCP - Register Layout Typedef */
10251typedef struct {
10252 __IO uint32_t CTRL;
10253 __IO uint32_t CTRL_SET;
10254 __IO uint32_t CTRL_CLR;
10255 __IO uint32_t CTRL_TOG;
10256 __IO uint32_t STAT;
10257 __IO uint32_t STAT_SET;
10258 __IO uint32_t STAT_CLR;
10259 __IO uint32_t STAT_TOG;
10260 __IO uint32_t CHANNELCTRL;
10261 __IO uint32_t CHANNELCTRL_SET;
10262 __IO uint32_t CHANNELCTRL_CLR;
10263 __IO uint32_t CHANNELCTRL_TOG;
10264 __IO uint32_t CAPABILITY0;
10265 uint8_t RESERVED_0[12];
10266 __I uint32_t CAPABILITY1;
10267 uint8_t RESERVED_1[12];
10268 __IO uint32_t CONTEXT;
10269 uint8_t RESERVED_2[12];
10270 __IO uint32_t KEY;
10271 uint8_t RESERVED_3[12];
10272 __IO uint32_t KEYDATA;
10273 uint8_t RESERVED_4[12];
10274 __I uint32_t PACKET0;
10275 uint8_t RESERVED_5[12];
10276 __I uint32_t PACKET1;
10277 uint8_t RESERVED_6[12];
10278 __I uint32_t PACKET2;
10279 uint8_t RESERVED_7[12];
10280 __I uint32_t PACKET3;
10281 uint8_t RESERVED_8[12];
10282 __I uint32_t PACKET4;
10283 uint8_t RESERVED_9[12];
10284 __I uint32_t PACKET5;
10285 uint8_t RESERVED_10[12];
10286 __I uint32_t PACKET6;
10287 uint8_t RESERVED_11[28];
10288 __IO uint32_t CH0CMDPTR;
10289 uint8_t RESERVED_12[12];
10290 __IO uint32_t CH0SEMA;
10291 uint8_t RESERVED_13[12];
10292 __IO uint32_t CH0STAT;
10293 __IO uint32_t CH0STAT_SET;
10294 __IO uint32_t CH0STAT_CLR;
10295 __IO uint32_t CH0STAT_TOG;
10296 __IO uint32_t CH0OPTS;
10297 __IO uint32_t CH0OPTS_SET;
10298 __IO uint32_t CH0OPTS_CLR;
10299 __IO uint32_t CH0OPTS_TOG;
10300 __IO uint32_t CH1CMDPTR;
10301 uint8_t RESERVED_14[12];
10302 __IO uint32_t CH1SEMA;
10303 uint8_t RESERVED_15[12];
10304 __IO uint32_t CH1STAT;
10305 __IO uint32_t CH1STAT_SET;
10306 __IO uint32_t CH1STAT_CLR;
10307 __IO uint32_t CH1STAT_TOG;
10308 __IO uint32_t CH1OPTS;
10309 __IO uint32_t CH1OPTS_SET;
10310 __IO uint32_t CH1OPTS_CLR;
10311 __IO uint32_t CH1OPTS_TOG;
10312 __IO uint32_t CH2CMDPTR;
10313 uint8_t RESERVED_16[12];
10314 __IO uint32_t CH2SEMA;
10315 uint8_t RESERVED_17[12];
10316 __IO uint32_t CH2STAT;
10317 __IO uint32_t CH2STAT_SET;
10318 __IO uint32_t CH2STAT_CLR;
10319 __IO uint32_t CH2STAT_TOG;
10320 __IO uint32_t CH2OPTS;
10321 __IO uint32_t CH2OPTS_SET;
10322 __IO uint32_t CH2OPTS_CLR;
10323 __IO uint32_t CH2OPTS_TOG;
10324 __IO uint32_t CH3CMDPTR;
10325 uint8_t RESERVED_18[12];
10326 __IO uint32_t CH3SEMA;
10327 uint8_t RESERVED_19[12];
10328 __IO uint32_t CH3STAT;
10329 __IO uint32_t CH3STAT_SET;
10330 __IO uint32_t CH3STAT_CLR;
10331 __IO uint32_t CH3STAT_TOG;
10332 __IO uint32_t CH3OPTS;
10333 __IO uint32_t CH3OPTS_SET;
10334 __IO uint32_t CH3OPTS_CLR;
10335 __IO uint32_t CH3OPTS_TOG;
10336 uint8_t RESERVED_20[512];
10337 __IO uint32_t DBGSELECT;
10338 uint8_t RESERVED_21[12];
10339 __I uint32_t DBGDATA;
10340 uint8_t RESERVED_22[12];
10341 __IO uint32_t PAGETABLE;
10342 uint8_t RESERVED_23[12];
10343 __I uint32_t VERSION;
10344} DCP_Type;
10345
10346/* ----------------------------------------------------------------------------
10347 -- DCP Register Masks
10348 ---------------------------------------------------------------------------- */
10349
10350/*
10351 * @addtogroup DCP_Register_Masks DCP Register Masks
10352 * @{
10353 */
10354
10355/* @name CTRL - DCP control register 0 */
10356/* @{ */
10357#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
10358#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
10359/* CHANNEL_INTERRUPT_ENABLE
10360 * 0b00000001..CH0
10361 * 0b00000010..CH1
10362 * 0b00000100..CH2
10363 * 0b00001000..CH3
10364 */
10365#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
10366#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
10367#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
10368#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
10369#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
10370#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
10371#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
10372#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
10373#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
10374#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
10375#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
10376#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
10377#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
10378#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
10379#define DCP_CTRL_PRESENT_SHA_SHIFT (28U)
10380/* PRESENT_SHA
10381 * 0b1..Present
10382 * 0b0..Absent
10383 */
10384#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
10385#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
10386#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
10387/* PRESENT_CRYPTO
10388 * 0b1..Present
10389 * 0b0..Absent
10390 */
10391#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
10392#define DCP_CTRL_CLKGATE_MASK (0x40000000U)
10393#define DCP_CTRL_CLKGATE_SHIFT (30U)
10394#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
10395#define DCP_CTRL_SFTRST_MASK (0x80000000U)
10396#define DCP_CTRL_SFTRST_SHIFT (31U)
10397#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
10398/* @} */
10399
10400/* @name CTRL_SET - DCP control register 0 */
10401/* @{ */
10402#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
10403#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
10404/* CHANNEL_INTERRUPT_ENABLE
10405 * 0b00000001..CH0
10406 * 0b00000010..CH1
10407 * 0b00000100..CH2
10408 * 0b00001000..CH3
10409 */
10410#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
10411#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
10412#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
10413#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
10414#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
10415#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
10416#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
10417#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
10418#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
10419#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
10420#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
10421#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
10422#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
10423#define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U)
10424#define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U)
10425/* PRESENT_SHA
10426 * 0b1..Present
10427 * 0b0..Absent
10428 */
10429#define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
10430#define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U)
10431#define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U)
10432/* PRESENT_CRYPTO
10433 * 0b1..Present
10434 * 0b0..Absent
10435 */
10436#define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
10437#define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U)
10438#define DCP_CTRL_SET_CLKGATE_SHIFT (30U)
10439#define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
10440#define DCP_CTRL_SET_SFTRST_MASK (0x80000000U)
10441#define DCP_CTRL_SET_SFTRST_SHIFT (31U)
10442#define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
10443/* @} */
10444
10445/* @name CTRL_CLR - DCP control register 0 */
10446/* @{ */
10447#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
10448#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
10449/* CHANNEL_INTERRUPT_ENABLE
10450 * 0b00000001..CH0
10451 * 0b00000010..CH1
10452 * 0b00000100..CH2
10453 * 0b00001000..CH3
10454 */
10455#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
10456#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
10457#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
10458#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
10459#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
10460#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
10461#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
10462#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
10463#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
10464#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
10465#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
10466#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
10467#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
10468#define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U)
10469#define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U)
10470/* PRESENT_SHA
10471 * 0b1..Present
10472 * 0b0..Absent
10473 */
10474#define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
10475#define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U)
10476#define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U)
10477/* PRESENT_CRYPTO
10478 * 0b1..Present
10479 * 0b0..Absent
10480 */
10481#define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
10482#define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
10483#define DCP_CTRL_CLR_CLKGATE_SHIFT (30U)
10484#define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
10485#define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U)
10486#define DCP_CTRL_CLR_SFTRST_SHIFT (31U)
10487#define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
10488/* @} */
10489
10490/* @name CTRL_TOG - DCP control register 0 */
10491/* @{ */
10492#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
10493#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
10494/* CHANNEL_INTERRUPT_ENABLE
10495 * 0b00000001..CH0
10496 * 0b00000010..CH1
10497 * 0b00000100..CH2
10498 * 0b00001000..CH3
10499 */
10500#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
10501#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
10502#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
10503#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
10504#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
10505#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
10506#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
10507#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
10508#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
10509#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
10510#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
10511#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
10512#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
10513#define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U)
10514#define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U)
10515/* PRESENT_SHA
10516 * 0b1..Present
10517 * 0b0..Absent
10518 */
10519#define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
10520#define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U)
10521#define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U)
10522/* PRESENT_CRYPTO
10523 * 0b1..Present
10524 * 0b0..Absent
10525 */
10526#define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
10527#define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
10528#define DCP_CTRL_TOG_CLKGATE_SHIFT (30U)
10529#define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
10530#define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U)
10531#define DCP_CTRL_TOG_SFTRST_SHIFT (31U)
10532#define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
10533/* @} */
10534
10535/* @name STAT - DCP status register */
10536/* @{ */
10537#define DCP_STAT_IRQ_MASK (0xFU)
10538#define DCP_STAT_IRQ_SHIFT (0U)
10539#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
10540#define DCP_STAT_RSVD_IRQ_MASK (0x100U)
10541#define DCP_STAT_RSVD_IRQ_SHIFT (8U)
10542#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
10543#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
10544#define DCP_STAT_READY_CHANNELS_SHIFT (16U)
10545/* READY_CHANNELS
10546 * 0b00000001..CH0
10547 * 0b00000010..CH1
10548 * 0b00000100..CH2
10549 * 0b00001000..CH3
10550 */
10551#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
10552#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
10553#define DCP_STAT_CUR_CHANNEL_SHIFT (24U)
10554/* CUR_CHANNEL
10555 * 0b0000..None
10556 * 0b0001..CH0
10557 * 0b0010..CH1
10558 * 0b0011..CH2
10559 * 0b0100..CH3
10560 */
10561#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
10562#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
10563#define DCP_STAT_OTP_KEY_READY_SHIFT (28U)
10564#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
10565/* @} */
10566
10567/* @name STAT_SET - DCP status register */
10568/* @{ */
10569#define DCP_STAT_SET_IRQ_MASK (0xFU)
10570#define DCP_STAT_SET_IRQ_SHIFT (0U)
10571#define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
10572#define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U)
10573#define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U)
10574#define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
10575#define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U)
10576#define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U)
10577/* READY_CHANNELS
10578 * 0b00000001..CH0
10579 * 0b00000010..CH1
10580 * 0b00000100..CH2
10581 * 0b00001000..CH3
10582 */
10583#define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
10584#define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U)
10585#define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U)
10586/* CUR_CHANNEL
10587 * 0b0000..None
10588 * 0b0001..CH0
10589 * 0b0010..CH1
10590 * 0b0011..CH2
10591 * 0b0100..CH3
10592 */
10593#define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
10594#define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U)
10595#define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U)
10596#define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
10597/* @} */
10598
10599/* @name STAT_CLR - DCP status register */
10600/* @{ */
10601#define DCP_STAT_CLR_IRQ_MASK (0xFU)
10602#define DCP_STAT_CLR_IRQ_SHIFT (0U)
10603#define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
10604#define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U)
10605#define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U)
10606#define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
10607#define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U)
10608#define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U)
10609/* READY_CHANNELS
10610 * 0b00000001..CH0
10611 * 0b00000010..CH1
10612 * 0b00000100..CH2
10613 * 0b00001000..CH3
10614 */
10615#define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
10616#define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U)
10617#define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U)
10618/* CUR_CHANNEL
10619 * 0b0000..None
10620 * 0b0001..CH0
10621 * 0b0010..CH1
10622 * 0b0011..CH2
10623 * 0b0100..CH3
10624 */
10625#define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
10626#define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U)
10627#define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U)
10628#define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
10629/* @} */
10630
10631/* @name STAT_TOG - DCP status register */
10632/* @{ */
10633#define DCP_STAT_TOG_IRQ_MASK (0xFU)
10634#define DCP_STAT_TOG_IRQ_SHIFT (0U)
10635#define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
10636#define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U)
10637#define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U)
10638#define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
10639#define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U)
10640#define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U)
10641/* READY_CHANNELS
10642 * 0b00000001..CH0
10643 * 0b00000010..CH1
10644 * 0b00000100..CH2
10645 * 0b00001000..CH3
10646 */
10647#define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
10648#define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U)
10649#define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U)
10650/* CUR_CHANNEL
10651 * 0b0000..None
10652 * 0b0001..CH0
10653 * 0b0010..CH1
10654 * 0b0011..CH2
10655 * 0b0100..CH3
10656 */
10657#define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
10658#define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U)
10659#define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U)
10660#define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
10661/* @} */
10662
10663/* @name CHANNELCTRL - DCP channel control register */
10664/* @{ */
10665#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
10666#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
10667/* ENABLE_CHANNEL
10668 * 0b00000001..CH0
10669 * 0b00000010..CH1
10670 * 0b00000100..CH2
10671 * 0b00001000..CH3
10672 */
10673#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
10674#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
10675#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
10676/* HIGH_PRIORITY_CHANNEL
10677 * 0b00000001..CH0
10678 * 0b00000010..CH1
10679 * 0b00000100..CH2
10680 * 0b00001000..CH3
10681 */
10682#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
10683#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
10684#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
10685#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
10686#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
10687#define DCP_CHANNELCTRL_RSVD_SHIFT (17U)
10688#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
10689/* @} */
10690
10691/* @name CHANNELCTRL_SET - DCP channel control register */
10692/* @{ */
10693#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU)
10694#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
10695/* ENABLE_CHANNEL
10696 * 0b00000001..CH0
10697 * 0b00000010..CH1
10698 * 0b00000100..CH2
10699 * 0b00001000..CH3
10700 */
10701#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
10702#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
10703#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
10704/* HIGH_PRIORITY_CHANNEL
10705 * 0b00000001..CH0
10706 * 0b00000010..CH1
10707 * 0b00000100..CH2
10708 * 0b00001000..CH3
10709 */
10710#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
10711#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U)
10712#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
10713#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
10714#define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U)
10715#define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U)
10716#define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
10717/* @} */
10718
10719/* @name CHANNELCTRL_CLR - DCP channel control register */
10720/* @{ */
10721#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU)
10722#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
10723/* ENABLE_CHANNEL
10724 * 0b00000001..CH0
10725 * 0b00000010..CH1
10726 * 0b00000100..CH2
10727 * 0b00001000..CH3
10728 */
10729#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
10730#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
10731#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
10732/* HIGH_PRIORITY_CHANNEL
10733 * 0b00000001..CH0
10734 * 0b00000010..CH1
10735 * 0b00000100..CH2
10736 * 0b00001000..CH3
10737 */
10738#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
10739#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U)
10740#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
10741#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
10742#define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U)
10743#define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U)
10744#define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
10745/* @} */
10746
10747/* @name CHANNELCTRL_TOG - DCP channel control register */
10748/* @{ */
10749#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU)
10750#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
10751/* ENABLE_CHANNEL
10752 * 0b00000001..CH0
10753 * 0b00000010..CH1
10754 * 0b00000100..CH2
10755 * 0b00001000..CH3
10756 */
10757#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
10758#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
10759#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
10760/* HIGH_PRIORITY_CHANNEL
10761 * 0b00000001..CH0
10762 * 0b00000010..CH1
10763 * 0b00000100..CH2
10764 * 0b00001000..CH3
10765 */
10766#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
10767#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U)
10768#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
10769#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
10770#define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U)
10771#define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U)
10772#define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
10773/* @} */
10774
10775/* @name CAPABILITY0 - DCP capability 0 register */
10776/* @{ */
10777#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
10778#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
10779#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
10780#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
10781#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
10782#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
10783#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
10784#define DCP_CAPABILITY0_RSVD_SHIFT (12U)
10785#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
10786#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
10787#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
10788#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
10789#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
10790#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
10791#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
10792/* @} */
10793
10794/* @name CAPABILITY1 - DCP capability 1 register */
10795/* @{ */
10796#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
10797#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
10798/* CIPHER_ALGORITHMS
10799 * 0b0000000000000001..AES128
10800 */
10801#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
10802#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
10803#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
10804/* HASH_ALGORITHMS
10805 * 0b0000000000000001..SHA1
10806 * 0b0000000000000010..CRC32
10807 * 0b0000000000000100..SHA256
10808 */
10809#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
10810/* @} */
10811
10812/* @name CONTEXT - DCP context buffer pointer */
10813/* @{ */
10814#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
10815#define DCP_CONTEXT_ADDR_SHIFT (0U)
10816#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
10817/* @} */
10818
10819/* @name KEY - DCP key index */
10820/* @{ */
10821#define DCP_KEY_SUBWORD_MASK (0x3U)
10822#define DCP_KEY_SUBWORD_SHIFT (0U)
10823#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
10824#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
10825#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
10826#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
10827#define DCP_KEY_INDEX_MASK (0x30U)
10828#define DCP_KEY_INDEX_SHIFT (4U)
10829#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
10830#define DCP_KEY_RSVD_INDEX_MASK (0xC0U)
10831#define DCP_KEY_RSVD_INDEX_SHIFT (6U)
10832#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
10833#define DCP_KEY_RSVD_MASK (0xFFFFFF00U)
10834#define DCP_KEY_RSVD_SHIFT (8U)
10835#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
10836/* @} */
10837
10838/* @name KEYDATA - DCP key data */
10839/* @{ */
10840#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
10841#define DCP_KEYDATA_DATA_SHIFT (0U)
10842#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
10843/* @} */
10844
10845/* @name PACKET0 - DCP work packet 0 status register */
10846/* @{ */
10847#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
10848#define DCP_PACKET0_ADDR_SHIFT (0U)
10849#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
10850/* @} */
10851
10852/* @name PACKET1 - DCP work packet 1 status register */
10853/* @{ */
10854#define DCP_PACKET1_INTERRUPT_MASK (0x1U)
10855#define DCP_PACKET1_INTERRUPT_SHIFT (0U)
10856#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
10857#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
10858#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
10859#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
10860#define DCP_PACKET1_CHAIN_MASK (0x4U)
10861#define DCP_PACKET1_CHAIN_SHIFT (2U)
10862#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
10863#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
10864#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
10865#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
10866#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
10867#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
10868#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
10869#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
10870#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
10871#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
10872#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
10873#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
10874#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
10875#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
10876#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
10877#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
10878#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
10879#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
10880/* CIPHER_ENCRYPT
10881 * 0b1..ENCRYPT
10882 * 0b0..DECRYPT
10883 */
10884#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
10885#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
10886#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
10887#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
10888#define DCP_PACKET1_OTP_KEY_MASK (0x400U)
10889#define DCP_PACKET1_OTP_KEY_SHIFT (10U)
10890#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
10891#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
10892#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
10893#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
10894#define DCP_PACKET1_HASH_INIT_MASK (0x1000U)
10895#define DCP_PACKET1_HASH_INIT_SHIFT (12U)
10896#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
10897#define DCP_PACKET1_HASH_TERM_MASK (0x2000U)
10898#define DCP_PACKET1_HASH_TERM_SHIFT (13U)
10899#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
10900#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
10901#define DCP_PACKET1_CHECK_HASH_SHIFT (14U)
10902#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
10903#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
10904#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
10905/* HASH_OUTPUT
10906 * 0b0..INPUT
10907 * 0b1..OUTPUT
10908 */
10909#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
10910#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
10911#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
10912#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
10913#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
10914#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
10915#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
10916#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
10917#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
10918#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
10919#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
10920#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
10921#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
10922#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
10923#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
10924#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
10925#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
10926#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
10927#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
10928#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
10929#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
10930#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
10931#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
10932#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
10933#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
10934#define DCP_PACKET1_TAG_MASK (0xFF000000U)
10935#define DCP_PACKET1_TAG_SHIFT (24U)
10936#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
10937/* @} */
10938
10939/* @name PACKET2 - DCP work packet 2 status register */
10940/* @{ */
10941#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
10942#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
10943/* CIPHER_SELECT
10944 * 0b0000..AES128
10945 */
10946#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
10947#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
10948#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
10949/* CIPHER_MODE
10950 * 0b0000..ECB
10951 * 0b0001..CBC
10952 */
10953#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
10954#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
10955#define DCP_PACKET2_KEY_SELECT_SHIFT (8U)
10956/* KEY_SELECT
10957 * 0b00000000..KEY0
10958 * 0b00000001..KEY1
10959 * 0b00000010..KEY2
10960 * 0b00000011..KEY3
10961 * 0b11111110..UNIQUE_KEY
10962 * 0b11111111..OTP_KEY
10963 */
10964#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
10965#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
10966#define DCP_PACKET2_HASH_SELECT_SHIFT (16U)
10967/* HASH_SELECT
10968 * 0b0000..SHA1
10969 * 0b0001..CRC32
10970 * 0b0010..SHA256
10971 */
10972#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
10973#define DCP_PACKET2_RSVD_MASK (0xF00000U)
10974#define DCP_PACKET2_RSVD_SHIFT (20U)
10975#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
10976#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
10977#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
10978#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
10979/* @} */
10980
10981/* @name PACKET3 - DCP work packet 3 status register */
10982/* @{ */
10983#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
10984#define DCP_PACKET3_ADDR_SHIFT (0U)
10985#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
10986/* @} */
10987
10988/* @name PACKET4 - DCP work packet 4 status register */
10989/* @{ */
10990#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
10991#define DCP_PACKET4_ADDR_SHIFT (0U)
10992#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
10993/* @} */
10994
10995/* @name PACKET5 - DCP work packet 5 status register */
10996/* @{ */
10997#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
10998#define DCP_PACKET5_COUNT_SHIFT (0U)
10999#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
11000/* @} */
11001
11002/* @name PACKET6 - DCP work packet 6 status register */
11003/* @{ */
11004#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
11005#define DCP_PACKET6_ADDR_SHIFT (0U)
11006#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
11007/* @} */
11008
11009/* @name CH0CMDPTR - DCP channel 0 command pointer address register */
11010/* @{ */
11011#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
11012#define DCP_CH0CMDPTR_ADDR_SHIFT (0U)
11013#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
11014/* @} */
11015
11016/* @name CH0SEMA - DCP channel 0 semaphore register */
11017/* @{ */
11018#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
11019#define DCP_CH0SEMA_INCREMENT_SHIFT (0U)
11020#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
11021#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
11022#define DCP_CH0SEMA_VALUE_SHIFT (16U)
11023#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
11024/* @} */
11025
11026/* @name CH0STAT - DCP channel 0 status register */
11027/* @{ */
11028#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
11029#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
11030#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
11031#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
11032#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
11033#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
11034#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
11035#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
11036#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
11037#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
11038#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
11039#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
11040#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
11041#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
11042#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
11043#define DCP_CH0STAT_ERROR_DST_MASK (0x20U)
11044#define DCP_CH0STAT_ERROR_DST_SHIFT (5U)
11045#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
11046#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
11047#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
11048#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
11049#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
11050#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
11051/* ERROR_CODE
11052 * 0b00000001..Error signalled because the next pointer is 0x00000000
11053 * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
11054 * 0b00000011..Error signalled because an error is reported reading/writing the context buffer
11055 * 0b00000100..Error signalled because an error is reported reading/writing the payload
11056 * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
11057 */
11058#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
11059#define DCP_CH0STAT_TAG_MASK (0xFF000000U)
11060#define DCP_CH0STAT_TAG_SHIFT (24U)
11061#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
11062/* @} */
11063
11064/* @name CH0STAT_SET - DCP channel 0 status register */
11065/* @{ */
11066#define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U)
11067#define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U)
11068#define DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
11069#define DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U)
11070#define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U)
11071#define DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
11072#define DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U)
11073#define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U)
11074#define DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
11075#define DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U)
11076#define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U)
11077#define DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
11078#define DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U)
11079#define DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U)
11080#define DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
11081#define DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U)
11082#define DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U)
11083#define DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
11084#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
11085#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
11086#define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
11087#define DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U)
11088#define DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U)
11089/* ERROR_CODE
11090 * 0b00000001..Error signalled because the next pointer is 0x00000000
11091 * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
11092 * 0b00000011..Error signalled because an error is reported reading/writing the context buffer
11093 * 0b00000100..Error signalled because an error is reported reading/writing the payload
11094 * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
11095 */
11096#define DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
11097#define DCP_CH0STAT_SET_TAG_MASK (0xFF000000U)
11098#define DCP_CH0STAT_SET_TAG_SHIFT (24U)
11099#define DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
11100/* @} */
11101
11102/* @name CH0STAT_CLR - DCP channel 0 status register */
11103/* @{ */
11104#define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
11105#define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
11106#define DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
11107#define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U)
11108#define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U)
11109#define DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
11110#define DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U)
11111#define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U)
11112#define DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
11113#define DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U)
11114#define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U)
11115#define DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
11116#define DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U)
11117#define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U)
11118#define DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
11119#define DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U)
11120#define DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U)
11121#define DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
11122#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
11123#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
11124#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
11125#define DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
11126#define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U)
11127/* ERROR_CODE
11128 * 0b00000001..Error signalled because the next pointer is 0x00000000
11129 * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
11130 * 0b00000011..Error signalled because an error is reported reading/writing the context buffer
11131 * 0b00000100..Error signalled because an error is reported reading/writing the payload
11132 * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
11133 */
11134#define DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
11135#define DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U)
11136#define DCP_CH0STAT_CLR_TAG_SHIFT (24U)
11137#define DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
11138/* @} */
11139
11140/* @name CH0STAT_TOG - DCP channel 0 status register */
11141/* @{ */
11142#define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
11143#define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
11144#define DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
11145#define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U)
11146#define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U)
11147#define DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
11148#define DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U)
11149#define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U)
11150#define DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
11151#define DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U)
11152#define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U)
11153#define DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
11154#define DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U)
11155#define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U)
11156#define DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
11157#define DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U)
11158#define DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U)
11159#define DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
11160#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
11161#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
11162#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
11163#define DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
11164#define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U)
11165/* ERROR_CODE
11166 * 0b00000001..Error signalled because the next pointer is 0x00000000
11167 * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
11168 * 0b00000011..Error signalled because an error is reported reading/writing the context buffer
11169 * 0b00000100..Error signalled because an error is reported reading/writing the payload
11170 * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
11171 */
11172#define DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
11173#define DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U)
11174#define DCP_CH0STAT_TOG_TAG_SHIFT (24U)
11175#define DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
11176/* @} */
11177
11178/* @name CH0OPTS - DCP channel 0 options register */
11179/* @{ */
11180#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
11181#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
11182#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
11183#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
11184#define DCP_CH0OPTS_RSVD_SHIFT (16U)
11185#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
11186/* @} */
11187
11188/* @name CH0OPTS_SET - DCP channel 0 options register */
11189/* @{ */
11190#define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
11191#define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
11192#define DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
11193#define DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U)
11194#define DCP_CH0OPTS_SET_RSVD_SHIFT (16U)
11195#define DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
11196/* @} */
11197
11198/* @name CH0OPTS_CLR - DCP channel 0 options register */
11199/* @{ */
11200#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
11201#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
11202#define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
11203#define DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U)
11204#define DCP_CH0OPTS_CLR_RSVD_SHIFT (16U)
11205#define DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
11206/* @} */
11207
11208/* @name CH0OPTS_TOG - DCP channel 0 options register */
11209/* @{ */
11210#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
11211#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
11212#define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
11213#define DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U)
11214#define DCP_CH0OPTS_TOG_RSVD_SHIFT (16U)
11215#define DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
11216/* @} */
11217
11218/* @name CH1CMDPTR - DCP channel 1 command pointer address register */
11219/* @{ */
11220#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
11221#define DCP_CH1CMDPTR_ADDR_SHIFT (0U)
11222#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
11223/* @} */
11224
11225/* @name CH1SEMA - DCP channel 1 semaphore register */
11226/* @{ */
11227#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
11228#define DCP_CH1SEMA_INCREMENT_SHIFT (0U)
11229#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
11230#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
11231#define DCP_CH1SEMA_VALUE_SHIFT (16U)
11232#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
11233/* @} */
11234
11235/* @name CH1STAT - DCP channel 1 status register */
11236/* @{ */
11237#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
11238#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
11239#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
11240#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
11241#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
11242#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
11243#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
11244#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
11245#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
11246#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
11247#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
11248#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
11249#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
11250#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
11251#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
11252#define DCP_CH1STAT_ERROR_DST_MASK (0x20U)
11253#define DCP_CH1STAT_ERROR_DST_SHIFT (5U)
11254#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
11255#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
11256#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
11257#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
11258#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
11259#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
11260/* ERROR_CODE
11261 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11262 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11263 * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
11264 * 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
11265 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
11266 */
11267#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
11268#define DCP_CH1STAT_TAG_MASK (0xFF000000U)
11269#define DCP_CH1STAT_TAG_SHIFT (24U)
11270#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
11271/* @} */
11272
11273/* @name CH1STAT_SET - DCP channel 1 status register */
11274/* @{ */
11275#define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U)
11276#define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U)
11277#define DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
11278#define DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U)
11279#define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U)
11280#define DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
11281#define DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U)
11282#define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U)
11283#define DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
11284#define DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U)
11285#define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U)
11286#define DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
11287#define DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U)
11288#define DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U)
11289#define DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
11290#define DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U)
11291#define DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U)
11292#define DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
11293#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
11294#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
11295#define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
11296#define DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U)
11297#define DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U)
11298/* ERROR_CODE
11299 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11300 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11301 * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
11302 * 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
11303 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
11304 */
11305#define DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
11306#define DCP_CH1STAT_SET_TAG_MASK (0xFF000000U)
11307#define DCP_CH1STAT_SET_TAG_SHIFT (24U)
11308#define DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
11309/* @} */
11310
11311/* @name CH1STAT_CLR - DCP channel 1 status register */
11312/* @{ */
11313#define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
11314#define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
11315#define DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
11316#define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U)
11317#define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U)
11318#define DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
11319#define DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U)
11320#define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U)
11321#define DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
11322#define DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U)
11323#define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U)
11324#define DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
11325#define DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U)
11326#define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U)
11327#define DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
11328#define DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U)
11329#define DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U)
11330#define DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
11331#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
11332#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
11333#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
11334#define DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
11335#define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U)
11336/* ERROR_CODE
11337 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11338 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11339 * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
11340 * 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
11341 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
11342 */
11343#define DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
11344#define DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U)
11345#define DCP_CH1STAT_CLR_TAG_SHIFT (24U)
11346#define DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
11347/* @} */
11348
11349/* @name CH1STAT_TOG - DCP channel 1 status register */
11350/* @{ */
11351#define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
11352#define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
11353#define DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
11354#define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U)
11355#define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U)
11356#define DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
11357#define DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U)
11358#define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U)
11359#define DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
11360#define DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U)
11361#define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U)
11362#define DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
11363#define DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U)
11364#define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U)
11365#define DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
11366#define DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U)
11367#define DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U)
11368#define DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
11369#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
11370#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
11371#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
11372#define DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
11373#define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U)
11374/* ERROR_CODE
11375 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11376 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11377 * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
11378 * 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
11379 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
11380 */
11381#define DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
11382#define DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U)
11383#define DCP_CH1STAT_TOG_TAG_SHIFT (24U)
11384#define DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
11385/* @} */
11386
11387/* @name CH1OPTS - DCP channel 1 options register */
11388/* @{ */
11389#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
11390#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
11391#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
11392#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
11393#define DCP_CH1OPTS_RSVD_SHIFT (16U)
11394#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
11395/* @} */
11396
11397/* @name CH1OPTS_SET - DCP channel 1 options register */
11398/* @{ */
11399#define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
11400#define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
11401#define DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
11402#define DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U)
11403#define DCP_CH1OPTS_SET_RSVD_SHIFT (16U)
11404#define DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
11405/* @} */
11406
11407/* @name CH1OPTS_CLR - DCP channel 1 options register */
11408/* @{ */
11409#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
11410#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
11411#define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
11412#define DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U)
11413#define DCP_CH1OPTS_CLR_RSVD_SHIFT (16U)
11414#define DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
11415/* @} */
11416
11417/* @name CH1OPTS_TOG - DCP channel 1 options register */
11418/* @{ */
11419#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
11420#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
11421#define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
11422#define DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U)
11423#define DCP_CH1OPTS_TOG_RSVD_SHIFT (16U)
11424#define DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
11425/* @} */
11426
11427/* @name CH2CMDPTR - DCP channel 2 command pointer address register */
11428/* @{ */
11429#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
11430#define DCP_CH2CMDPTR_ADDR_SHIFT (0U)
11431#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
11432/* @} */
11433
11434/* @name CH2SEMA - DCP channel 2 semaphore register */
11435/* @{ */
11436#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
11437#define DCP_CH2SEMA_INCREMENT_SHIFT (0U)
11438#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
11439#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
11440#define DCP_CH2SEMA_VALUE_SHIFT (16U)
11441#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
11442/* @} */
11443
11444/* @name CH2STAT - DCP channel 2 status register */
11445/* @{ */
11446#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
11447#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
11448#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
11449#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
11450#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
11451#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
11452#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
11453#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
11454#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
11455#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
11456#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
11457#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
11458#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
11459#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
11460#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
11461#define DCP_CH2STAT_ERROR_DST_MASK (0x20U)
11462#define DCP_CH2STAT_ERROR_DST_SHIFT (5U)
11463#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
11464#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
11465#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
11466#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
11467#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
11468#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
11469/* ERROR_CODE
11470 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11471 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11472 * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
11473 * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
11474 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
11475 */
11476#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
11477#define DCP_CH2STAT_TAG_MASK (0xFF000000U)
11478#define DCP_CH2STAT_TAG_SHIFT (24U)
11479#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
11480/* @} */
11481
11482/* @name CH2STAT_SET - DCP channel 2 status register */
11483/* @{ */
11484#define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U)
11485#define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U)
11486#define DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
11487#define DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U)
11488#define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U)
11489#define DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
11490#define DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U)
11491#define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U)
11492#define DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
11493#define DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U)
11494#define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U)
11495#define DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
11496#define DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U)
11497#define DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U)
11498#define DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
11499#define DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U)
11500#define DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U)
11501#define DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
11502#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
11503#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
11504#define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
11505#define DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U)
11506#define DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U)
11507/* ERROR_CODE
11508 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11509 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11510 * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
11511 * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
11512 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
11513 */
11514#define DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
11515#define DCP_CH2STAT_SET_TAG_MASK (0xFF000000U)
11516#define DCP_CH2STAT_SET_TAG_SHIFT (24U)
11517#define DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
11518/* @} */
11519
11520/* @name CH2STAT_CLR - DCP channel 2 status register */
11521/* @{ */
11522#define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
11523#define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
11524#define DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
11525#define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U)
11526#define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U)
11527#define DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
11528#define DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U)
11529#define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U)
11530#define DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
11531#define DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U)
11532#define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U)
11533#define DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
11534#define DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U)
11535#define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U)
11536#define DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
11537#define DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U)
11538#define DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U)
11539#define DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
11540#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
11541#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
11542#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
11543#define DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
11544#define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U)
11545/* ERROR_CODE
11546 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11547 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11548 * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
11549 * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
11550 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
11551 */
11552#define DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
11553#define DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U)
11554#define DCP_CH2STAT_CLR_TAG_SHIFT (24U)
11555#define DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
11556/* @} */
11557
11558/* @name CH2STAT_TOG - DCP channel 2 status register */
11559/* @{ */
11560#define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
11561#define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
11562#define DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
11563#define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U)
11564#define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U)
11565#define DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
11566#define DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U)
11567#define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U)
11568#define DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
11569#define DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U)
11570#define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U)
11571#define DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
11572#define DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U)
11573#define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U)
11574#define DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
11575#define DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U)
11576#define DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U)
11577#define DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
11578#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
11579#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
11580#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
11581#define DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
11582#define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U)
11583/* ERROR_CODE
11584 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11585 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11586 * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
11587 * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
11588 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
11589 */
11590#define DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
11591#define DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U)
11592#define DCP_CH2STAT_TOG_TAG_SHIFT (24U)
11593#define DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
11594/* @} */
11595
11596/* @name CH2OPTS - DCP channel 2 options register */
11597/* @{ */
11598#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
11599#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
11600#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
11601#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
11602#define DCP_CH2OPTS_RSVD_SHIFT (16U)
11603#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
11604/* @} */
11605
11606/* @name CH2OPTS_SET - DCP channel 2 options register */
11607/* @{ */
11608#define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
11609#define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
11610#define DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
11611#define DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U)
11612#define DCP_CH2OPTS_SET_RSVD_SHIFT (16U)
11613#define DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
11614/* @} */
11615
11616/* @name CH2OPTS_CLR - DCP channel 2 options register */
11617/* @{ */
11618#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
11619#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
11620#define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
11621#define DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U)
11622#define DCP_CH2OPTS_CLR_RSVD_SHIFT (16U)
11623#define DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
11624/* @} */
11625
11626/* @name CH2OPTS_TOG - DCP channel 2 options register */
11627/* @{ */
11628#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
11629#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
11630#define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
11631#define DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U)
11632#define DCP_CH2OPTS_TOG_RSVD_SHIFT (16U)
11633#define DCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK)
11634/* @} */
11635
11636/* @name CH3CMDPTR - DCP channel 3 command pointer address register */
11637/* @{ */
11638#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU)
11639#define DCP_CH3CMDPTR_ADDR_SHIFT (0U)
11640#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK)
11641/* @} */
11642
11643/* @name CH3SEMA - DCP channel 3 semaphore register */
11644/* @{ */
11645#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU)
11646#define DCP_CH3SEMA_INCREMENT_SHIFT (0U)
11647#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK)
11648#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U)
11649#define DCP_CH3SEMA_VALUE_SHIFT (16U)
11650#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK)
11651/* @} */
11652
11653/* @name CH3STAT - DCP channel 3 status register */
11654/* @{ */
11655#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U)
11656#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U)
11657#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK)
11658#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U)
11659#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U)
11660#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK)
11661#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U)
11662#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U)
11663#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK)
11664#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U)
11665#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U)
11666#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK)
11667#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U)
11668#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U)
11669#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK)
11670#define DCP_CH3STAT_ERROR_DST_MASK (0x20U)
11671#define DCP_CH3STAT_ERROR_DST_SHIFT (5U)
11672#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK)
11673#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U)
11674#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U)
11675#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK)
11676#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U)
11677#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U)
11678/* ERROR_CODE
11679 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11680 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11681 * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
11682 * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
11683 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
11684 */
11685#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK)
11686#define DCP_CH3STAT_TAG_MASK (0xFF000000U)
11687#define DCP_CH3STAT_TAG_SHIFT (24U)
11688#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK)
11689/* @} */
11690
11691/* @name CH3STAT_SET - DCP channel 3 status register */
11692/* @{ */
11693#define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U)
11694#define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U)
11695#define DCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK)
11696#define DCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U)
11697#define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U)
11698#define DCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK)
11699#define DCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U)
11700#define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U)
11701#define DCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK)
11702#define DCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U)
11703#define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U)
11704#define DCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK)
11705#define DCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U)
11706#define DCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U)
11707#define DCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK)
11708#define DCP_CH3STAT_SET_ERROR_DST_MASK (0x20U)
11709#define DCP_CH3STAT_SET_ERROR_DST_SHIFT (5U)
11710#define DCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK)
11711#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
11712#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
11713#define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK)
11714#define DCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U)
11715#define DCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U)
11716/* ERROR_CODE
11717 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11718 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11719 * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
11720 * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
11721 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
11722 */
11723#define DCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK)
11724#define DCP_CH3STAT_SET_TAG_MASK (0xFF000000U)
11725#define DCP_CH3STAT_SET_TAG_SHIFT (24U)
11726#define DCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK)
11727/* @} */
11728
11729/* @name CH3STAT_CLR - DCP channel 3 status register */
11730/* @{ */
11731#define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
11732#define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
11733#define DCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK)
11734#define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U)
11735#define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U)
11736#define DCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK)
11737#define DCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U)
11738#define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U)
11739#define DCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK)
11740#define DCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U)
11741#define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U)
11742#define DCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK)
11743#define DCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U)
11744#define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U)
11745#define DCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK)
11746#define DCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U)
11747#define DCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U)
11748#define DCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK)
11749#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
11750#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
11751#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK)
11752#define DCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
11753#define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U)
11754/* ERROR_CODE
11755 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11756 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11757 * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
11758 * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
11759 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
11760 */
11761#define DCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK)
11762#define DCP_CH3STAT_CLR_TAG_MASK (0xFF000000U)
11763#define DCP_CH3STAT_CLR_TAG_SHIFT (24U)
11764#define DCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK)
11765/* @} */
11766
11767/* @name CH3STAT_TOG - DCP channel 3 status register */
11768/* @{ */
11769#define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
11770#define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
11771#define DCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK)
11772#define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U)
11773#define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U)
11774#define DCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK)
11775#define DCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U)
11776#define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U)
11777#define DCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK)
11778#define DCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U)
11779#define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U)
11780#define DCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK)
11781#define DCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U)
11782#define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U)
11783#define DCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK)
11784#define DCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U)
11785#define DCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U)
11786#define DCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK)
11787#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
11788#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
11789#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK)
11790#define DCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
11791#define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U)
11792/* ERROR_CODE
11793 * 0b00000001..Error is signalled because the next pointer is 0x00000000.
11794 * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
11795 * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
11796 * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
11797 * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
11798 */
11799#define DCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK)
11800#define DCP_CH3STAT_TOG_TAG_MASK (0xFF000000U)
11801#define DCP_CH3STAT_TOG_TAG_SHIFT (24U)
11802#define DCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK)
11803/* @} */
11804
11805/* @name CH3OPTS - DCP channel 3 options register */
11806/* @{ */
11807#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
11808#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U)
11809#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK)
11810#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U)
11811#define DCP_CH3OPTS_RSVD_SHIFT (16U)
11812#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK)
11813/* @} */
11814
11815/* @name CH3OPTS_SET - DCP channel 3 options register */
11816/* @{ */
11817#define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
11818#define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
11819#define DCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK)
11820#define DCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U)
11821#define DCP_CH3OPTS_SET_RSVD_SHIFT (16U)
11822#define DCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK)
11823/* @} */
11824
11825/* @name CH3OPTS_CLR - DCP channel 3 options register */
11826/* @{ */
11827#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
11828#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
11829#define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK)
11830#define DCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U)
11831#define DCP_CH3OPTS_CLR_RSVD_SHIFT (16U)
11832#define DCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK)
11833/* @} */
11834
11835/* @name CH3OPTS_TOG - DCP channel 3 options register */
11836/* @{ */
11837#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
11838#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
11839#define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK)
11840#define DCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U)
11841#define DCP_CH3OPTS_TOG_RSVD_SHIFT (16U)
11842#define DCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK)
11843/* @} */
11844
11845/* @name DBGSELECT - DCP debug select register */
11846/* @{ */
11847#define DCP_DBGSELECT_INDEX_MASK (0xFFU)
11848#define DCP_DBGSELECT_INDEX_SHIFT (0U)
11849/* INDEX
11850 * 0b00000001..CONTROL
11851 * 0b00010000..OTPKEY0
11852 * 0b00010001..OTPKEY1
11853 * 0b00010010..OTPKEY2
11854 * 0b00010011..OTPKEY3
11855 */
11856#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK)
11857#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U)
11858#define DCP_DBGSELECT_RSVD_SHIFT (8U)
11859#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK)
11860/* @} */
11861
11862/* @name DBGDATA - DCP debug data register */
11863/* @{ */
11864#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU)
11865#define DCP_DBGDATA_DATA_SHIFT (0U)
11866#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK)
11867/* @} */
11868
11869/* @name PAGETABLE - DCP page table register */
11870/* @{ */
11871#define DCP_PAGETABLE_ENABLE_MASK (0x1U)
11872#define DCP_PAGETABLE_ENABLE_SHIFT (0U)
11873#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK)
11874#define DCP_PAGETABLE_FLUSH_MASK (0x2U)
11875#define DCP_PAGETABLE_FLUSH_SHIFT (1U)
11876#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK)
11877#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU)
11878#define DCP_PAGETABLE_BASE_SHIFT (2U)
11879#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK)
11880/* @} */
11881
11882/* @name VERSION - DCP version register */
11883/* @{ */
11884#define DCP_VERSION_STEP_MASK (0xFFFFU)
11885#define DCP_VERSION_STEP_SHIFT (0U)
11886#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK)
11887#define DCP_VERSION_MINOR_MASK (0xFF0000U)
11888#define DCP_VERSION_MINOR_SHIFT (16U)
11889#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK)
11890#define DCP_VERSION_MAJOR_MASK (0xFF000000U)
11891#define DCP_VERSION_MAJOR_SHIFT (24U)
11892#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK)
11893/* @} */
11894
11895
11896/*
11897 * @}
11898 */ /* end of group DCP_Register_Masks */
11899
11900
11901/* DCP - Peripheral instance base addresses */
11902/* Peripheral DCP base address */
11903#define DCP_BASE (0x402FC000u)
11904/* Peripheral DCP base pointer */
11905#define DCP ((DCP_Type *)DCP_BASE)
11906/* Array initializer of DCP peripheral base addresses */
11907#define DCP_BASE_ADDRS { DCP_BASE }
11908/* Array initializer of DCP peripheral base pointers */
11909#define DCP_BASE_PTRS { DCP }
11910/* Interrupt vectors for the DCP peripheral type */
11911#define DCP_IRQS { DCP_IRQn }
11912#define DCP_VMI_IRQS { DCP_VMI_IRQn }
11913
11914/*
11915 * @}
11916 */ /* end of group DCP_Peripheral_Access_Layer */
11917
11918
11919/* ----------------------------------------------------------------------------
11920 -- DMA Peripheral Access Layer
11921 ---------------------------------------------------------------------------- */
11922
11923/*
11924 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
11925 * @{
11926 */
11927
11928/* DMA - Register Layout Typedef */
11929typedef struct {
11930 __IO uint32_t CR;
11931 __I uint32_t ES;
11932 uint8_t RESERVED_0[4];
11933 __IO uint32_t ERQ;
11934 uint8_t RESERVED_1[4];
11935 __IO uint32_t EEI;
11936 __O uint8_t CEEI;
11937 __O uint8_t SEEI;
11938 __O uint8_t CERQ;
11939 __O uint8_t SERQ;
11940 __O uint8_t CDNE;
11941 __O uint8_t SSRT;
11942 __O uint8_t CERR;
11943 __O uint8_t CINT;
11944 uint8_t RESERVED_2[4];
11945 __IO uint32_t INT;
11946 uint8_t RESERVED_3[4];
11947 __IO uint32_t ERR;
11948 uint8_t RESERVED_4[4];
11949 __I uint32_t HRS;
11950 uint8_t RESERVED_5[12];
11951 __IO uint32_t EARS;
11952 uint8_t RESERVED_6[184];
11953 union {
11954 struct {
11955 __IO uint8_t DCHPRI3;
11956 __IO uint8_t DCHPRI2;
11957 __IO uint8_t DCHPRI1;
11958 __IO uint8_t DCHPRI0;
11959 __IO uint8_t DCHPRI7;
11960 __IO uint8_t DCHPRI6;
11961 __IO uint8_t DCHPRI5;
11962 __IO uint8_t DCHPRI4;
11963 __IO uint8_t DCHPRI11;
11964 __IO uint8_t DCHPRI10;
11965 __IO uint8_t DCHPRI9;
11966 __IO uint8_t DCHPRI8;
11967 __IO uint8_t DCHPRI15;
11968 __IO uint8_t DCHPRI14;
11969 __IO uint8_t DCHPRI13;
11970 __IO uint8_t DCHPRI12;
11971 __IO uint8_t DCHPRI19;
11972 __IO uint8_t DCHPRI18;
11973 __IO uint8_t DCHPRI17;
11974 __IO uint8_t DCHPRI16;
11975 __IO uint8_t DCHPRI23;
11976 __IO uint8_t DCHPRI22;
11977 __IO uint8_t DCHPRI21;
11978 __IO uint8_t DCHPRI20;
11979 __IO uint8_t DCHPRI27;
11980 __IO uint8_t DCHPRI26;
11981 __IO uint8_t DCHPRI25;
11982 __IO uint8_t DCHPRI24;
11983 __IO uint8_t DCHPRI31;
11984 __IO uint8_t DCHPRI30;
11985 __IO uint8_t DCHPRI29;
11986 __IO uint8_t DCHPRI28;
11987 };
11988 uint32_t _DCHPRI_32[8];
11989 uint8_t _DCHPRI_8[32];
11990 };
11991 uint8_t RESERVED_7[3808];
11992 struct _TCD_t { /* offset: 0x1000, array step: 0x20 */
11993 __IO uint32_t SADDR;
11994 __IO uint16_t SOFF;
11995 __IO uint16_t ATTR;
11996 union { /* offset: 0x1008, array step: 0x20 */
11997 __IO uint32_t NBYTES_MLNO;
11998 __IO uint32_t NBYTES_MLOFFNO;
11999 __IO uint32_t NBYTES_MLOFFYES;
12000 };
12001 __IO uint32_t SLAST;
12002 __IO uint32_t DADDR;
12003 __IO uint16_t DOFF;
12004 union { /* offset: 0x1016, array step: 0x20 */
12005 __IO uint16_t CITER_ELINKNO;
12006 __IO uint16_t CITER_ELINKYES;
12007 };
12008 __IO uint32_t DLAST_SGA;
12009 __IO uint16_t CSR;
12010 union { /* offset: 0x101E, array step: 0x20 */
12011 __IO uint16_t BITER_ELINKNO;
12012 __IO uint16_t BITER_ELINKYES;
12013 };
12014 } TCD[32];
12015} DMA_Type;
12016
12017/* ----------------------------------------------------------------------------
12018 -- DMA Register Masks
12019 ---------------------------------------------------------------------------- */
12020
12021/*
12022 * @addtogroup DMA_Register_Masks DMA Register Masks
12023 * @{
12024 */
12025
12026/* @name CR - Control Register */
12027/* @{ */
12028#define DMA_CR_EDBG_MASK (0x2U)
12029#define DMA_CR_EDBG_SHIFT (1U)
12030/* EDBG - Enable Debug
12031 * 0b0..When in debug mode, the DMA continues to operate.
12032 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
12033 * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
12034 */
12035#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
12036#define DMA_CR_ERCA_MASK (0x4U)
12037#define DMA_CR_ERCA_SHIFT (2U)
12038/* ERCA - Enable Round Robin Channel Arbitration
12039 * 0b0..Fixed priority arbitration is used for channel selection within each group.
12040 * 0b1..Round robin arbitration is used for channel selection within each group.
12041 */
12042#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
12043#define DMA_CR_ERGA_MASK (0x8U)
12044#define DMA_CR_ERGA_SHIFT (3U)
12045/* ERGA - Enable Round Robin Group Arbitration
12046 * 0b0..Fixed priority arbitration is used for selection among the groups.
12047 * 0b1..Round robin arbitration is used for selection among the groups.
12048 */
12049#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
12050#define DMA_CR_HOE_MASK (0x10U)
12051#define DMA_CR_HOE_SHIFT (4U)
12052/* HOE - Halt On Error
12053 * 0b0..Normal operation
12054 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
12055 */
12056#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
12057#define DMA_CR_HALT_MASK (0x20U)
12058#define DMA_CR_HALT_SHIFT (5U)
12059/* HALT - Halt DMA Operations
12060 * 0b0..Normal operation
12061 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
12062 */
12063#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
12064#define DMA_CR_CLM_MASK (0x40U)
12065#define DMA_CR_CLM_SHIFT (6U)
12066/* CLM - Continuous Link Mode
12067 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
12068 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated
12069 * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel
12070 * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the
12071 * next minor loop.
12072 */
12073#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
12074#define DMA_CR_EMLM_MASK (0x80U)
12075#define DMA_CR_EMLM_SHIFT (7U)
12076/* EMLM - Enable Minor Loop Mapping
12077 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
12078 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
12079 * field. The individual enable fields allow the minor loop offset to be applied to the source address, the
12080 * destination address, or both. The NBYTES field is reduced when either offset is enabled.
12081 */
12082#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
12083#define DMA_CR_GRP0PRI_MASK (0x100U)
12084#define DMA_CR_GRP0PRI_SHIFT (8U)
12085#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
12086#define DMA_CR_GRP1PRI_MASK (0x400U)
12087#define DMA_CR_GRP1PRI_SHIFT (10U)
12088#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
12089#define DMA_CR_ECX_MASK (0x10000U)
12090#define DMA_CR_ECX_SHIFT (16U)
12091/* ECX - Error Cancel Transfer
12092 * 0b0..Normal operation
12093 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
12094 * force the minor loop to finish. The cancel takes effect after the last write of the current read/write
12095 * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
12096 * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an
12097 * optional error interrupt.
12098 */
12099#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
12100#define DMA_CR_CX_MASK (0x20000U)
12101#define DMA_CR_CX_SHIFT (17U)
12102/* CX - Cancel Transfer
12103 * 0b0..Normal operation
12104 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
12105 * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
12106 * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
12107 */
12108#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
12109#define DMA_CR_ACTIVE_MASK (0x80000000U)
12110#define DMA_CR_ACTIVE_SHIFT (31U)
12111/* ACTIVE - DMA Active Status
12112 * 0b0..eDMA is idle.
12113 * 0b1..eDMA is executing a channel.
12114 */
12115#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
12116/* @} */
12117
12118/* @name ES - Error Status Register */
12119/* @{ */
12120#define DMA_ES_DBE_MASK (0x1U)
12121#define DMA_ES_DBE_SHIFT (0U)
12122/* DBE - Destination Bus Error
12123 * 0b0..No destination bus error
12124 * 0b1..The last recorded error was a bus error on a destination write
12125 */
12126#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
12127#define DMA_ES_SBE_MASK (0x2U)
12128#define DMA_ES_SBE_SHIFT (1U)
12129/* SBE - Source Bus Error
12130 * 0b0..No source bus error
12131 * 0b1..The last recorded error was a bus error on a source read
12132 */
12133#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
12134#define DMA_ES_SGE_MASK (0x4U)
12135#define DMA_ES_SGE_SHIFT (2U)
12136/* SGE - Scatter/Gather Configuration Error
12137 * 0b0..No scatter/gather configuration error
12138 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
12139 * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
12140 * enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
12141 */
12142#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
12143#define DMA_ES_NCE_MASK (0x8U)
12144#define DMA_ES_NCE_SHIFT (3U)
12145/* NCE - NBYTES/CITER Configuration Error
12146 * 0b0..No NBYTES/CITER configuration error
12147 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
12148 * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
12149 * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
12150 */
12151#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
12152#define DMA_ES_DOE_MASK (0x10U)
12153#define DMA_ES_DOE_SHIFT (4U)
12154/* DOE - Destination Offset Error
12155 * 0b0..No destination offset configuration error
12156 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
12157 */
12158#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
12159#define DMA_ES_DAE_MASK (0x20U)
12160#define DMA_ES_DAE_SHIFT (5U)
12161/* DAE - Destination Address Error
12162 * 0b0..No destination address configuration error
12163 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
12164 */
12165#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
12166#define DMA_ES_SOE_MASK (0x40U)
12167#define DMA_ES_SOE_SHIFT (6U)
12168/* SOE - Source Offset Error
12169 * 0b0..No source offset configuration error
12170 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
12171 */
12172#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
12173#define DMA_ES_SAE_MASK (0x80U)
12174#define DMA_ES_SAE_SHIFT (7U)
12175/* SAE - Source Address Error
12176 * 0b0..No source address configuration error.
12177 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
12178 */
12179#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
12180#define DMA_ES_ERRCHN_MASK (0x1F00U)
12181#define DMA_ES_ERRCHN_SHIFT (8U)
12182#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
12183#define DMA_ES_CPE_MASK (0x4000U)
12184#define DMA_ES_CPE_SHIFT (14U)
12185/* CPE - Channel Priority Error
12186 * 0b0..No channel priority error
12187 * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel
12188 * priorities within a group are not unique.
12189 */
12190#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
12191#define DMA_ES_GPE_MASK (0x8000U)
12192#define DMA_ES_GPE_SHIFT (15U)
12193/* GPE - Group Priority Error
12194 * 0b0..No group priority error
12195 * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
12196 */
12197#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
12198#define DMA_ES_ECX_MASK (0x10000U)
12199#define DMA_ES_ECX_SHIFT (16U)
12200/* ECX - Transfer Canceled
12201 * 0b0..No canceled transfers
12202 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
12203 */
12204#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
12205#define DMA_ES_VLD_MASK (0x80000000U)
12206#define DMA_ES_VLD_SHIFT (31U)
12207/* VLD - VLD
12208 * 0b0..No ERR bits are set.
12209 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
12210 */
12211#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
12212/* @} */
12213
12214/* @name ERQ - Enable Request Register */
12215/* @{ */
12216#define DMA_ERQ_ERQ0_MASK (0x1U)
12217#define DMA_ERQ_ERQ0_SHIFT (0U)
12218/* ERQ0 - Enable DMA Request 0
12219 * 0b0..The DMA request signal for the corresponding channel is disabled
12220 * 0b1..The DMA request signal for the corresponding channel is enabled
12221 */
12222#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
12223#define DMA_ERQ_ERQ1_MASK (0x2U)
12224#define DMA_ERQ_ERQ1_SHIFT (1U)
12225/* ERQ1 - Enable DMA Request 1
12226 * 0b0..The DMA request signal for the corresponding channel is disabled
12227 * 0b1..The DMA request signal for the corresponding channel is enabled
12228 */
12229#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
12230#define DMA_ERQ_ERQ2_MASK (0x4U)
12231#define DMA_ERQ_ERQ2_SHIFT (2U)
12232/* ERQ2 - Enable DMA Request 2
12233 * 0b0..The DMA request signal for the corresponding channel is disabled
12234 * 0b1..The DMA request signal for the corresponding channel is enabled
12235 */
12236#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
12237#define DMA_ERQ_ERQ3_MASK (0x8U)
12238#define DMA_ERQ_ERQ3_SHIFT (3U)
12239/* ERQ3 - Enable DMA Request 3
12240 * 0b0..The DMA request signal for the corresponding channel is disabled
12241 * 0b1..The DMA request signal for the corresponding channel is enabled
12242 */
12243#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
12244#define DMA_ERQ_ERQ4_MASK (0x10U)
12245#define DMA_ERQ_ERQ4_SHIFT (4U)
12246/* ERQ4 - Enable DMA Request 4
12247 * 0b0..The DMA request signal for the corresponding channel is disabled
12248 * 0b1..The DMA request signal for the corresponding channel is enabled
12249 */
12250#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
12251#define DMA_ERQ_ERQ5_MASK (0x20U)
12252#define DMA_ERQ_ERQ5_SHIFT (5U)
12253/* ERQ5 - Enable DMA Request 5
12254 * 0b0..The DMA request signal for the corresponding channel is disabled
12255 * 0b1..The DMA request signal for the corresponding channel is enabled
12256 */
12257#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
12258#define DMA_ERQ_ERQ6_MASK (0x40U)
12259#define DMA_ERQ_ERQ6_SHIFT (6U)
12260/* ERQ6 - Enable DMA Request 6
12261 * 0b0..The DMA request signal for the corresponding channel is disabled
12262 * 0b1..The DMA request signal for the corresponding channel is enabled
12263 */
12264#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
12265#define DMA_ERQ_ERQ7_MASK (0x80U)
12266#define DMA_ERQ_ERQ7_SHIFT (7U)
12267/* ERQ7 - Enable DMA Request 7
12268 * 0b0..The DMA request signal for the corresponding channel is disabled
12269 * 0b1..The DMA request signal for the corresponding channel is enabled
12270 */
12271#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
12272#define DMA_ERQ_ERQ8_MASK (0x100U)
12273#define DMA_ERQ_ERQ8_SHIFT (8U)
12274/* ERQ8 - Enable DMA Request 8
12275 * 0b0..The DMA request signal for the corresponding channel is disabled
12276 * 0b1..The DMA request signal for the corresponding channel is enabled
12277 */
12278#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
12279#define DMA_ERQ_ERQ9_MASK (0x200U)
12280#define DMA_ERQ_ERQ9_SHIFT (9U)
12281/* ERQ9 - Enable DMA Request 9
12282 * 0b0..The DMA request signal for the corresponding channel is disabled
12283 * 0b1..The DMA request signal for the corresponding channel is enabled
12284 */
12285#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
12286#define DMA_ERQ_ERQ10_MASK (0x400U)
12287#define DMA_ERQ_ERQ10_SHIFT (10U)
12288/* ERQ10 - Enable DMA Request 10
12289 * 0b0..The DMA request signal for the corresponding channel is disabled
12290 * 0b1..The DMA request signal for the corresponding channel is enabled
12291 */
12292#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
12293#define DMA_ERQ_ERQ11_MASK (0x800U)
12294#define DMA_ERQ_ERQ11_SHIFT (11U)
12295/* ERQ11 - Enable DMA Request 11
12296 * 0b0..The DMA request signal for the corresponding channel is disabled
12297 * 0b1..The DMA request signal for the corresponding channel is enabled
12298 */
12299#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
12300#define DMA_ERQ_ERQ12_MASK (0x1000U)
12301#define DMA_ERQ_ERQ12_SHIFT (12U)
12302/* ERQ12 - Enable DMA Request 12
12303 * 0b0..The DMA request signal for the corresponding channel is disabled
12304 * 0b1..The DMA request signal for the corresponding channel is enabled
12305 */
12306#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
12307#define DMA_ERQ_ERQ13_MASK (0x2000U)
12308#define DMA_ERQ_ERQ13_SHIFT (13U)
12309/* ERQ13 - Enable DMA Request 13
12310 * 0b0..The DMA request signal for the corresponding channel is disabled
12311 * 0b1..The DMA request signal for the corresponding channel is enabled
12312 */
12313#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
12314#define DMA_ERQ_ERQ14_MASK (0x4000U)
12315#define DMA_ERQ_ERQ14_SHIFT (14U)
12316/* ERQ14 - Enable DMA Request 14
12317 * 0b0..The DMA request signal for the corresponding channel is disabled
12318 * 0b1..The DMA request signal for the corresponding channel is enabled
12319 */
12320#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
12321#define DMA_ERQ_ERQ15_MASK (0x8000U)
12322#define DMA_ERQ_ERQ15_SHIFT (15U)
12323/* ERQ15 - Enable DMA Request 15
12324 * 0b0..The DMA request signal for the corresponding channel is disabled
12325 * 0b1..The DMA request signal for the corresponding channel is enabled
12326 */
12327#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
12328#define DMA_ERQ_ERQ16_MASK (0x10000U)
12329#define DMA_ERQ_ERQ16_SHIFT (16U)
12330/* ERQ16 - Enable DMA Request 16
12331 * 0b0..The DMA request signal for the corresponding channel is disabled
12332 * 0b1..The DMA request signal for the corresponding channel is enabled
12333 */
12334#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
12335#define DMA_ERQ_ERQ17_MASK (0x20000U)
12336#define DMA_ERQ_ERQ17_SHIFT (17U)
12337/* ERQ17 - Enable DMA Request 17
12338 * 0b0..The DMA request signal for the corresponding channel is disabled
12339 * 0b1..The DMA request signal for the corresponding channel is enabled
12340 */
12341#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
12342#define DMA_ERQ_ERQ18_MASK (0x40000U)
12343#define DMA_ERQ_ERQ18_SHIFT (18U)
12344/* ERQ18 - Enable DMA Request 18
12345 * 0b0..The DMA request signal for the corresponding channel is disabled
12346 * 0b1..The DMA request signal for the corresponding channel is enabled
12347 */
12348#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
12349#define DMA_ERQ_ERQ19_MASK (0x80000U)
12350#define DMA_ERQ_ERQ19_SHIFT (19U)
12351/* ERQ19 - Enable DMA Request 19
12352 * 0b0..The DMA request signal for the corresponding channel is disabled
12353 * 0b1..The DMA request signal for the corresponding channel is enabled
12354 */
12355#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
12356#define DMA_ERQ_ERQ20_MASK (0x100000U)
12357#define DMA_ERQ_ERQ20_SHIFT (20U)
12358/* ERQ20 - Enable DMA Request 20
12359 * 0b0..The DMA request signal for the corresponding channel is disabled
12360 * 0b1..The DMA request signal for the corresponding channel is enabled
12361 */
12362#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
12363#define DMA_ERQ_ERQ21_MASK (0x200000U)
12364#define DMA_ERQ_ERQ21_SHIFT (21U)
12365/* ERQ21 - Enable DMA Request 21
12366 * 0b0..The DMA request signal for the corresponding channel is disabled
12367 * 0b1..The DMA request signal for the corresponding channel is enabled
12368 */
12369#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
12370#define DMA_ERQ_ERQ22_MASK (0x400000U)
12371#define DMA_ERQ_ERQ22_SHIFT (22U)
12372/* ERQ22 - Enable DMA Request 22
12373 * 0b0..The DMA request signal for the corresponding channel is disabled
12374 * 0b1..The DMA request signal for the corresponding channel is enabled
12375 */
12376#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
12377#define DMA_ERQ_ERQ23_MASK (0x800000U)
12378#define DMA_ERQ_ERQ23_SHIFT (23U)
12379/* ERQ23 - Enable DMA Request 23
12380 * 0b0..The DMA request signal for the corresponding channel is disabled
12381 * 0b1..The DMA request signal for the corresponding channel is enabled
12382 */
12383#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
12384#define DMA_ERQ_ERQ24_MASK (0x1000000U)
12385#define DMA_ERQ_ERQ24_SHIFT (24U)
12386/* ERQ24 - Enable DMA Request 24
12387 * 0b0..The DMA request signal for the corresponding channel is disabled
12388 * 0b1..The DMA request signal for the corresponding channel is enabled
12389 */
12390#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
12391#define DMA_ERQ_ERQ25_MASK (0x2000000U)
12392#define DMA_ERQ_ERQ25_SHIFT (25U)
12393/* ERQ25 - Enable DMA Request 25
12394 * 0b0..The DMA request signal for the corresponding channel is disabled
12395 * 0b1..The DMA request signal for the corresponding channel is enabled
12396 */
12397#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
12398#define DMA_ERQ_ERQ26_MASK (0x4000000U)
12399#define DMA_ERQ_ERQ26_SHIFT (26U)
12400/* ERQ26 - Enable DMA Request 26
12401 * 0b0..The DMA request signal for the corresponding channel is disabled
12402 * 0b1..The DMA request signal for the corresponding channel is enabled
12403 */
12404#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
12405#define DMA_ERQ_ERQ27_MASK (0x8000000U)
12406#define DMA_ERQ_ERQ27_SHIFT (27U)
12407/* ERQ27 - Enable DMA Request 27
12408 * 0b0..The DMA request signal for the corresponding channel is disabled
12409 * 0b1..The DMA request signal for the corresponding channel is enabled
12410 */
12411#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
12412#define DMA_ERQ_ERQ28_MASK (0x10000000U)
12413#define DMA_ERQ_ERQ28_SHIFT (28U)
12414/* ERQ28 - Enable DMA Request 28
12415 * 0b0..The DMA request signal for the corresponding channel is disabled
12416 * 0b1..The DMA request signal for the corresponding channel is enabled
12417 */
12418#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
12419#define DMA_ERQ_ERQ29_MASK (0x20000000U)
12420#define DMA_ERQ_ERQ29_SHIFT (29U)
12421/* ERQ29 - Enable DMA Request 29
12422 * 0b0..The DMA request signal for the corresponding channel is disabled
12423 * 0b1..The DMA request signal for the corresponding channel is enabled
12424 */
12425#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
12426#define DMA_ERQ_ERQ30_MASK (0x40000000U)
12427#define DMA_ERQ_ERQ30_SHIFT (30U)
12428/* ERQ30 - Enable DMA Request 30
12429 * 0b0..The DMA request signal for the corresponding channel is disabled
12430 * 0b1..The DMA request signal for the corresponding channel is enabled
12431 */
12432#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
12433#define DMA_ERQ_ERQ31_MASK (0x80000000U)
12434#define DMA_ERQ_ERQ31_SHIFT (31U)
12435/* ERQ31 - Enable DMA Request 31
12436 * 0b0..The DMA request signal for the corresponding channel is disabled
12437 * 0b1..The DMA request signal for the corresponding channel is enabled
12438 */
12439#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
12440/* @} */
12441
12442/* @name EEI - Enable Error Interrupt Register */
12443/* @{ */
12444#define DMA_EEI_EEI0_MASK (0x1U)
12445#define DMA_EEI_EEI0_SHIFT (0U)
12446/* EEI0 - Enable Error Interrupt 0
12447 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12448 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12449 */
12450#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
12451#define DMA_EEI_EEI1_MASK (0x2U)
12452#define DMA_EEI_EEI1_SHIFT (1U)
12453/* EEI1 - Enable Error Interrupt 1
12454 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12455 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12456 */
12457#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
12458#define DMA_EEI_EEI2_MASK (0x4U)
12459#define DMA_EEI_EEI2_SHIFT (2U)
12460/* EEI2 - Enable Error Interrupt 2
12461 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12462 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12463 */
12464#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
12465#define DMA_EEI_EEI3_MASK (0x8U)
12466#define DMA_EEI_EEI3_SHIFT (3U)
12467/* EEI3 - Enable Error Interrupt 3
12468 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12469 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12470 */
12471#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
12472#define DMA_EEI_EEI4_MASK (0x10U)
12473#define DMA_EEI_EEI4_SHIFT (4U)
12474/* EEI4 - Enable Error Interrupt 4
12475 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12476 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12477 */
12478#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
12479#define DMA_EEI_EEI5_MASK (0x20U)
12480#define DMA_EEI_EEI5_SHIFT (5U)
12481/* EEI5 - Enable Error Interrupt 5
12482 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12483 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12484 */
12485#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
12486#define DMA_EEI_EEI6_MASK (0x40U)
12487#define DMA_EEI_EEI6_SHIFT (6U)
12488/* EEI6 - Enable Error Interrupt 6
12489 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12490 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12491 */
12492#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
12493#define DMA_EEI_EEI7_MASK (0x80U)
12494#define DMA_EEI_EEI7_SHIFT (7U)
12495/* EEI7 - Enable Error Interrupt 7
12496 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12497 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12498 */
12499#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
12500#define DMA_EEI_EEI8_MASK (0x100U)
12501#define DMA_EEI_EEI8_SHIFT (8U)
12502/* EEI8 - Enable Error Interrupt 8
12503 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12504 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12505 */
12506#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
12507#define DMA_EEI_EEI9_MASK (0x200U)
12508#define DMA_EEI_EEI9_SHIFT (9U)
12509/* EEI9 - Enable Error Interrupt 9
12510 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12511 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12512 */
12513#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
12514#define DMA_EEI_EEI10_MASK (0x400U)
12515#define DMA_EEI_EEI10_SHIFT (10U)
12516/* EEI10 - Enable Error Interrupt 10
12517 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12518 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12519 */
12520#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
12521#define DMA_EEI_EEI11_MASK (0x800U)
12522#define DMA_EEI_EEI11_SHIFT (11U)
12523/* EEI11 - Enable Error Interrupt 11
12524 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12525 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12526 */
12527#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
12528#define DMA_EEI_EEI12_MASK (0x1000U)
12529#define DMA_EEI_EEI12_SHIFT (12U)
12530/* EEI12 - Enable Error Interrupt 12
12531 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12532 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12533 */
12534#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
12535#define DMA_EEI_EEI13_MASK (0x2000U)
12536#define DMA_EEI_EEI13_SHIFT (13U)
12537/* EEI13 - Enable Error Interrupt 13
12538 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12539 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12540 */
12541#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
12542#define DMA_EEI_EEI14_MASK (0x4000U)
12543#define DMA_EEI_EEI14_SHIFT (14U)
12544/* EEI14 - Enable Error Interrupt 14
12545 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12546 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12547 */
12548#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
12549#define DMA_EEI_EEI15_MASK (0x8000U)
12550#define DMA_EEI_EEI15_SHIFT (15U)
12551/* EEI15 - Enable Error Interrupt 15
12552 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12553 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12554 */
12555#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
12556#define DMA_EEI_EEI16_MASK (0x10000U)
12557#define DMA_EEI_EEI16_SHIFT (16U)
12558/* EEI16 - Enable Error Interrupt 16
12559 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12560 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12561 */
12562#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
12563#define DMA_EEI_EEI17_MASK (0x20000U)
12564#define DMA_EEI_EEI17_SHIFT (17U)
12565/* EEI17 - Enable Error Interrupt 17
12566 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12567 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12568 */
12569#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
12570#define DMA_EEI_EEI18_MASK (0x40000U)
12571#define DMA_EEI_EEI18_SHIFT (18U)
12572/* EEI18 - Enable Error Interrupt 18
12573 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12574 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12575 */
12576#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
12577#define DMA_EEI_EEI19_MASK (0x80000U)
12578#define DMA_EEI_EEI19_SHIFT (19U)
12579/* EEI19 - Enable Error Interrupt 19
12580 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12581 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12582 */
12583#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
12584#define DMA_EEI_EEI20_MASK (0x100000U)
12585#define DMA_EEI_EEI20_SHIFT (20U)
12586/* EEI20 - Enable Error Interrupt 20
12587 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12588 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12589 */
12590#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
12591#define DMA_EEI_EEI21_MASK (0x200000U)
12592#define DMA_EEI_EEI21_SHIFT (21U)
12593/* EEI21 - Enable Error Interrupt 21
12594 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12595 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12596 */
12597#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
12598#define DMA_EEI_EEI22_MASK (0x400000U)
12599#define DMA_EEI_EEI22_SHIFT (22U)
12600/* EEI22 - Enable Error Interrupt 22
12601 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12602 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12603 */
12604#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
12605#define DMA_EEI_EEI23_MASK (0x800000U)
12606#define DMA_EEI_EEI23_SHIFT (23U)
12607/* EEI23 - Enable Error Interrupt 23
12608 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12609 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12610 */
12611#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
12612#define DMA_EEI_EEI24_MASK (0x1000000U)
12613#define DMA_EEI_EEI24_SHIFT (24U)
12614/* EEI24 - Enable Error Interrupt 24
12615 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12616 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12617 */
12618#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
12619#define DMA_EEI_EEI25_MASK (0x2000000U)
12620#define DMA_EEI_EEI25_SHIFT (25U)
12621/* EEI25 - Enable Error Interrupt 25
12622 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12623 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12624 */
12625#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
12626#define DMA_EEI_EEI26_MASK (0x4000000U)
12627#define DMA_EEI_EEI26_SHIFT (26U)
12628/* EEI26 - Enable Error Interrupt 26
12629 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12630 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12631 */
12632#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
12633#define DMA_EEI_EEI27_MASK (0x8000000U)
12634#define DMA_EEI_EEI27_SHIFT (27U)
12635/* EEI27 - Enable Error Interrupt 27
12636 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12637 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12638 */
12639#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
12640#define DMA_EEI_EEI28_MASK (0x10000000U)
12641#define DMA_EEI_EEI28_SHIFT (28U)
12642/* EEI28 - Enable Error Interrupt 28
12643 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12644 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12645 */
12646#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
12647#define DMA_EEI_EEI29_MASK (0x20000000U)
12648#define DMA_EEI_EEI29_SHIFT (29U)
12649/* EEI29 - Enable Error Interrupt 29
12650 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12651 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12652 */
12653#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
12654#define DMA_EEI_EEI30_MASK (0x40000000U)
12655#define DMA_EEI_EEI30_SHIFT (30U)
12656/* EEI30 - Enable Error Interrupt 30
12657 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12658 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12659 */
12660#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
12661#define DMA_EEI_EEI31_MASK (0x80000000U)
12662#define DMA_EEI_EEI31_SHIFT (31U)
12663/* EEI31 - Enable Error Interrupt 31
12664 * 0b0..The error signal for corresponding channel does not generate an error interrupt
12665 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
12666 */
12667#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
12668/* @} */
12669
12670/* @name CEEI - Clear Enable Error Interrupt Register */
12671/* @{ */
12672#define DMA_CEEI_CEEI_MASK (0x1FU)
12673#define DMA_CEEI_CEEI_SHIFT (0U)
12674#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
12675#define DMA_CEEI_CAEE_MASK (0x40U)
12676#define DMA_CEEI_CAEE_SHIFT (6U)
12677/* CAEE - Clear All Enable Error Interrupts
12678 * 0b0..Clear only the EEI bit specified in the CEEI field
12679 * 0b1..Clear all bits in EEI
12680 */
12681#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
12682#define DMA_CEEI_NOP_MASK (0x80U)
12683#define DMA_CEEI_NOP_SHIFT (7U)
12684/* NOP - No Op enable
12685 * 0b0..Normal operation
12686 * 0b1..No operation, ignore the other bits in this register
12687 */
12688#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
12689/* @} */
12690
12691/* @name SEEI - Set Enable Error Interrupt Register */
12692/* @{ */
12693#define DMA_SEEI_SEEI_MASK (0x1FU)
12694#define DMA_SEEI_SEEI_SHIFT (0U)
12695#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
12696#define DMA_SEEI_SAEE_MASK (0x40U)
12697#define DMA_SEEI_SAEE_SHIFT (6U)
12698/* SAEE - Sets All Enable Error Interrupts
12699 * 0b0..Set only the EEI bit specified in the SEEI field.
12700 * 0b1..Sets all bits in EEI
12701 */
12702#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
12703#define DMA_SEEI_NOP_MASK (0x80U)
12704#define DMA_SEEI_NOP_SHIFT (7U)
12705/* NOP - No Op enable
12706 * 0b0..Normal operation
12707 * 0b1..No operation, ignore the other bits in this register
12708 */
12709#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
12710/* @} */
12711
12712/* @name CERQ - Clear Enable Request Register */
12713/* @{ */
12714#define DMA_CERQ_CERQ_MASK (0x1FU)
12715#define DMA_CERQ_CERQ_SHIFT (0U)
12716#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
12717#define DMA_CERQ_CAER_MASK (0x40U)
12718#define DMA_CERQ_CAER_SHIFT (6U)
12719/* CAER - Clear All Enable Requests
12720 * 0b0..Clear only the ERQ bit specified in the CERQ field
12721 * 0b1..Clear all bits in ERQ
12722 */
12723#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
12724#define DMA_CERQ_NOP_MASK (0x80U)
12725#define DMA_CERQ_NOP_SHIFT (7U)
12726/* NOP - No Op enable
12727 * 0b0..Normal operation
12728 * 0b1..No operation, ignore the other bits in this register
12729 */
12730#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
12731/* @} */
12732
12733/* @name SERQ - Set Enable Request Register */
12734/* @{ */
12735#define DMA_SERQ_SERQ_MASK (0x1FU)
12736#define DMA_SERQ_SERQ_SHIFT (0U)
12737#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
12738#define DMA_SERQ_SAER_MASK (0x40U)
12739#define DMA_SERQ_SAER_SHIFT (6U)
12740/* SAER - Set All Enable Requests
12741 * 0b0..Set only the ERQ bit specified in the SERQ field
12742 * 0b1..Set all bits in ERQ
12743 */
12744#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
12745#define DMA_SERQ_NOP_MASK (0x80U)
12746#define DMA_SERQ_NOP_SHIFT (7U)
12747/* NOP - No Op enable
12748 * 0b0..Normal operation
12749 * 0b1..No operation, ignore the other bits in this register
12750 */
12751#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
12752/* @} */
12753
12754/* @name CDNE - Clear DONE Status Bit Register */
12755/* @{ */
12756#define DMA_CDNE_CDNE_MASK (0x1FU)
12757#define DMA_CDNE_CDNE_SHIFT (0U)
12758#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
12759#define DMA_CDNE_CADN_MASK (0x40U)
12760#define DMA_CDNE_CADN_SHIFT (6U)
12761/* CADN - Clears All DONE Bits
12762 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
12763 * 0b1..Clears all bits in TCDn_CSR[DONE]
12764 */
12765#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
12766#define DMA_CDNE_NOP_MASK (0x80U)
12767#define DMA_CDNE_NOP_SHIFT (7U)
12768/* NOP - No Op enable
12769 * 0b0..Normal operation
12770 * 0b1..No operation, ignore the other bits in this register
12771 */
12772#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
12773/* @} */
12774
12775/* @name SSRT - Set START Bit Register */
12776/* @{ */
12777#define DMA_SSRT_SSRT_MASK (0x1FU)
12778#define DMA_SSRT_SSRT_SHIFT (0U)
12779#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
12780#define DMA_SSRT_SAST_MASK (0x40U)
12781#define DMA_SSRT_SAST_SHIFT (6U)
12782/* SAST - Set All START Bits (activates all channels)
12783 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
12784 * 0b1..Set all bits in TCDn_CSR[START]
12785 */
12786#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
12787#define DMA_SSRT_NOP_MASK (0x80U)
12788#define DMA_SSRT_NOP_SHIFT (7U)
12789/* NOP - No Op enable
12790 * 0b0..Normal operation
12791 * 0b1..No operation, ignore the other bits in this register
12792 */
12793#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
12794/* @} */
12795
12796/* @name CERR - Clear Error Register */
12797/* @{ */
12798#define DMA_CERR_CERR_MASK (0x1FU)
12799#define DMA_CERR_CERR_SHIFT (0U)
12800#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
12801#define DMA_CERR_CAEI_MASK (0x40U)
12802#define DMA_CERR_CAEI_SHIFT (6U)
12803/* CAEI - Clear All Error Indicators
12804 * 0b0..Clear only the ERR bit specified in the CERR field
12805 * 0b1..Clear all bits in ERR
12806 */
12807#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
12808#define DMA_CERR_NOP_MASK (0x80U)
12809#define DMA_CERR_NOP_SHIFT (7U)
12810/* NOP - No Op enable
12811 * 0b0..Normal operation
12812 * 0b1..No operation, ignore the other bits in this register
12813 */
12814#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
12815/* @} */
12816
12817/* @name CINT - Clear Interrupt Request Register */
12818/* @{ */
12819#define DMA_CINT_CINT_MASK (0x1FU)
12820#define DMA_CINT_CINT_SHIFT (0U)
12821#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
12822#define DMA_CINT_CAIR_MASK (0x40U)
12823#define DMA_CINT_CAIR_SHIFT (6U)
12824/* CAIR - Clear All Interrupt Requests
12825 * 0b0..Clear only the INT bit specified in the CINT field
12826 * 0b1..Clear all bits in INT
12827 */
12828#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
12829#define DMA_CINT_NOP_MASK (0x80U)
12830#define DMA_CINT_NOP_SHIFT (7U)
12831/* NOP - No Op enable
12832 * 0b0..Normal operation
12833 * 0b1..No operation, ignore the other bits in this register
12834 */
12835#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
12836/* @} */
12837
12838/* @name INT - Interrupt Request Register */
12839/* @{ */
12840#define DMA_INT_INT0_MASK (0x1U)
12841#define DMA_INT_INT0_SHIFT (0U)
12842/* INT0 - Interrupt Request 0
12843 * 0b0..The interrupt request for corresponding channel is cleared
12844 * 0b1..The interrupt request for corresponding channel is active
12845 */
12846#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
12847#define DMA_INT_INT1_MASK (0x2U)
12848#define DMA_INT_INT1_SHIFT (1U)
12849/* INT1 - Interrupt Request 1
12850 * 0b0..The interrupt request for corresponding channel is cleared
12851 * 0b1..The interrupt request for corresponding channel is active
12852 */
12853#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
12854#define DMA_INT_INT2_MASK (0x4U)
12855#define DMA_INT_INT2_SHIFT (2U)
12856/* INT2 - Interrupt Request 2
12857 * 0b0..The interrupt request for corresponding channel is cleared
12858 * 0b1..The interrupt request for corresponding channel is active
12859 */
12860#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
12861#define DMA_INT_INT3_MASK (0x8U)
12862#define DMA_INT_INT3_SHIFT (3U)
12863/* INT3 - Interrupt Request 3
12864 * 0b0..The interrupt request for corresponding channel is cleared
12865 * 0b1..The interrupt request for corresponding channel is active
12866 */
12867#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
12868#define DMA_INT_INT4_MASK (0x10U)
12869#define DMA_INT_INT4_SHIFT (4U)
12870/* INT4 - Interrupt Request 4
12871 * 0b0..The interrupt request for corresponding channel is cleared
12872 * 0b1..The interrupt request for corresponding channel is active
12873 */
12874#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
12875#define DMA_INT_INT5_MASK (0x20U)
12876#define DMA_INT_INT5_SHIFT (5U)
12877/* INT5 - Interrupt Request 5
12878 * 0b0..The interrupt request for corresponding channel is cleared
12879 * 0b1..The interrupt request for corresponding channel is active
12880 */
12881#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
12882#define DMA_INT_INT6_MASK (0x40U)
12883#define DMA_INT_INT6_SHIFT (6U)
12884/* INT6 - Interrupt Request 6
12885 * 0b0..The interrupt request for corresponding channel is cleared
12886 * 0b1..The interrupt request for corresponding channel is active
12887 */
12888#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
12889#define DMA_INT_INT7_MASK (0x80U)
12890#define DMA_INT_INT7_SHIFT (7U)
12891/* INT7 - Interrupt Request 7
12892 * 0b0..The interrupt request for corresponding channel is cleared
12893 * 0b1..The interrupt request for corresponding channel is active
12894 */
12895#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
12896#define DMA_INT_INT8_MASK (0x100U)
12897#define DMA_INT_INT8_SHIFT (8U)
12898/* INT8 - Interrupt Request 8
12899 * 0b0..The interrupt request for corresponding channel is cleared
12900 * 0b1..The interrupt request for corresponding channel is active
12901 */
12902#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
12903#define DMA_INT_INT9_MASK (0x200U)
12904#define DMA_INT_INT9_SHIFT (9U)
12905/* INT9 - Interrupt Request 9
12906 * 0b0..The interrupt request for corresponding channel is cleared
12907 * 0b1..The interrupt request for corresponding channel is active
12908 */
12909#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
12910#define DMA_INT_INT10_MASK (0x400U)
12911#define DMA_INT_INT10_SHIFT (10U)
12912/* INT10 - Interrupt Request 10
12913 * 0b0..The interrupt request for corresponding channel is cleared
12914 * 0b1..The interrupt request for corresponding channel is active
12915 */
12916#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
12917#define DMA_INT_INT11_MASK (0x800U)
12918#define DMA_INT_INT11_SHIFT (11U)
12919/* INT11 - Interrupt Request 11
12920 * 0b0..The interrupt request for corresponding channel is cleared
12921 * 0b1..The interrupt request for corresponding channel is active
12922 */
12923#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
12924#define DMA_INT_INT12_MASK (0x1000U)
12925#define DMA_INT_INT12_SHIFT (12U)
12926/* INT12 - Interrupt Request 12
12927 * 0b0..The interrupt request for corresponding channel is cleared
12928 * 0b1..The interrupt request for corresponding channel is active
12929 */
12930#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
12931#define DMA_INT_INT13_MASK (0x2000U)
12932#define DMA_INT_INT13_SHIFT (13U)
12933/* INT13 - Interrupt Request 13
12934 * 0b0..The interrupt request for corresponding channel is cleared
12935 * 0b1..The interrupt request for corresponding channel is active
12936 */
12937#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
12938#define DMA_INT_INT14_MASK (0x4000U)
12939#define DMA_INT_INT14_SHIFT (14U)
12940/* INT14 - Interrupt Request 14
12941 * 0b0..The interrupt request for corresponding channel is cleared
12942 * 0b1..The interrupt request for corresponding channel is active
12943 */
12944#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
12945#define DMA_INT_INT15_MASK (0x8000U)
12946#define DMA_INT_INT15_SHIFT (15U)
12947/* INT15 - Interrupt Request 15
12948 * 0b0..The interrupt request for corresponding channel is cleared
12949 * 0b1..The interrupt request for corresponding channel is active
12950 */
12951#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
12952#define DMA_INT_INT16_MASK (0x10000U)
12953#define DMA_INT_INT16_SHIFT (16U)
12954/* INT16 - Interrupt Request 16
12955 * 0b0..The interrupt request for corresponding channel is cleared
12956 * 0b1..The interrupt request for corresponding channel is active
12957 */
12958#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
12959#define DMA_INT_INT17_MASK (0x20000U)
12960#define DMA_INT_INT17_SHIFT (17U)
12961/* INT17 - Interrupt Request 17
12962 * 0b0..The interrupt request for corresponding channel is cleared
12963 * 0b1..The interrupt request for corresponding channel is active
12964 */
12965#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
12966#define DMA_INT_INT18_MASK (0x40000U)
12967#define DMA_INT_INT18_SHIFT (18U)
12968/* INT18 - Interrupt Request 18
12969 * 0b0..The interrupt request for corresponding channel is cleared
12970 * 0b1..The interrupt request for corresponding channel is active
12971 */
12972#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
12973#define DMA_INT_INT19_MASK (0x80000U)
12974#define DMA_INT_INT19_SHIFT (19U)
12975/* INT19 - Interrupt Request 19
12976 * 0b0..The interrupt request for corresponding channel is cleared
12977 * 0b1..The interrupt request for corresponding channel is active
12978 */
12979#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
12980#define DMA_INT_INT20_MASK (0x100000U)
12981#define DMA_INT_INT20_SHIFT (20U)
12982/* INT20 - Interrupt Request 20
12983 * 0b0..The interrupt request for corresponding channel is cleared
12984 * 0b1..The interrupt request for corresponding channel is active
12985 */
12986#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
12987#define DMA_INT_INT21_MASK (0x200000U)
12988#define DMA_INT_INT21_SHIFT (21U)
12989/* INT21 - Interrupt Request 21
12990 * 0b0..The interrupt request for corresponding channel is cleared
12991 * 0b1..The interrupt request for corresponding channel is active
12992 */
12993#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
12994#define DMA_INT_INT22_MASK (0x400000U)
12995#define DMA_INT_INT22_SHIFT (22U)
12996/* INT22 - Interrupt Request 22
12997 * 0b0..The interrupt request for corresponding channel is cleared
12998 * 0b1..The interrupt request for corresponding channel is active
12999 */
13000#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
13001#define DMA_INT_INT23_MASK (0x800000U)
13002#define DMA_INT_INT23_SHIFT (23U)
13003/* INT23 - Interrupt Request 23
13004 * 0b0..The interrupt request for corresponding channel is cleared
13005 * 0b1..The interrupt request for corresponding channel is active
13006 */
13007#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
13008#define DMA_INT_INT24_MASK (0x1000000U)
13009#define DMA_INT_INT24_SHIFT (24U)
13010/* INT24 - Interrupt Request 24
13011 * 0b0..The interrupt request for corresponding channel is cleared
13012 * 0b1..The interrupt request for corresponding channel is active
13013 */
13014#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
13015#define DMA_INT_INT25_MASK (0x2000000U)
13016#define DMA_INT_INT25_SHIFT (25U)
13017/* INT25 - Interrupt Request 25
13018 * 0b0..The interrupt request for corresponding channel is cleared
13019 * 0b1..The interrupt request for corresponding channel is active
13020 */
13021#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
13022#define DMA_INT_INT26_MASK (0x4000000U)
13023#define DMA_INT_INT26_SHIFT (26U)
13024/* INT26 - Interrupt Request 26
13025 * 0b0..The interrupt request for corresponding channel is cleared
13026 * 0b1..The interrupt request for corresponding channel is active
13027 */
13028#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
13029#define DMA_INT_INT27_MASK (0x8000000U)
13030#define DMA_INT_INT27_SHIFT (27U)
13031/* INT27 - Interrupt Request 27
13032 * 0b0..The interrupt request for corresponding channel is cleared
13033 * 0b1..The interrupt request for corresponding channel is active
13034 */
13035#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
13036#define DMA_INT_INT28_MASK (0x10000000U)
13037#define DMA_INT_INT28_SHIFT (28U)
13038/* INT28 - Interrupt Request 28
13039 * 0b0..The interrupt request for corresponding channel is cleared
13040 * 0b1..The interrupt request for corresponding channel is active
13041 */
13042#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
13043#define DMA_INT_INT29_MASK (0x20000000U)
13044#define DMA_INT_INT29_SHIFT (29U)
13045/* INT29 - Interrupt Request 29
13046 * 0b0..The interrupt request for corresponding channel is cleared
13047 * 0b1..The interrupt request for corresponding channel is active
13048 */
13049#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
13050#define DMA_INT_INT30_MASK (0x40000000U)
13051#define DMA_INT_INT30_SHIFT (30U)
13052/* INT30 - Interrupt Request 30
13053 * 0b0..The interrupt request for corresponding channel is cleared
13054 * 0b1..The interrupt request for corresponding channel is active
13055 */
13056#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
13057#define DMA_INT_INT31_MASK (0x80000000U)
13058#define DMA_INT_INT31_SHIFT (31U)
13059/* INT31 - Interrupt Request 31
13060 * 0b0..The interrupt request for corresponding channel is cleared
13061 * 0b1..The interrupt request for corresponding channel is active
13062 */
13063#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
13064/* @} */
13065
13066/* @name ERR - Error Register */
13067/* @{ */
13068#define DMA_ERR_ERR0_MASK (0x1U)
13069#define DMA_ERR_ERR0_SHIFT (0U)
13070/* ERR0 - Error In Channel 0
13071 * 0b0..An error in this channel has not occurred
13072 * 0b1..An error in this channel has occurred
13073 */
13074#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
13075#define DMA_ERR_ERR1_MASK (0x2U)
13076#define DMA_ERR_ERR1_SHIFT (1U)
13077/* ERR1 - Error In Channel 1
13078 * 0b0..An error in this channel has not occurred
13079 * 0b1..An error in this channel has occurred
13080 */
13081#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
13082#define DMA_ERR_ERR2_MASK (0x4U)
13083#define DMA_ERR_ERR2_SHIFT (2U)
13084/* ERR2 - Error In Channel 2
13085 * 0b0..An error in this channel has not occurred
13086 * 0b1..An error in this channel has occurred
13087 */
13088#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
13089#define DMA_ERR_ERR3_MASK (0x8U)
13090#define DMA_ERR_ERR3_SHIFT (3U)
13091/* ERR3 - Error In Channel 3
13092 * 0b0..An error in this channel has not occurred
13093 * 0b1..An error in this channel has occurred
13094 */
13095#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
13096#define DMA_ERR_ERR4_MASK (0x10U)
13097#define DMA_ERR_ERR4_SHIFT (4U)
13098/* ERR4 - Error In Channel 4
13099 * 0b0..An error in this channel has not occurred
13100 * 0b1..An error in this channel has occurred
13101 */
13102#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
13103#define DMA_ERR_ERR5_MASK (0x20U)
13104#define DMA_ERR_ERR5_SHIFT (5U)
13105/* ERR5 - Error In Channel 5
13106 * 0b0..An error in this channel has not occurred
13107 * 0b1..An error in this channel has occurred
13108 */
13109#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
13110#define DMA_ERR_ERR6_MASK (0x40U)
13111#define DMA_ERR_ERR6_SHIFT (6U)
13112/* ERR6 - Error In Channel 6
13113 * 0b0..An error in this channel has not occurred
13114 * 0b1..An error in this channel has occurred
13115 */
13116#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
13117#define DMA_ERR_ERR7_MASK (0x80U)
13118#define DMA_ERR_ERR7_SHIFT (7U)
13119/* ERR7 - Error In Channel 7
13120 * 0b0..An error in this channel has not occurred
13121 * 0b1..An error in this channel has occurred
13122 */
13123#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
13124#define DMA_ERR_ERR8_MASK (0x100U)
13125#define DMA_ERR_ERR8_SHIFT (8U)
13126/* ERR8 - Error In Channel 8
13127 * 0b0..An error in this channel has not occurred
13128 * 0b1..An error in this channel has occurred
13129 */
13130#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
13131#define DMA_ERR_ERR9_MASK (0x200U)
13132#define DMA_ERR_ERR9_SHIFT (9U)
13133/* ERR9 - Error In Channel 9
13134 * 0b0..An error in this channel has not occurred
13135 * 0b1..An error in this channel has occurred
13136 */
13137#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
13138#define DMA_ERR_ERR10_MASK (0x400U)
13139#define DMA_ERR_ERR10_SHIFT (10U)
13140/* ERR10 - Error In Channel 10
13141 * 0b0..An error in this channel has not occurred
13142 * 0b1..An error in this channel has occurred
13143 */
13144#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
13145#define DMA_ERR_ERR11_MASK (0x800U)
13146#define DMA_ERR_ERR11_SHIFT (11U)
13147/* ERR11 - Error In Channel 11
13148 * 0b0..An error in this channel has not occurred
13149 * 0b1..An error in this channel has occurred
13150 */
13151#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
13152#define DMA_ERR_ERR12_MASK (0x1000U)
13153#define DMA_ERR_ERR12_SHIFT (12U)
13154/* ERR12 - Error In Channel 12
13155 * 0b0..An error in this channel has not occurred
13156 * 0b1..An error in this channel has occurred
13157 */
13158#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
13159#define DMA_ERR_ERR13_MASK (0x2000U)
13160#define DMA_ERR_ERR13_SHIFT (13U)
13161/* ERR13 - Error In Channel 13
13162 * 0b0..An error in this channel has not occurred
13163 * 0b1..An error in this channel has occurred
13164 */
13165#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
13166#define DMA_ERR_ERR14_MASK (0x4000U)
13167#define DMA_ERR_ERR14_SHIFT (14U)
13168/* ERR14 - Error In Channel 14
13169 * 0b0..An error in this channel has not occurred
13170 * 0b1..An error in this channel has occurred
13171 */
13172#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
13173#define DMA_ERR_ERR15_MASK (0x8000U)
13174#define DMA_ERR_ERR15_SHIFT (15U)
13175/* ERR15 - Error In Channel 15
13176 * 0b0..An error in this channel has not occurred
13177 * 0b1..An error in this channel has occurred
13178 */
13179#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
13180#define DMA_ERR_ERR16_MASK (0x10000U)
13181#define DMA_ERR_ERR16_SHIFT (16U)
13182/* ERR16 - Error In Channel 16
13183 * 0b0..An error in this channel has not occurred
13184 * 0b1..An error in this channel has occurred
13185 */
13186#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
13187#define DMA_ERR_ERR17_MASK (0x20000U)
13188#define DMA_ERR_ERR17_SHIFT (17U)
13189/* ERR17 - Error In Channel 17
13190 * 0b0..An error in this channel has not occurred
13191 * 0b1..An error in this channel has occurred
13192 */
13193#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
13194#define DMA_ERR_ERR18_MASK (0x40000U)
13195#define DMA_ERR_ERR18_SHIFT (18U)
13196/* ERR18 - Error In Channel 18
13197 * 0b0..An error in this channel has not occurred
13198 * 0b1..An error in this channel has occurred
13199 */
13200#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
13201#define DMA_ERR_ERR19_MASK (0x80000U)
13202#define DMA_ERR_ERR19_SHIFT (19U)
13203/* ERR19 - Error In Channel 19
13204 * 0b0..An error in this channel has not occurred
13205 * 0b1..An error in this channel has occurred
13206 */
13207#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
13208#define DMA_ERR_ERR20_MASK (0x100000U)
13209#define DMA_ERR_ERR20_SHIFT (20U)
13210/* ERR20 - Error In Channel 20
13211 * 0b0..An error in this channel has not occurred
13212 * 0b1..An error in this channel has occurred
13213 */
13214#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
13215#define DMA_ERR_ERR21_MASK (0x200000U)
13216#define DMA_ERR_ERR21_SHIFT (21U)
13217/* ERR21 - Error In Channel 21
13218 * 0b0..An error in this channel has not occurred
13219 * 0b1..An error in this channel has occurred
13220 */
13221#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
13222#define DMA_ERR_ERR22_MASK (0x400000U)
13223#define DMA_ERR_ERR22_SHIFT (22U)
13224/* ERR22 - Error In Channel 22
13225 * 0b0..An error in this channel has not occurred
13226 * 0b1..An error in this channel has occurred
13227 */
13228#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
13229#define DMA_ERR_ERR23_MASK (0x800000U)
13230#define DMA_ERR_ERR23_SHIFT (23U)
13231/* ERR23 - Error In Channel 23
13232 * 0b0..An error in this channel has not occurred
13233 * 0b1..An error in this channel has occurred
13234 */
13235#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
13236#define DMA_ERR_ERR24_MASK (0x1000000U)
13237#define DMA_ERR_ERR24_SHIFT (24U)
13238/* ERR24 - Error In Channel 24
13239 * 0b0..An error in this channel has not occurred
13240 * 0b1..An error in this channel has occurred
13241 */
13242#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
13243#define DMA_ERR_ERR25_MASK (0x2000000U)
13244#define DMA_ERR_ERR25_SHIFT (25U)
13245/* ERR25 - Error In Channel 25
13246 * 0b0..An error in this channel has not occurred
13247 * 0b1..An error in this channel has occurred
13248 */
13249#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
13250#define DMA_ERR_ERR26_MASK (0x4000000U)
13251#define DMA_ERR_ERR26_SHIFT (26U)
13252/* ERR26 - Error In Channel 26
13253 * 0b0..An error in this channel has not occurred
13254 * 0b1..An error in this channel has occurred
13255 */
13256#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
13257#define DMA_ERR_ERR27_MASK (0x8000000U)
13258#define DMA_ERR_ERR27_SHIFT (27U)
13259/* ERR27 - Error In Channel 27
13260 * 0b0..An error in this channel has not occurred
13261 * 0b1..An error in this channel has occurred
13262 */
13263#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
13264#define DMA_ERR_ERR28_MASK (0x10000000U)
13265#define DMA_ERR_ERR28_SHIFT (28U)
13266/* ERR28 - Error In Channel 28
13267 * 0b0..An error in this channel has not occurred
13268 * 0b1..An error in this channel has occurred
13269 */
13270#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
13271#define DMA_ERR_ERR29_MASK (0x20000000U)
13272#define DMA_ERR_ERR29_SHIFT (29U)
13273/* ERR29 - Error In Channel 29
13274 * 0b0..An error in this channel has not occurred
13275 * 0b1..An error in this channel has occurred
13276 */
13277#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
13278#define DMA_ERR_ERR30_MASK (0x40000000U)
13279#define DMA_ERR_ERR30_SHIFT (30U)
13280/* ERR30 - Error In Channel 30
13281 * 0b0..An error in this channel has not occurred
13282 * 0b1..An error in this channel has occurred
13283 */
13284#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
13285#define DMA_ERR_ERR31_MASK (0x80000000U)
13286#define DMA_ERR_ERR31_SHIFT (31U)
13287/* ERR31 - Error In Channel 31
13288 * 0b0..An error in this channel has not occurred
13289 * 0b1..An error in this channel has occurred
13290 */
13291#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
13292/* @} */
13293
13294/* @name HRS - Hardware Request Status Register */
13295/* @{ */
13296#define DMA_HRS_HRS0_MASK (0x1U)
13297#define DMA_HRS_HRS0_SHIFT (0U)
13298/* HRS0 - Hardware Request Status Channel 0
13299 * 0b0..A hardware service request for channel 0 is not present
13300 * 0b1..A hardware service request for channel 0 is present
13301 */
13302#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
13303#define DMA_HRS_HRS1_MASK (0x2U)
13304#define DMA_HRS_HRS1_SHIFT (1U)
13305/* HRS1 - Hardware Request Status Channel 1
13306 * 0b0..A hardware service request for channel 1 is not present
13307 * 0b1..A hardware service request for channel 1 is present
13308 */
13309#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
13310#define DMA_HRS_HRS2_MASK (0x4U)
13311#define DMA_HRS_HRS2_SHIFT (2U)
13312/* HRS2 - Hardware Request Status Channel 2
13313 * 0b0..A hardware service request for channel 2 is not present
13314 * 0b1..A hardware service request for channel 2 is present
13315 */
13316#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
13317#define DMA_HRS_HRS3_MASK (0x8U)
13318#define DMA_HRS_HRS3_SHIFT (3U)
13319/* HRS3 - Hardware Request Status Channel 3
13320 * 0b0..A hardware service request for channel 3 is not present
13321 * 0b1..A hardware service request for channel 3 is present
13322 */
13323#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
13324#define DMA_HRS_HRS4_MASK (0x10U)
13325#define DMA_HRS_HRS4_SHIFT (4U)
13326/* HRS4 - Hardware Request Status Channel 4
13327 * 0b0..A hardware service request for channel 4 is not present
13328 * 0b1..A hardware service request for channel 4 is present
13329 */
13330#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
13331#define DMA_HRS_HRS5_MASK (0x20U)
13332#define DMA_HRS_HRS5_SHIFT (5U)
13333/* HRS5 - Hardware Request Status Channel 5
13334 * 0b0..A hardware service request for channel 5 is not present
13335 * 0b1..A hardware service request for channel 5 is present
13336 */
13337#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
13338#define DMA_HRS_HRS6_MASK (0x40U)
13339#define DMA_HRS_HRS6_SHIFT (6U)
13340/* HRS6 - Hardware Request Status Channel 6
13341 * 0b0..A hardware service request for channel 6 is not present
13342 * 0b1..A hardware service request for channel 6 is present
13343 */
13344#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
13345#define DMA_HRS_HRS7_MASK (0x80U)
13346#define DMA_HRS_HRS7_SHIFT (7U)
13347/* HRS7 - Hardware Request Status Channel 7
13348 * 0b0..A hardware service request for channel 7 is not present
13349 * 0b1..A hardware service request for channel 7 is present
13350 */
13351#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
13352#define DMA_HRS_HRS8_MASK (0x100U)
13353#define DMA_HRS_HRS8_SHIFT (8U)
13354/* HRS8 - Hardware Request Status Channel 8
13355 * 0b0..A hardware service request for channel 8 is not present
13356 * 0b1..A hardware service request for channel 8 is present
13357 */
13358#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
13359#define DMA_HRS_HRS9_MASK (0x200U)
13360#define DMA_HRS_HRS9_SHIFT (9U)
13361/* HRS9 - Hardware Request Status Channel 9
13362 * 0b0..A hardware service request for channel 9 is not present
13363 * 0b1..A hardware service request for channel 9 is present
13364 */
13365#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
13366#define DMA_HRS_HRS10_MASK (0x400U)
13367#define DMA_HRS_HRS10_SHIFT (10U)
13368/* HRS10 - Hardware Request Status Channel 10
13369 * 0b0..A hardware service request for channel 10 is not present
13370 * 0b1..A hardware service request for channel 10 is present
13371 */
13372#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
13373#define DMA_HRS_HRS11_MASK (0x800U)
13374#define DMA_HRS_HRS11_SHIFT (11U)
13375/* HRS11 - Hardware Request Status Channel 11
13376 * 0b0..A hardware service request for channel 11 is not present
13377 * 0b1..A hardware service request for channel 11 is present
13378 */
13379#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
13380#define DMA_HRS_HRS12_MASK (0x1000U)
13381#define DMA_HRS_HRS12_SHIFT (12U)
13382/* HRS12 - Hardware Request Status Channel 12
13383 * 0b0..A hardware service request for channel 12 is not present
13384 * 0b1..A hardware service request for channel 12 is present
13385 */
13386#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
13387#define DMA_HRS_HRS13_MASK (0x2000U)
13388#define DMA_HRS_HRS13_SHIFT (13U)
13389/* HRS13 - Hardware Request Status Channel 13
13390 * 0b0..A hardware service request for channel 13 is not present
13391 * 0b1..A hardware service request for channel 13 is present
13392 */
13393#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
13394#define DMA_HRS_HRS14_MASK (0x4000U)
13395#define DMA_HRS_HRS14_SHIFT (14U)
13396/* HRS14 - Hardware Request Status Channel 14
13397 * 0b0..A hardware service request for channel 14 is not present
13398 * 0b1..A hardware service request for channel 14 is present
13399 */
13400#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
13401#define DMA_HRS_HRS15_MASK (0x8000U)
13402#define DMA_HRS_HRS15_SHIFT (15U)
13403/* HRS15 - Hardware Request Status Channel 15
13404 * 0b0..A hardware service request for channel 15 is not present
13405 * 0b1..A hardware service request for channel 15 is present
13406 */
13407#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
13408#define DMA_HRS_HRS16_MASK (0x10000U)
13409#define DMA_HRS_HRS16_SHIFT (16U)
13410/* HRS16 - Hardware Request Status Channel 16
13411 * 0b0..A hardware service request for channel 16 is not present
13412 * 0b1..A hardware service request for channel 16 is present
13413 */
13414#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
13415#define DMA_HRS_HRS17_MASK (0x20000U)
13416#define DMA_HRS_HRS17_SHIFT (17U)
13417/* HRS17 - Hardware Request Status Channel 17
13418 * 0b0..A hardware service request for channel 17 is not present
13419 * 0b1..A hardware service request for channel 17 is present
13420 */
13421#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
13422#define DMA_HRS_HRS18_MASK (0x40000U)
13423#define DMA_HRS_HRS18_SHIFT (18U)
13424/* HRS18 - Hardware Request Status Channel 18
13425 * 0b0..A hardware service request for channel 18 is not present
13426 * 0b1..A hardware service request for channel 18 is present
13427 */
13428#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
13429#define DMA_HRS_HRS19_MASK (0x80000U)
13430#define DMA_HRS_HRS19_SHIFT (19U)
13431/* HRS19 - Hardware Request Status Channel 19
13432 * 0b0..A hardware service request for channel 19 is not present
13433 * 0b1..A hardware service request for channel 19 is present
13434 */
13435#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
13436#define DMA_HRS_HRS20_MASK (0x100000U)
13437#define DMA_HRS_HRS20_SHIFT (20U)
13438/* HRS20 - Hardware Request Status Channel 20
13439 * 0b0..A hardware service request for channel 20 is not present
13440 * 0b1..A hardware service request for channel 20 is present
13441 */
13442#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
13443#define DMA_HRS_HRS21_MASK (0x200000U)
13444#define DMA_HRS_HRS21_SHIFT (21U)
13445/* HRS21 - Hardware Request Status Channel 21
13446 * 0b0..A hardware service request for channel 21 is not present
13447 * 0b1..A hardware service request for channel 21 is present
13448 */
13449#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
13450#define DMA_HRS_HRS22_MASK (0x400000U)
13451#define DMA_HRS_HRS22_SHIFT (22U)
13452/* HRS22 - Hardware Request Status Channel 22
13453 * 0b0..A hardware service request for channel 22 is not present
13454 * 0b1..A hardware service request for channel 22 is present
13455 */
13456#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
13457#define DMA_HRS_HRS23_MASK (0x800000U)
13458#define DMA_HRS_HRS23_SHIFT (23U)
13459/* HRS23 - Hardware Request Status Channel 23
13460 * 0b0..A hardware service request for channel 23 is not present
13461 * 0b1..A hardware service request for channel 23 is present
13462 */
13463#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
13464#define DMA_HRS_HRS24_MASK (0x1000000U)
13465#define DMA_HRS_HRS24_SHIFT (24U)
13466/* HRS24 - Hardware Request Status Channel 24
13467 * 0b0..A hardware service request for channel 24 is not present
13468 * 0b1..A hardware service request for channel 24 is present
13469 */
13470#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
13471#define DMA_HRS_HRS25_MASK (0x2000000U)
13472#define DMA_HRS_HRS25_SHIFT (25U)
13473/* HRS25 - Hardware Request Status Channel 25
13474 * 0b0..A hardware service request for channel 25 is not present
13475 * 0b1..A hardware service request for channel 25 is present
13476 */
13477#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
13478#define DMA_HRS_HRS26_MASK (0x4000000U)
13479#define DMA_HRS_HRS26_SHIFT (26U)
13480/* HRS26 - Hardware Request Status Channel 26
13481 * 0b0..A hardware service request for channel 26 is not present
13482 * 0b1..A hardware service request for channel 26 is present
13483 */
13484#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
13485#define DMA_HRS_HRS27_MASK (0x8000000U)
13486#define DMA_HRS_HRS27_SHIFT (27U)
13487/* HRS27 - Hardware Request Status Channel 27
13488 * 0b0..A hardware service request for channel 27 is not present
13489 * 0b1..A hardware service request for channel 27 is present
13490 */
13491#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
13492#define DMA_HRS_HRS28_MASK (0x10000000U)
13493#define DMA_HRS_HRS28_SHIFT (28U)
13494/* HRS28 - Hardware Request Status Channel 28
13495 * 0b0..A hardware service request for channel 28 is not present
13496 * 0b1..A hardware service request for channel 28 is present
13497 */
13498#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
13499#define DMA_HRS_HRS29_MASK (0x20000000U)
13500#define DMA_HRS_HRS29_SHIFT (29U)
13501/* HRS29 - Hardware Request Status Channel 29
13502 * 0b0..A hardware service request for channel 29 is not preset
13503 * 0b1..A hardware service request for channel 29 is present
13504 */
13505#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
13506#define DMA_HRS_HRS30_MASK (0x40000000U)
13507#define DMA_HRS_HRS30_SHIFT (30U)
13508/* HRS30 - Hardware Request Status Channel 30
13509 * 0b0..A hardware service request for channel 30 is not present
13510 * 0b1..A hardware service request for channel 30 is present
13511 */
13512#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
13513#define DMA_HRS_HRS31_MASK (0x80000000U)
13514#define DMA_HRS_HRS31_SHIFT (31U)
13515/* HRS31 - Hardware Request Status Channel 31
13516 * 0b0..A hardware service request for channel 31 is not present
13517 * 0b1..A hardware service request for channel 31 is present
13518 */
13519#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
13520/* @} */
13521
13522/* @name EARS - Enable Asynchronous Request in Stop Register */
13523/* @{ */
13524#define DMA_EARS_EDREQ_0_MASK (0x1U)
13525#define DMA_EARS_EDREQ_0_SHIFT (0U)
13526/* EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
13527 * 0b0..Disable asynchronous DMA request for channel 0.
13528 * 0b1..Enable asynchronous DMA request for channel 0.
13529 */
13530#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
13531#define DMA_EARS_EDREQ_1_MASK (0x2U)
13532#define DMA_EARS_EDREQ_1_SHIFT (1U)
13533/* EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
13534 * 0b0..Disable asynchronous DMA request for channel 1
13535 * 0b1..Enable asynchronous DMA request for channel 1.
13536 */
13537#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
13538#define DMA_EARS_EDREQ_2_MASK (0x4U)
13539#define DMA_EARS_EDREQ_2_SHIFT (2U)
13540/* EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
13541 * 0b0..Disable asynchronous DMA request for channel 2.
13542 * 0b1..Enable asynchronous DMA request for channel 2.
13543 */
13544#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
13545#define DMA_EARS_EDREQ_3_MASK (0x8U)
13546#define DMA_EARS_EDREQ_3_SHIFT (3U)
13547/* EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
13548 * 0b0..Disable asynchronous DMA request for channel 3.
13549 * 0b1..Enable asynchronous DMA request for channel 3.
13550 */
13551#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
13552#define DMA_EARS_EDREQ_4_MASK (0x10U)
13553#define DMA_EARS_EDREQ_4_SHIFT (4U)
13554/* EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
13555 * 0b0..Disable asynchronous DMA request for channel 4.
13556 * 0b1..Enable asynchronous DMA request for channel 4.
13557 */
13558#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
13559#define DMA_EARS_EDREQ_5_MASK (0x20U)
13560#define DMA_EARS_EDREQ_5_SHIFT (5U)
13561/* EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
13562 * 0b0..Disable asynchronous DMA request for channel 5.
13563 * 0b1..Enable asynchronous DMA request for channel 5.
13564 */
13565#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
13566#define DMA_EARS_EDREQ_6_MASK (0x40U)
13567#define DMA_EARS_EDREQ_6_SHIFT (6U)
13568/* EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
13569 * 0b0..Disable asynchronous DMA request for channel 6.
13570 * 0b1..Enable asynchronous DMA request for channel 6.
13571 */
13572#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
13573#define DMA_EARS_EDREQ_7_MASK (0x80U)
13574#define DMA_EARS_EDREQ_7_SHIFT (7U)
13575/* EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
13576 * 0b0..Disable asynchronous DMA request for channel 7.
13577 * 0b1..Enable asynchronous DMA request for channel 7.
13578 */
13579#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
13580#define DMA_EARS_EDREQ_8_MASK (0x100U)
13581#define DMA_EARS_EDREQ_8_SHIFT (8U)
13582/* EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
13583 * 0b0..Disable asynchronous DMA request for channel 8.
13584 * 0b1..Enable asynchronous DMA request for channel 8.
13585 */
13586#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
13587#define DMA_EARS_EDREQ_9_MASK (0x200U)
13588#define DMA_EARS_EDREQ_9_SHIFT (9U)
13589/* EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
13590 * 0b0..Disable asynchronous DMA request for channel 9.
13591 * 0b1..Enable asynchronous DMA request for channel 9.
13592 */
13593#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
13594#define DMA_EARS_EDREQ_10_MASK (0x400U)
13595#define DMA_EARS_EDREQ_10_SHIFT (10U)
13596/* EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
13597 * 0b0..Disable asynchronous DMA request for channel 10.
13598 * 0b1..Enable asynchronous DMA request for channel 10.
13599 */
13600#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
13601#define DMA_EARS_EDREQ_11_MASK (0x800U)
13602#define DMA_EARS_EDREQ_11_SHIFT (11U)
13603/* EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
13604 * 0b0..Disable asynchronous DMA request for channel 11.
13605 * 0b1..Enable asynchronous DMA request for channel 11.
13606 */
13607#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
13608#define DMA_EARS_EDREQ_12_MASK (0x1000U)
13609#define DMA_EARS_EDREQ_12_SHIFT (12U)
13610/* EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
13611 * 0b0..Disable asynchronous DMA request for channel 12.
13612 * 0b1..Enable asynchronous DMA request for channel 12.
13613 */
13614#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
13615#define DMA_EARS_EDREQ_13_MASK (0x2000U)
13616#define DMA_EARS_EDREQ_13_SHIFT (13U)
13617/* EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
13618 * 0b0..Disable asynchronous DMA request for channel 13.
13619 * 0b1..Enable asynchronous DMA request for channel 13.
13620 */
13621#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
13622#define DMA_EARS_EDREQ_14_MASK (0x4000U)
13623#define DMA_EARS_EDREQ_14_SHIFT (14U)
13624/* EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
13625 * 0b0..Disable asynchronous DMA request for channel 14.
13626 * 0b1..Enable asynchronous DMA request for channel 14.
13627 */
13628#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
13629#define DMA_EARS_EDREQ_15_MASK (0x8000U)
13630#define DMA_EARS_EDREQ_15_SHIFT (15U)
13631/* EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
13632 * 0b0..Disable asynchronous DMA request for channel 15.
13633 * 0b1..Enable asynchronous DMA request for channel 15.
13634 */
13635#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
13636#define DMA_EARS_EDREQ_16_MASK (0x10000U)
13637#define DMA_EARS_EDREQ_16_SHIFT (16U)
13638/* EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16
13639 * 0b0..Disable asynchronous DMA request for channel 16
13640 * 0b1..Enable asynchronous DMA request for channel 16
13641 */
13642#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
13643#define DMA_EARS_EDREQ_17_MASK (0x20000U)
13644#define DMA_EARS_EDREQ_17_SHIFT (17U)
13645/* EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17
13646 * 0b0..Disable asynchronous DMA request for channel 17
13647 * 0b1..Enable asynchronous DMA request for channel 17
13648 */
13649#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
13650#define DMA_EARS_EDREQ_18_MASK (0x40000U)
13651#define DMA_EARS_EDREQ_18_SHIFT (18U)
13652/* EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18
13653 * 0b0..Disable asynchronous DMA request for channel 18
13654 * 0b1..Enable asynchronous DMA request for channel 18
13655 */
13656#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
13657#define DMA_EARS_EDREQ_19_MASK (0x80000U)
13658#define DMA_EARS_EDREQ_19_SHIFT (19U)
13659/* EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19
13660 * 0b0..Disable asynchronous DMA request for channel 19
13661 * 0b1..Enable asynchronous DMA request for channel 19
13662 */
13663#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
13664#define DMA_EARS_EDREQ_20_MASK (0x100000U)
13665#define DMA_EARS_EDREQ_20_SHIFT (20U)
13666/* EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20
13667 * 0b0..Disable asynchronous DMA request for channel 20
13668 * 0b1..Enable asynchronous DMA request for channel 20
13669 */
13670#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
13671#define DMA_EARS_EDREQ_21_MASK (0x200000U)
13672#define DMA_EARS_EDREQ_21_SHIFT (21U)
13673/* EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21
13674 * 0b0..Disable asynchronous DMA request for channel 21
13675 * 0b1..Enable asynchronous DMA request for channel 21
13676 */
13677#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
13678#define DMA_EARS_EDREQ_22_MASK (0x400000U)
13679#define DMA_EARS_EDREQ_22_SHIFT (22U)
13680/* EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22
13681 * 0b0..Disable asynchronous DMA request for channel 22
13682 * 0b1..Enable asynchronous DMA request for channel 22
13683 */
13684#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
13685#define DMA_EARS_EDREQ_23_MASK (0x800000U)
13686#define DMA_EARS_EDREQ_23_SHIFT (23U)
13687/* EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23
13688 * 0b0..Disable asynchronous DMA request for channel 23
13689 * 0b1..Enable asynchronous DMA request for channel 23
13690 */
13691#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
13692#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
13693#define DMA_EARS_EDREQ_24_SHIFT (24U)
13694/* EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24
13695 * 0b0..Disable asynchronous DMA request for channel 24
13696 * 0b1..Enable asynchronous DMA request for channel 24
13697 */
13698#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
13699#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
13700#define DMA_EARS_EDREQ_25_SHIFT (25U)
13701/* EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25
13702 * 0b0..Disable asynchronous DMA request for channel 25
13703 * 0b1..Enable asynchronous DMA request for channel 25
13704 */
13705#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
13706#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
13707#define DMA_EARS_EDREQ_26_SHIFT (26U)
13708/* EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26
13709 * 0b0..Disable asynchronous DMA request for channel 26
13710 * 0b1..Enable asynchronous DMA request for channel 26
13711 */
13712#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
13713#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
13714#define DMA_EARS_EDREQ_27_SHIFT (27U)
13715/* EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27
13716 * 0b0..Disable asynchronous DMA request for channel 27
13717 * 0b1..Enable asynchronous DMA request for channel 27
13718 */
13719#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
13720#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
13721#define DMA_EARS_EDREQ_28_SHIFT (28U)
13722/* EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28
13723 * 0b0..Disable asynchronous DMA request for channel 28
13724 * 0b1..Enable asynchronous DMA request for channel 28
13725 */
13726#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
13727#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
13728#define DMA_EARS_EDREQ_29_SHIFT (29U)
13729/* EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29
13730 * 0b0..Disable asynchronous DMA request for channel 29
13731 * 0b1..Enable asynchronous DMA request for channel 29
13732 */
13733#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
13734#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
13735#define DMA_EARS_EDREQ_30_SHIFT (30U)
13736/* EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30
13737 * 0b0..Disable asynchronous DMA request for channel 30
13738 * 0b1..Enable asynchronous DMA request for channel 30
13739 */
13740#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
13741#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
13742#define DMA_EARS_EDREQ_31_SHIFT (31U)
13743/* EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31
13744 * 0b0..Disable asynchronous DMA request for channel 31
13745 * 0b1..Enable asynchronous DMA request for channel 31
13746 */
13747#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
13748/* @} */
13749
13750/* @name DCHPRI3 - Channel n Priority Register */
13751/* @{ */
13752#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
13753#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
13754#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
13755#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
13756#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
13757#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
13758#define DMA_DCHPRI3_DPA_MASK (0x40U)
13759#define DMA_DCHPRI3_DPA_SHIFT (6U)
13760/* DPA - Disable Preempt Ability. This field resets to 0.
13761 * 0b0..Channel n can suspend a lower priority channel.
13762 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13763 */
13764#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
13765#define DMA_DCHPRI3_ECP_MASK (0x80U)
13766#define DMA_DCHPRI3_ECP_SHIFT (7U)
13767/* ECP - Enable Channel Preemption. This field resets to 0.
13768 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13769 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13770 */
13771#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
13772/* @} */
13773
13774/* @name DCHPRI2 - Channel n Priority Register */
13775/* @{ */
13776#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
13777#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
13778#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
13779#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
13780#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
13781#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
13782#define DMA_DCHPRI2_DPA_MASK (0x40U)
13783#define DMA_DCHPRI2_DPA_SHIFT (6U)
13784/* DPA - Disable Preempt Ability. This field resets to 0.
13785 * 0b0..Channel n can suspend a lower priority channel.
13786 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13787 */
13788#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
13789#define DMA_DCHPRI2_ECP_MASK (0x80U)
13790#define DMA_DCHPRI2_ECP_SHIFT (7U)
13791/* ECP - Enable Channel Preemption. This field resets to 0.
13792 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13793 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13794 */
13795#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
13796/* @} */
13797
13798/* @name DCHPRI1 - Channel n Priority Register */
13799/* @{ */
13800#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
13801#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
13802#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
13803#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
13804#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
13805#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
13806#define DMA_DCHPRI1_DPA_MASK (0x40U)
13807#define DMA_DCHPRI1_DPA_SHIFT (6U)
13808/* DPA - Disable Preempt Ability. This field resets to 0.
13809 * 0b0..Channel n can suspend a lower priority channel.
13810 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13811 */
13812#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
13813#define DMA_DCHPRI1_ECP_MASK (0x80U)
13814#define DMA_DCHPRI1_ECP_SHIFT (7U)
13815/* ECP - Enable Channel Preemption. This field resets to 0.
13816 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13817 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13818 */
13819#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
13820/* @} */
13821
13822/* @name DCHPRI0 - Channel n Priority Register */
13823/* @{ */
13824#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
13825#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
13826#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
13827#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
13828#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
13829#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
13830#define DMA_DCHPRI0_DPA_MASK (0x40U)
13831#define DMA_DCHPRI0_DPA_SHIFT (6U)
13832/* DPA - Disable Preempt Ability. This field resets to 0.
13833 * 0b0..Channel n can suspend a lower priority channel.
13834 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13835 */
13836#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
13837#define DMA_DCHPRI0_ECP_MASK (0x80U)
13838#define DMA_DCHPRI0_ECP_SHIFT (7U)
13839/* ECP - Enable Channel Preemption. This field resets to 0.
13840 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13841 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13842 */
13843#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
13844/* @} */
13845
13846/* @name DCHPRI7 - Channel n Priority Register */
13847/* @{ */
13848#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
13849#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
13850#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
13851#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
13852#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
13853#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
13854#define DMA_DCHPRI7_DPA_MASK (0x40U)
13855#define DMA_DCHPRI7_DPA_SHIFT (6U)
13856/* DPA - Disable Preempt Ability. This field resets to 0.
13857 * 0b0..Channel n can suspend a lower priority channel.
13858 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13859 */
13860#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
13861#define DMA_DCHPRI7_ECP_MASK (0x80U)
13862#define DMA_DCHPRI7_ECP_SHIFT (7U)
13863/* ECP - Enable Channel Preemption. This field resets to 0.
13864 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13865 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13866 */
13867#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
13868/* @} */
13869
13870/* @name DCHPRI6 - Channel n Priority Register */
13871/* @{ */
13872#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
13873#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
13874#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
13875#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
13876#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
13877#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
13878#define DMA_DCHPRI6_DPA_MASK (0x40U)
13879#define DMA_DCHPRI6_DPA_SHIFT (6U)
13880/* DPA - Disable Preempt Ability. This field resets to 0.
13881 * 0b0..Channel n can suspend a lower priority channel.
13882 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13883 */
13884#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
13885#define DMA_DCHPRI6_ECP_MASK (0x80U)
13886#define DMA_DCHPRI6_ECP_SHIFT (7U)
13887/* ECP - Enable Channel Preemption. This field resets to 0.
13888 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13889 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13890 */
13891#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
13892/* @} */
13893
13894/* @name DCHPRI5 - Channel n Priority Register */
13895/* @{ */
13896#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
13897#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
13898#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
13899#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
13900#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
13901#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
13902#define DMA_DCHPRI5_DPA_MASK (0x40U)
13903#define DMA_DCHPRI5_DPA_SHIFT (6U)
13904/* DPA - Disable Preempt Ability. This field resets to 0.
13905 * 0b0..Channel n can suspend a lower priority channel.
13906 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13907 */
13908#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
13909#define DMA_DCHPRI5_ECP_MASK (0x80U)
13910#define DMA_DCHPRI5_ECP_SHIFT (7U)
13911/* ECP - Enable Channel Preemption. This field resets to 0.
13912 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13913 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13914 */
13915#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
13916/* @} */
13917
13918/* @name DCHPRI4 - Channel n Priority Register */
13919/* @{ */
13920#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
13921#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
13922#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
13923#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
13924#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
13925#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
13926#define DMA_DCHPRI4_DPA_MASK (0x40U)
13927#define DMA_DCHPRI4_DPA_SHIFT (6U)
13928/* DPA - Disable Preempt Ability. This field resets to 0.
13929 * 0b0..Channel n can suspend a lower priority channel.
13930 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13931 */
13932#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
13933#define DMA_DCHPRI4_ECP_MASK (0x80U)
13934#define DMA_DCHPRI4_ECP_SHIFT (7U)
13935/* ECP - Enable Channel Preemption. This field resets to 0.
13936 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13937 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13938 */
13939#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
13940/* @} */
13941
13942/* @name DCHPRI11 - Channel n Priority Register */
13943/* @{ */
13944#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
13945#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
13946#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
13947#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
13948#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
13949#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
13950#define DMA_DCHPRI11_DPA_MASK (0x40U)
13951#define DMA_DCHPRI11_DPA_SHIFT (6U)
13952/* DPA - Disable Preempt Ability. This field resets to 0.
13953 * 0b0..Channel n can suspend a lower priority channel.
13954 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13955 */
13956#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
13957#define DMA_DCHPRI11_ECP_MASK (0x80U)
13958#define DMA_DCHPRI11_ECP_SHIFT (7U)
13959/* ECP - Enable Channel Preemption. This field resets to 0.
13960 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13961 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13962 */
13963#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
13964/* @} */
13965
13966/* @name DCHPRI10 - Channel n Priority Register */
13967/* @{ */
13968#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
13969#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
13970#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
13971#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
13972#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
13973#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
13974#define DMA_DCHPRI10_DPA_MASK (0x40U)
13975#define DMA_DCHPRI10_DPA_SHIFT (6U)
13976/* DPA - Disable Preempt Ability. This field resets to 0.
13977 * 0b0..Channel n can suspend a lower priority channel.
13978 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
13979 */
13980#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
13981#define DMA_DCHPRI10_ECP_MASK (0x80U)
13982#define DMA_DCHPRI10_ECP_SHIFT (7U)
13983/* ECP - Enable Channel Preemption. This field resets to 0.
13984 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
13985 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
13986 */
13987#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
13988/* @} */
13989
13990/* @name DCHPRI9 - Channel n Priority Register */
13991/* @{ */
13992#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
13993#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
13994#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
13995#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
13996#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
13997#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
13998#define DMA_DCHPRI9_DPA_MASK (0x40U)
13999#define DMA_DCHPRI9_DPA_SHIFT (6U)
14000/* DPA - Disable Preempt Ability. This field resets to 0.
14001 * 0b0..Channel n can suspend a lower priority channel.
14002 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14003 */
14004#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
14005#define DMA_DCHPRI9_ECP_MASK (0x80U)
14006#define DMA_DCHPRI9_ECP_SHIFT (7U)
14007/* ECP - Enable Channel Preemption. This field resets to 0.
14008 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14009 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14010 */
14011#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
14012/* @} */
14013
14014/* @name DCHPRI8 - Channel n Priority Register */
14015/* @{ */
14016#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
14017#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
14018#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
14019#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
14020#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
14021#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
14022#define DMA_DCHPRI8_DPA_MASK (0x40U)
14023#define DMA_DCHPRI8_DPA_SHIFT (6U)
14024/* DPA - Disable Preempt Ability. This field resets to 0.
14025 * 0b0..Channel n can suspend a lower priority channel.
14026 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14027 */
14028#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
14029#define DMA_DCHPRI8_ECP_MASK (0x80U)
14030#define DMA_DCHPRI8_ECP_SHIFT (7U)
14031/* ECP - Enable Channel Preemption. This field resets to 0.
14032 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14033 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14034 */
14035#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
14036/* @} */
14037
14038/* @name DCHPRI15 - Channel n Priority Register */
14039/* @{ */
14040#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
14041#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
14042#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
14043#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
14044#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
14045#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
14046#define DMA_DCHPRI15_DPA_MASK (0x40U)
14047#define DMA_DCHPRI15_DPA_SHIFT (6U)
14048/* DPA - Disable Preempt Ability. This field resets to 0.
14049 * 0b0..Channel n can suspend a lower priority channel.
14050 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14051 */
14052#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
14053#define DMA_DCHPRI15_ECP_MASK (0x80U)
14054#define DMA_DCHPRI15_ECP_SHIFT (7U)
14055/* ECP - Enable Channel Preemption. This field resets to 0.
14056 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14057 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14058 */
14059#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
14060/* @} */
14061
14062/* @name DCHPRI14 - Channel n Priority Register */
14063/* @{ */
14064#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
14065#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
14066#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
14067#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
14068#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
14069#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
14070#define DMA_DCHPRI14_DPA_MASK (0x40U)
14071#define DMA_DCHPRI14_DPA_SHIFT (6U)
14072/* DPA - Disable Preempt Ability. This field resets to 0.
14073 * 0b0..Channel n can suspend a lower priority channel.
14074 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14075 */
14076#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
14077#define DMA_DCHPRI14_ECP_MASK (0x80U)
14078#define DMA_DCHPRI14_ECP_SHIFT (7U)
14079/* ECP - Enable Channel Preemption. This field resets to 0.
14080 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14081 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14082 */
14083#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
14084/* @} */
14085
14086/* @name DCHPRI13 - Channel n Priority Register */
14087/* @{ */
14088#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
14089#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
14090#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
14091#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
14092#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
14093#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
14094#define DMA_DCHPRI13_DPA_MASK (0x40U)
14095#define DMA_DCHPRI13_DPA_SHIFT (6U)
14096/* DPA - Disable Preempt Ability. This field resets to 0.
14097 * 0b0..Channel n can suspend a lower priority channel.
14098 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14099 */
14100#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
14101#define DMA_DCHPRI13_ECP_MASK (0x80U)
14102#define DMA_DCHPRI13_ECP_SHIFT (7U)
14103/* ECP - Enable Channel Preemption. This field resets to 0.
14104 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14105 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14106 */
14107#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
14108/* @} */
14109
14110/* @name DCHPRI12 - Channel n Priority Register */
14111/* @{ */
14112#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
14113#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
14114#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
14115#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
14116#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
14117#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
14118#define DMA_DCHPRI12_DPA_MASK (0x40U)
14119#define DMA_DCHPRI12_DPA_SHIFT (6U)
14120/* DPA - Disable Preempt Ability. This field resets to 0.
14121 * 0b0..Channel n can suspend a lower priority channel.
14122 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14123 */
14124#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
14125#define DMA_DCHPRI12_ECP_MASK (0x80U)
14126#define DMA_DCHPRI12_ECP_SHIFT (7U)
14127/* ECP - Enable Channel Preemption. This field resets to 0.
14128 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14129 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14130 */
14131#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
14132/* @} */
14133
14134/* @name DCHPRI19 - Channel n Priority Register */
14135/* @{ */
14136#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
14137#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
14138#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
14139#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
14140#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
14141#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
14142#define DMA_DCHPRI19_DPA_MASK (0x40U)
14143#define DMA_DCHPRI19_DPA_SHIFT (6U)
14144/* DPA - Disable Preempt Ability. This field resets to 0.
14145 * 0b0..Channel n can suspend a lower priority channel.
14146 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14147 */
14148#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
14149#define DMA_DCHPRI19_ECP_MASK (0x80U)
14150#define DMA_DCHPRI19_ECP_SHIFT (7U)
14151/* ECP - Enable Channel Preemption. This field resets to 0.
14152 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14153 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14154 */
14155#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
14156/* @} */
14157
14158/* @name DCHPRI18 - Channel n Priority Register */
14159/* @{ */
14160#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
14161#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
14162#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
14163#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
14164#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
14165#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
14166#define DMA_DCHPRI18_DPA_MASK (0x40U)
14167#define DMA_DCHPRI18_DPA_SHIFT (6U)
14168/* DPA - Disable Preempt Ability. This field resets to 0.
14169 * 0b0..Channel n can suspend a lower priority channel.
14170 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14171 */
14172#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
14173#define DMA_DCHPRI18_ECP_MASK (0x80U)
14174#define DMA_DCHPRI18_ECP_SHIFT (7U)
14175/* ECP - Enable Channel Preemption. This field resets to 0.
14176 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14177 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14178 */
14179#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
14180/* @} */
14181
14182/* @name DCHPRI17 - Channel n Priority Register */
14183/* @{ */
14184#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
14185#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
14186#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
14187#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
14188#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
14189#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
14190#define DMA_DCHPRI17_DPA_MASK (0x40U)
14191#define DMA_DCHPRI17_DPA_SHIFT (6U)
14192/* DPA - Disable Preempt Ability. This field resets to 0.
14193 * 0b0..Channel n can suspend a lower priority channel.
14194 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14195 */
14196#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
14197#define DMA_DCHPRI17_ECP_MASK (0x80U)
14198#define DMA_DCHPRI17_ECP_SHIFT (7U)
14199/* ECP - Enable Channel Preemption. This field resets to 0.
14200 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14201 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14202 */
14203#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
14204/* @} */
14205
14206/* @name DCHPRI16 - Channel n Priority Register */
14207/* @{ */
14208#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
14209#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
14210#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
14211#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
14212#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
14213#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
14214#define DMA_DCHPRI16_DPA_MASK (0x40U)
14215#define DMA_DCHPRI16_DPA_SHIFT (6U)
14216/* DPA - Disable Preempt Ability. This field resets to 0.
14217 * 0b0..Channel n can suspend a lower priority channel.
14218 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14219 */
14220#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
14221#define DMA_DCHPRI16_ECP_MASK (0x80U)
14222#define DMA_DCHPRI16_ECP_SHIFT (7U)
14223/* ECP - Enable Channel Preemption. This field resets to 0.
14224 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14225 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14226 */
14227#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
14228/* @} */
14229
14230/* @name DCHPRI23 - Channel n Priority Register */
14231/* @{ */
14232#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
14233#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
14234#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
14235#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
14236#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
14237#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
14238#define DMA_DCHPRI23_DPA_MASK (0x40U)
14239#define DMA_DCHPRI23_DPA_SHIFT (6U)
14240/* DPA - Disable Preempt Ability. This field resets to 0.
14241 * 0b0..Channel n can suspend a lower priority channel.
14242 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14243 */
14244#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
14245#define DMA_DCHPRI23_ECP_MASK (0x80U)
14246#define DMA_DCHPRI23_ECP_SHIFT (7U)
14247/* ECP - Enable Channel Preemption. This field resets to 0.
14248 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14249 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14250 */
14251#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
14252/* @} */
14253
14254/* @name DCHPRI22 - Channel n Priority Register */
14255/* @{ */
14256#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
14257#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
14258#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
14259#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
14260#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
14261#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
14262#define DMA_DCHPRI22_DPA_MASK (0x40U)
14263#define DMA_DCHPRI22_DPA_SHIFT (6U)
14264/* DPA - Disable Preempt Ability. This field resets to 0.
14265 * 0b0..Channel n can suspend a lower priority channel.
14266 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14267 */
14268#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
14269#define DMA_DCHPRI22_ECP_MASK (0x80U)
14270#define DMA_DCHPRI22_ECP_SHIFT (7U)
14271/* ECP - Enable Channel Preemption. This field resets to 0.
14272 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14273 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14274 */
14275#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
14276/* @} */
14277
14278/* @name DCHPRI21 - Channel n Priority Register */
14279/* @{ */
14280#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
14281#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
14282#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
14283#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
14284#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
14285#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
14286#define DMA_DCHPRI21_DPA_MASK (0x40U)
14287#define DMA_DCHPRI21_DPA_SHIFT (6U)
14288/* DPA - Disable Preempt Ability. This field resets to 0.
14289 * 0b0..Channel n can suspend a lower priority channel.
14290 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14291 */
14292#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
14293#define DMA_DCHPRI21_ECP_MASK (0x80U)
14294#define DMA_DCHPRI21_ECP_SHIFT (7U)
14295/* ECP - Enable Channel Preemption. This field resets to 0.
14296 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14297 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14298 */
14299#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
14300/* @} */
14301
14302/* @name DCHPRI20 - Channel n Priority Register */
14303/* @{ */
14304#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
14305#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
14306#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
14307#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
14308#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
14309#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
14310#define DMA_DCHPRI20_DPA_MASK (0x40U)
14311#define DMA_DCHPRI20_DPA_SHIFT (6U)
14312/* DPA - Disable Preempt Ability. This field resets to 0.
14313 * 0b0..Channel n can suspend a lower priority channel.
14314 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14315 */
14316#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
14317#define DMA_DCHPRI20_ECP_MASK (0x80U)
14318#define DMA_DCHPRI20_ECP_SHIFT (7U)
14319/* ECP - Enable Channel Preemption. This field resets to 0.
14320 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14321 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14322 */
14323#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
14324/* @} */
14325
14326/* @name DCHPRI27 - Channel n Priority Register */
14327/* @{ */
14328#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
14329#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
14330#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
14331#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
14332#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
14333#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
14334#define DMA_DCHPRI27_DPA_MASK (0x40U)
14335#define DMA_DCHPRI27_DPA_SHIFT (6U)
14336/* DPA - Disable Preempt Ability. This field resets to 0.
14337 * 0b0..Channel n can suspend a lower priority channel.
14338 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14339 */
14340#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
14341#define DMA_DCHPRI27_ECP_MASK (0x80U)
14342#define DMA_DCHPRI27_ECP_SHIFT (7U)
14343/* ECP - Enable Channel Preemption. This field resets to 0.
14344 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14345 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14346 */
14347#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
14348/* @} */
14349
14350/* @name DCHPRI26 - Channel n Priority Register */
14351/* @{ */
14352#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
14353#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
14354#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
14355#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
14356#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
14357#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
14358#define DMA_DCHPRI26_DPA_MASK (0x40U)
14359#define DMA_DCHPRI26_DPA_SHIFT (6U)
14360/* DPA - Disable Preempt Ability. This field resets to 0.
14361 * 0b0..Channel n can suspend a lower priority channel.
14362 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14363 */
14364#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
14365#define DMA_DCHPRI26_ECP_MASK (0x80U)
14366#define DMA_DCHPRI26_ECP_SHIFT (7U)
14367/* ECP - Enable Channel Preemption. This field resets to 0.
14368 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14369 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14370 */
14371#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
14372/* @} */
14373
14374/* @name DCHPRI25 - Channel n Priority Register */
14375/* @{ */
14376#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
14377#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
14378#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
14379#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
14380#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
14381#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
14382#define DMA_DCHPRI25_DPA_MASK (0x40U)
14383#define DMA_DCHPRI25_DPA_SHIFT (6U)
14384/* DPA - Disable Preempt Ability. This field resets to 0.
14385 * 0b0..Channel n can suspend a lower priority channel.
14386 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14387 */
14388#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
14389#define DMA_DCHPRI25_ECP_MASK (0x80U)
14390#define DMA_DCHPRI25_ECP_SHIFT (7U)
14391/* ECP - Enable Channel Preemption. This field resets to 0.
14392 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14393 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14394 */
14395#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
14396/* @} */
14397
14398/* @name DCHPRI24 - Channel n Priority Register */
14399/* @{ */
14400#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
14401#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
14402#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
14403#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
14404#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
14405#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
14406#define DMA_DCHPRI24_DPA_MASK (0x40U)
14407#define DMA_DCHPRI24_DPA_SHIFT (6U)
14408/* DPA - Disable Preempt Ability. This field resets to 0.
14409 * 0b0..Channel n can suspend a lower priority channel.
14410 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14411 */
14412#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
14413#define DMA_DCHPRI24_ECP_MASK (0x80U)
14414#define DMA_DCHPRI24_ECP_SHIFT (7U)
14415/* ECP - Enable Channel Preemption. This field resets to 0.
14416 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14417 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14418 */
14419#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
14420/* @} */
14421
14422/* @name DCHPRI31 - Channel n Priority Register */
14423/* @{ */
14424#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
14425#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
14426#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
14427#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
14428#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
14429#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
14430#define DMA_DCHPRI31_DPA_MASK (0x40U)
14431#define DMA_DCHPRI31_DPA_SHIFT (6U)
14432/* DPA - Disable Preempt Ability. This field resets to 0.
14433 * 0b0..Channel n can suspend a lower priority channel.
14434 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14435 */
14436#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
14437#define DMA_DCHPRI31_ECP_MASK (0x80U)
14438#define DMA_DCHPRI31_ECP_SHIFT (7U)
14439/* ECP - Enable Channel Preemption. This field resets to 0.
14440 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14441 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14442 */
14443#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
14444/* @} */
14445
14446/* @name DCHPRI30 - Channel n Priority Register */
14447/* @{ */
14448#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
14449#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
14450#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
14451#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
14452#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
14453#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
14454#define DMA_DCHPRI30_DPA_MASK (0x40U)
14455#define DMA_DCHPRI30_DPA_SHIFT (6U)
14456/* DPA - Disable Preempt Ability. This field resets to 0.
14457 * 0b0..Channel n can suspend a lower priority channel.
14458 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14459 */
14460#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
14461#define DMA_DCHPRI30_ECP_MASK (0x80U)
14462#define DMA_DCHPRI30_ECP_SHIFT (7U)
14463/* ECP - Enable Channel Preemption. This field resets to 0.
14464 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14465 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14466 */
14467#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
14468/* @} */
14469
14470/* @name DCHPRI29 - Channel n Priority Register */
14471/* @{ */
14472#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
14473#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
14474#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
14475#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
14476#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
14477#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
14478#define DMA_DCHPRI29_DPA_MASK (0x40U)
14479#define DMA_DCHPRI29_DPA_SHIFT (6U)
14480/* DPA - Disable Preempt Ability. This field resets to 0.
14481 * 0b0..Channel n can suspend a lower priority channel.
14482 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14483 */
14484#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
14485#define DMA_DCHPRI29_ECP_MASK (0x80U)
14486#define DMA_DCHPRI29_ECP_SHIFT (7U)
14487/* ECP - Enable Channel Preemption. This field resets to 0.
14488 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14489 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14490 */
14491#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
14492/* @} */
14493
14494/* @name DCHPRI28 - Channel n Priority Register */
14495/* @{ */
14496#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
14497#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
14498#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
14499#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
14500#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
14501#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
14502#define DMA_DCHPRI28_DPA_MASK (0x40U)
14503#define DMA_DCHPRI28_DPA_SHIFT (6U)
14504/* DPA - Disable Preempt Ability. This field resets to 0.
14505 * 0b0..Channel n can suspend a lower priority channel.
14506 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
14507 */
14508#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
14509#define DMA_DCHPRI28_ECP_MASK (0x80U)
14510#define DMA_DCHPRI28_ECP_SHIFT (7U)
14511/* ECP - Enable Channel Preemption. This field resets to 0.
14512 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
14513 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
14514 */
14515#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
14516/* @} */
14517
14518/* @name SADDR - TCD Source Address */
14519/* @{ */
14520#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
14521#define DMA_SADDR_SADDR_SHIFT (0U)
14522#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
14523/* @} */
14524
14525/* The count of DMA_SADDR */
14526#define DMA_SADDR_COUNT (32U)
14527
14528/* @name SOFF - TCD Signed Source Address Offset */
14529/* @{ */
14530#define DMA_SOFF_SOFF_MASK (0xFFFFU)
14531#define DMA_SOFF_SOFF_SHIFT (0U)
14532#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
14533/* @} */
14534
14535/* The count of DMA_SOFF */
14536#define DMA_SOFF_COUNT (32U)
14537
14538/* @name ATTR - TCD Transfer Attributes */
14539/* @{ */
14540#define DMA_ATTR_DSIZE_MASK (0x7U)
14541#define DMA_ATTR_DSIZE_SHIFT (0U)
14542#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
14543#define DMA_ATTR_DMOD_MASK (0xF8U)
14544#define DMA_ATTR_DMOD_SHIFT (3U)
14545#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
14546#define DMA_ATTR_SSIZE_MASK (0x700U)
14547#define DMA_ATTR_SSIZE_SHIFT (8U)
14548/* SSIZE - Source data transfer size
14549 * 0b000..8-bit
14550 * 0b001..16-bit
14551 * 0b010..32-bit
14552 * 0b011..64-bit
14553 * 0b100..Reserved
14554 * 0b101..32-byte burst (4 beats of 64 bits)
14555 * 0b110..Reserved
14556 * 0b111..Reserved
14557 */
14558#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
14559#define DMA_ATTR_SMOD_MASK (0xF800U)
14560#define DMA_ATTR_SMOD_SHIFT (11U)
14561/* SMOD - Source Address Modulo
14562 * 0b00000..Source address modulo feature is disabled
14563 * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF
14564 * calculation is performed on the original register value. Setting this field provides the ability
14565 * to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the
14566 * queue should start at a 0-modulo-size address and the SMOD field should be set to the
14567 * appropriate value for the queue, freezing the desired number of upper address bits. The value
14568 * programmed into this field specifies the number of lower address bits allowed to change. For a
14569 * circular queue application, the SOFF is typically set to the transfer size to implement
14570 * post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.
14571 */
14572#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
14573/* @} */
14574
14575/* The count of DMA_ATTR */
14576#define DMA_ATTR_COUNT (32U)
14577
14578/* @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
14579/* @{ */
14580#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
14581#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
14582#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
14583/* @} */
14584
14585/* The count of DMA_NBYTES_MLNO */
14586#define DMA_NBYTES_MLNO_COUNT (32U)
14587
14588/* @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
14589/* @{ */
14590#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
14591#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
14592#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
14593#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
14594#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
14595/* DMLOE - Destination Minor Loop Offset enable
14596 * 0b0..The minor loop offset is not applied to the DADDR
14597 * 0b1..The minor loop offset is applied to the DADDR
14598 */
14599#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
14600#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
14601#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
14602/* SMLOE - Source Minor Loop Offset Enable
14603 * 0b0..The minor loop offset is not applied to the SADDR
14604 * 0b1..The minor loop offset is applied to the SADDR
14605 */
14606#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
14607/* @} */
14608
14609/* The count of DMA_NBYTES_MLOFFNO */
14610#define DMA_NBYTES_MLOFFNO_COUNT (32U)
14611
14612/* @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
14613/* @{ */
14614#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
14615#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
14616#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
14617#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
14618#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
14619#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
14620#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
14621#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
14622/* DMLOE - Destination Minor Loop Offset enable
14623 * 0b0..The minor loop offset is not applied to the DADDR
14624 * 0b1..The minor loop offset is applied to the DADDR
14625 */
14626#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
14627#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
14628#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
14629/* SMLOE - Source Minor Loop Offset Enable
14630 * 0b0..The minor loop offset is not applied to the SADDR
14631 * 0b1..The minor loop offset is applied to the SADDR
14632 */
14633#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
14634/* @} */
14635
14636/* The count of DMA_NBYTES_MLOFFYES */
14637#define DMA_NBYTES_MLOFFYES_COUNT (32U)
14638
14639/* @name SLAST - TCD Last Source Address Adjustment */
14640/* @{ */
14641#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
14642#define DMA_SLAST_SLAST_SHIFT (0U)
14643#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
14644/* @} */
14645
14646/* The count of DMA_SLAST */
14647#define DMA_SLAST_COUNT (32U)
14648
14649/* @name DADDR - TCD Destination Address */
14650/* @{ */
14651#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
14652#define DMA_DADDR_DADDR_SHIFT (0U)
14653#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
14654/* @} */
14655
14656/* The count of DMA_DADDR */
14657#define DMA_DADDR_COUNT (32U)
14658
14659/* @name DOFF - TCD Signed Destination Address Offset */
14660/* @{ */
14661#define DMA_DOFF_DOFF_MASK (0xFFFFU)
14662#define DMA_DOFF_DOFF_SHIFT (0U)
14663#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
14664/* @} */
14665
14666/* The count of DMA_DOFF */
14667#define DMA_DOFF_COUNT (32U)
14668
14669/* @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
14670/* @{ */
14671#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
14672#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
14673#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
14674#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
14675#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
14676/* ELINK - Enable channel-to-channel linking on minor-loop complete
14677 * 0b0..The channel-to-channel linking is disabled
14678 * 0b1..The channel-to-channel linking is enabled
14679 */
14680#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
14681/* @} */
14682
14683/* The count of DMA_CITER_ELINKNO */
14684#define DMA_CITER_ELINKNO_COUNT (32U)
14685
14686/* @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
14687/* @{ */
14688#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
14689#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
14690#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
14691#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
14692#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
14693#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
14694#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
14695#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
14696/* ELINK - Enable channel-to-channel linking on minor-loop complete
14697 * 0b0..The channel-to-channel linking is disabled
14698 * 0b1..The channel-to-channel linking is enabled
14699 */
14700#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
14701/* @} */
14702
14703/* The count of DMA_CITER_ELINKYES */
14704#define DMA_CITER_ELINKYES_COUNT (32U)
14705
14706/* @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
14707/* @{ */
14708#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
14709#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
14710#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
14711/* @} */
14712
14713/* The count of DMA_DLAST_SGA */
14714#define DMA_DLAST_SGA_COUNT (32U)
14715
14716/* @name CSR - TCD Control and Status */
14717/* @{ */
14718#define DMA_CSR_START_MASK (0x1U)
14719#define DMA_CSR_START_SHIFT (0U)
14720/* START - Channel Start
14721 * 0b0..The channel is not explicitly started.
14722 * 0b1..The channel is explicitly started via a software initiated service request.
14723 */
14724#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
14725#define DMA_CSR_INTMAJOR_MASK (0x2U)
14726#define DMA_CSR_INTMAJOR_SHIFT (1U)
14727/* INTMAJOR - Enable an interrupt when major iteration count completes.
14728 * 0b0..The end-of-major loop interrupt is disabled.
14729 * 0b1..The end-of-major loop interrupt is enabled.
14730 */
14731#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
14732#define DMA_CSR_INTHALF_MASK (0x4U)
14733#define DMA_CSR_INTHALF_SHIFT (2U)
14734/* INTHALF - Enable an interrupt when major counter is half complete.
14735 * 0b0..The half-point interrupt is disabled.
14736 * 0b1..The half-point interrupt is enabled.
14737 */
14738#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
14739#define DMA_CSR_DREQ_MASK (0x8U)
14740#define DMA_CSR_DREQ_SHIFT (3U)
14741/* DREQ - Disable Request
14742 * 0b0..The channel's ERQ bit is not affected.
14743 * 0b1..The channel's ERQ bit is cleared when the major loop is complete.
14744 */
14745#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
14746#define DMA_CSR_ESG_MASK (0x10U)
14747#define DMA_CSR_ESG_SHIFT (4U)
14748/* ESG - Enable Scatter/Gather Processing
14749 * 0b0..The current channel's TCD is normal format.
14750 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
14751 * to the next TCD to be loaded into this channel after the major loop completes its execution.
14752 */
14753#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
14754#define DMA_CSR_MAJORELINK_MASK (0x20U)
14755#define DMA_CSR_MAJORELINK_SHIFT (5U)
14756/* MAJORELINK - Enable channel-to-channel linking on major loop complete
14757 * 0b0..The channel-to-channel linking is disabled.
14758 * 0b1..The channel-to-channel linking is enabled.
14759 */
14760#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
14761#define DMA_CSR_ACTIVE_MASK (0x40U)
14762#define DMA_CSR_ACTIVE_SHIFT (6U)
14763#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
14764#define DMA_CSR_DONE_MASK (0x80U)
14765#define DMA_CSR_DONE_SHIFT (7U)
14766#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
14767#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
14768#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
14769#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
14770#define DMA_CSR_BWC_MASK (0xC000U)
14771#define DMA_CSR_BWC_SHIFT (14U)
14772/* BWC - Bandwidth Control
14773 * 0b00..No eDMA engine stalls.
14774 * 0b01..Reserved
14775 * 0b10..eDMA engine stalls for 4 cycles after each R/W.
14776 * 0b11..eDMA engine stalls for 8 cycles after each R/W.
14777 */
14778#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
14779/* @} */
14780
14781/* The count of DMA_CSR */
14782#define DMA_CSR_COUNT (32U)
14783
14784/* @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
14785/* @{ */
14786#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
14787#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
14788#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
14789#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
14790#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
14791/* ELINK - Enables channel-to-channel linking on minor loop complete
14792 * 0b0..The channel-to-channel linking is disabled
14793 * 0b1..The channel-to-channel linking is enabled
14794 */
14795#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
14796/* @} */
14797
14798/* The count of DMA_BITER_ELINKNO */
14799#define DMA_BITER_ELINKNO_COUNT (32U)
14800
14801/* @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
14802/* @{ */
14803#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
14804#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
14805#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
14806#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
14807#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
14808#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
14809#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
14810#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
14811/* ELINK - Enables channel-to-channel linking on minor loop complete
14812 * 0b0..The channel-to-channel linking is disabled
14813 * 0b1..The channel-to-channel linking is enabled
14814 */
14815#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
14816/* @} */
14817
14818/* The count of DMA_BITER_ELINKYES */
14819#define DMA_BITER_ELINKYES_COUNT (32U)
14820
14821
14822/*
14823 * @}
14824 */ /* end of group DMA_Register_Masks */
14825
14826
14827/* DMA - Peripheral instance base addresses */
14828/* Peripheral DMA0 base address */
14829#define DMA0_BASE (0x400E8000u)
14830/* Peripheral DMA0 base pointer */
14831#define DMA0 ((DMA_Type *)DMA0_BASE)
14832/* Array initializer of DMA peripheral base addresses */
14833#define DMA_BASE_ADDRS { DMA0_BASE }
14834/* Array initializer of DMA peripheral base pointers */
14835#define DMA_BASE_PTRS { DMA0 }
14836/* Interrupt vectors for the DMA peripheral type */
14837#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
14838#define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
14839
14840/*
14841 * @}
14842 */ /* end of group DMA_Peripheral_Access_Layer */
14843
14844
14845/* ----------------------------------------------------------------------------
14846 -- DMAMUX Peripheral Access Layer
14847 ---------------------------------------------------------------------------- */
14848
14849/*
14850 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
14851 * @{
14852 */
14853
14854/* DMAMUX - Register Layout Typedef */
14855typedef struct {
14856 __IO uint32_t CHCFG[32];
14857} DMAMUX_Type;
14858
14859/* ----------------------------------------------------------------------------
14860 -- DMAMUX Register Masks
14861 ---------------------------------------------------------------------------- */
14862
14863/*
14864 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
14865 * @{
14866 */
14867
14868/* @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
14869/* @{ */
14870#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU)
14871#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
14872#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
14873#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
14874#define DMAMUX_CHCFG_A_ON_SHIFT (29U)
14875/* A_ON - DMA Channel Always Enable
14876 * 0b0..DMA Channel Always ON function is disabled
14877 * 0b1..DMA Channel Always ON function is enabled
14878 */
14879#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
14880#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
14881#define DMAMUX_CHCFG_TRIG_SHIFT (30U)
14882/* TRIG - DMA Channel Trigger Enable
14883 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
14884 * specified source to the DMA channel. (Normal mode)
14885 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
14886 */
14887#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
14888#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
14889#define DMAMUX_CHCFG_ENBL_SHIFT (31U)
14890/* ENBL - DMA Mux Channel Enable
14891 * 0b0..DMA Mux channel is disabled
14892 * 0b1..DMA Mux channel is enabled
14893 */
14894#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
14895/* @} */
14896
14897/* The count of DMAMUX_CHCFG */
14898#define DMAMUX_CHCFG_COUNT (32U)
14899
14900
14901/*
14902 * @}
14903 */ /* end of group DMAMUX_Register_Masks */
14904
14905
14906/* DMAMUX - Peripheral instance base addresses */
14907/* Peripheral DMAMUX base address */
14908#define DMAMUX_BASE (0x400EC000u)
14909/* Peripheral DMAMUX base pointer */
14910#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
14911/* Array initializer of DMAMUX peripheral base addresses */
14912#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
14913/* Array initializer of DMAMUX peripheral base pointers */
14914#define DMAMUX_BASE_PTRS { DMAMUX }
14915
14916/*
14917 * @}
14918 */ /* end of group DMAMUX_Peripheral_Access_Layer */
14919
14920
14921/* ----------------------------------------------------------------------------
14922 -- QDC Peripheral Access Layer
14923 ---------------------------------------------------------------------------- */
14924
14925/*
14926 * @addtogroup QDC_Peripheral_Access_Layer QDC Peripheral Access Layer
14927 * @{
14928 */
14929
14930/* QDC - Register Layout Typedef */
14931typedef struct {
14932 __IO uint16_t CTRL;
14933 __IO uint16_t FILT;
14934 __IO uint16_t WTR;
14935 __IO uint16_t POSD;
14936 __I uint16_t POSDH;
14937 __IO uint16_t REV;
14938 __I uint16_t REVH;
14939 __IO uint16_t UPOS;
14940 __IO uint16_t LPOS;
14941 __I uint16_t UPOSH;
14942 __I uint16_t LPOSH;
14943 __IO uint16_t UINIT;
14944 __IO uint16_t LINIT;
14945 __I uint16_t IMR;
14946 __IO uint16_t TST;
14947 __IO uint16_t CTRL2;
14948 __IO uint16_t UMOD;
14949 __IO uint16_t LMOD;
14950 __IO uint16_t UCOMP;
14951 __IO uint16_t LCOMP;
14952} QDC_Type;
14953
14954/* ----------------------------------------------------------------------------
14955 -- QDC Register Masks
14956 ---------------------------------------------------------------------------- */
14957
14958/*
14959 * @addtogroup QDC_Register_Masks QDC Register Masks
14960 * @{
14961 */
14962
14963/* @name CTRL - Control Register */
14964/* @{ */
14965#define QDC_CTRL_CMPIE_MASK (0x1U)
14966#define QDC_CTRL_CMPIE_SHIFT (0U)
14967/* CMPIE - Compare Interrupt Enable
14968 * 0b0..Compare interrupt is disabled
14969 * 0b1..Compare interrupt is enabled
14970 */
14971#define QDC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIE_SHIFT)) & QDC_CTRL_CMPIE_MASK)
14972#define QDC_CTRL_CMPIRQ_MASK (0x2U)
14973#define QDC_CTRL_CMPIRQ_SHIFT (1U)
14974/* CMPIRQ - Compare Interrupt Request
14975 * 0b0..No match has occurred
14976 * 0b1..COMP match has occurred
14977 */
14978#define QDC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIRQ_SHIFT)) & QDC_CTRL_CMPIRQ_MASK)
14979#define QDC_CTRL_WDE_MASK (0x4U)
14980#define QDC_CTRL_WDE_SHIFT (2U)
14981/* WDE - Watchdog Enable
14982 * 0b0..Watchdog timer is disabled
14983 * 0b1..Watchdog timer is enabled
14984 */
14985#define QDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_WDE_SHIFT)) & QDC_CTRL_WDE_MASK)
14986#define QDC_CTRL_DIE_MASK (0x8U)
14987#define QDC_CTRL_DIE_SHIFT (3U)
14988/* DIE - Watchdog Timeout Interrupt Enable
14989 * 0b0..Watchdog timer interrupt is disabled
14990 * 0b1..Watchdog timer interrupt is enabled
14991 */
14992#define QDC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIE_SHIFT)) & QDC_CTRL_DIE_MASK)
14993#define QDC_CTRL_DIRQ_MASK (0x10U)
14994#define QDC_CTRL_DIRQ_SHIFT (4U)
14995/* DIRQ - Watchdog Timeout Interrupt Request
14996 * 0b0..No interrupt has occurred
14997 * 0b1..Watchdog timeout interrupt has occurred
14998 */
14999#define QDC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIRQ_SHIFT)) & QDC_CTRL_DIRQ_MASK)
15000#define QDC_CTRL_XNE_MASK (0x20U)
15001#define QDC_CTRL_XNE_SHIFT (5U)
15002/* XNE - Use Negative Edge of INDEX Pulse
15003 * 0b0..Use positive transition edge of INDEX pulse
15004 * 0b1..Use negative transition edge of INDEX pulse
15005 */
15006#define QDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XNE_SHIFT)) & QDC_CTRL_XNE_MASK)
15007#define QDC_CTRL_XIP_MASK (0x40U)
15008#define QDC_CTRL_XIP_SHIFT (6U)
15009/* XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
15010 * 0b0..No action
15011 * 0b1..INDEX pulse initializes the position counter
15012 */
15013#define QDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIP_SHIFT)) & QDC_CTRL_XIP_MASK)
15014#define QDC_CTRL_XIE_MASK (0x80U)
15015#define QDC_CTRL_XIE_SHIFT (7U)
15016/* XIE - INDEX Pulse Interrupt Enable
15017 * 0b0..INDEX pulse interrupt is disabled
15018 * 0b1..INDEX pulse interrupt is enabled
15019 */
15020#define QDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIE_SHIFT)) & QDC_CTRL_XIE_MASK)
15021#define QDC_CTRL_XIRQ_MASK (0x100U)
15022#define QDC_CTRL_XIRQ_SHIFT (8U)
15023/* XIRQ - INDEX Pulse Interrupt Request
15024 * 0b0..No interrupt has occurred
15025 * 0b1..INDEX pulse interrupt has occurred
15026 */
15027#define QDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIRQ_SHIFT)) & QDC_CTRL_XIRQ_MASK)
15028#define QDC_CTRL_PH1_MASK (0x200U)
15029#define QDC_CTRL_PH1_SHIFT (9U)
15030/* PH1 - Enable Signal Phase Count Mode
15031 * 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal.
15032 * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The
15033 * PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If
15034 * CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1,
15035 * PHASEB = 1, then count up
15036 */
15037#define QDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_PH1_SHIFT)) & QDC_CTRL_PH1_MASK)
15038#define QDC_CTRL_REV_MASK (0x400U)
15039#define QDC_CTRL_REV_SHIFT (10U)
15040/* REV - Enable Reverse Direction Counting
15041 * 0b0..Count normally
15042 * 0b1..Count in the reverse direction
15043 */
15044#define QDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_REV_SHIFT)) & QDC_CTRL_REV_MASK)
15045#define QDC_CTRL_SWIP_MASK (0x800U)
15046#define QDC_CTRL_SWIP_SHIFT (11U)
15047/* SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS
15048 * 0b0..No action
15049 * 0b1..Initialize position counter
15050 */
15051#define QDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_SWIP_SHIFT)) & QDC_CTRL_SWIP_MASK)
15052#define QDC_CTRL_HNE_MASK (0x1000U)
15053#define QDC_CTRL_HNE_SHIFT (12U)
15054/* HNE - Use Negative Edge of HOME Input
15055 * 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS
15056 * 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS
15057 */
15058#define QDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HNE_SHIFT)) & QDC_CTRL_HNE_MASK)
15059#define QDC_CTRL_HIP_MASK (0x2000U)
15060#define QDC_CTRL_HIP_SHIFT (13U)
15061/* HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
15062 * 0b0..No action
15063 * 0b1..HOME signal initializes the position counter
15064 */
15065#define QDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIP_SHIFT)) & QDC_CTRL_HIP_MASK)
15066#define QDC_CTRL_HIE_MASK (0x4000U)
15067#define QDC_CTRL_HIE_SHIFT (14U)
15068/* HIE - HOME Interrupt Enable
15069 * 0b0..Disable HOME interrupts
15070 * 0b1..Enable HOME interrupts
15071 */
15072#define QDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIE_SHIFT)) & QDC_CTRL_HIE_MASK)
15073#define QDC_CTRL_HIRQ_MASK (0x8000U)
15074#define QDC_CTRL_HIRQ_SHIFT (15U)
15075/* HIRQ - HOME Signal Transition Interrupt Request
15076 * 0b0..No interrupt
15077 * 0b1..HOME signal transition interrupt request
15078 */
15079#define QDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIRQ_SHIFT)) & QDC_CTRL_HIRQ_MASK)
15080/* @} */
15081
15082/* @name FILT - Input Filter Register */
15083/* @{ */
15084#define QDC_FILT_FILT_PER_MASK (0xFFU)
15085#define QDC_FILT_FILT_PER_SHIFT (0U)
15086#define QDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PER_SHIFT)) & QDC_FILT_FILT_PER_MASK)
15087#define QDC_FILT_FILT_CNT_MASK (0x700U)
15088#define QDC_FILT_FILT_CNT_SHIFT (8U)
15089#define QDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_CNT_SHIFT)) & QDC_FILT_FILT_CNT_MASK)
15090/* @} */
15091
15092/* @name WTR - Watchdog Timeout Register */
15093/* @{ */
15094#define QDC_WTR_WDOG_MASK (0xFFFFU)
15095#define QDC_WTR_WDOG_SHIFT (0U)
15096#define QDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << QDC_WTR_WDOG_SHIFT)) & QDC_WTR_WDOG_MASK)
15097/* @} */
15098
15099/* @name POSD - Position Difference Counter Register */
15100/* @{ */
15101#define QDC_POSD_POSD_MASK (0xFFFFU)
15102#define QDC_POSD_POSD_SHIFT (0U)
15103#define QDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSD_POSD_SHIFT)) & QDC_POSD_POSD_MASK)
15104/* @} */
15105
15106/* @name POSDH - Position Difference Hold Register */
15107/* @{ */
15108#define QDC_POSDH_POSDH_MASK (0xFFFFU)
15109#define QDC_POSDH_POSDH_SHIFT (0U)
15110#define QDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDH_POSDH_SHIFT)) & QDC_POSDH_POSDH_MASK)
15111/* @} */
15112
15113/* @name REV - Revolution Counter Register */
15114/* @{ */
15115#define QDC_REV_REV_MASK (0xFFFFU)
15116#define QDC_REV_REV_SHIFT (0U)
15117#define QDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_REV_REV_SHIFT)) & QDC_REV_REV_MASK)
15118/* @} */
15119
15120/* @name REVH - Revolution Hold Register */
15121/* @{ */
15122#define QDC_REVH_REVH_MASK (0xFFFFU)
15123#define QDC_REVH_REVH_SHIFT (0U)
15124#define QDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << QDC_REVH_REVH_SHIFT)) & QDC_REVH_REVH_MASK)
15125/* @} */
15126
15127/* @name UPOS - Upper Position Counter Register */
15128/* @{ */
15129#define QDC_UPOS_POS_MASK (0xFFFFU)
15130#define QDC_UPOS_POS_SHIFT (0U)
15131#define QDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOS_POS_SHIFT)) & QDC_UPOS_POS_MASK)
15132/* @} */
15133
15134/* @name LPOS - Lower Position Counter Register */
15135/* @{ */
15136#define QDC_LPOS_POS_MASK (0xFFFFU)
15137#define QDC_LPOS_POS_SHIFT (0U)
15138#define QDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOS_POS_SHIFT)) & QDC_LPOS_POS_MASK)
15139/* @} */
15140
15141/* @name UPOSH - Upper Position Hold Register */
15142/* @{ */
15143#define QDC_UPOSH_POSH_MASK (0xFFFFU)
15144#define QDC_UPOSH_POSH_SHIFT (0U)
15145#define QDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOSH_POSH_SHIFT)) & QDC_UPOSH_POSH_MASK)
15146/* @} */
15147
15148/* @name LPOSH - Lower Position Hold Register */
15149/* @{ */
15150#define QDC_LPOSH_POSH_MASK (0xFFFFU)
15151#define QDC_LPOSH_POSH_SHIFT (0U)
15152#define QDC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOSH_POSH_SHIFT)) & QDC_LPOSH_POSH_MASK)
15153/* @} */
15154
15155/* @name UINIT - Upper Initialization Register */
15156/* @{ */
15157#define QDC_UINIT_INIT_MASK (0xFFFFU)
15158#define QDC_UINIT_INIT_SHIFT (0U)
15159#define QDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_UINIT_INIT_SHIFT)) & QDC_UINIT_INIT_MASK)
15160/* @} */
15161
15162/* @name LINIT - Lower Initialization Register */
15163/* @{ */
15164#define QDC_LINIT_INIT_MASK (0xFFFFU)
15165#define QDC_LINIT_INIT_SHIFT (0U)
15166#define QDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_LINIT_INIT_SHIFT)) & QDC_LINIT_INIT_MASK)
15167/* @} */
15168
15169/* @name IMR - Input Monitor Register */
15170/* @{ */
15171#define QDC_IMR_HOME_MASK (0x1U)
15172#define QDC_IMR_HOME_SHIFT (0U)
15173#define QDC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_HOME_SHIFT)) & QDC_IMR_HOME_MASK)
15174#define QDC_IMR_INDEX_MASK (0x2U)
15175#define QDC_IMR_INDEX_SHIFT (1U)
15176#define QDC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_INDEX_SHIFT)) & QDC_IMR_INDEX_MASK)
15177#define QDC_IMR_PHB_MASK (0x4U)
15178#define QDC_IMR_PHB_SHIFT (2U)
15179#define QDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHB_SHIFT)) & QDC_IMR_PHB_MASK)
15180#define QDC_IMR_PHA_MASK (0x8U)
15181#define QDC_IMR_PHA_SHIFT (3U)
15182#define QDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHA_SHIFT)) & QDC_IMR_PHA_MASK)
15183#define QDC_IMR_FHOM_MASK (0x10U)
15184#define QDC_IMR_FHOM_SHIFT (4U)
15185#define QDC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FHOM_SHIFT)) & QDC_IMR_FHOM_MASK)
15186#define QDC_IMR_FIND_MASK (0x20U)
15187#define QDC_IMR_FIND_SHIFT (5U)
15188#define QDC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FIND_SHIFT)) & QDC_IMR_FIND_MASK)
15189#define QDC_IMR_FPHB_MASK (0x40U)
15190#define QDC_IMR_FPHB_SHIFT (6U)
15191#define QDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHB_SHIFT)) & QDC_IMR_FPHB_MASK)
15192#define QDC_IMR_FPHA_MASK (0x80U)
15193#define QDC_IMR_FPHA_SHIFT (7U)
15194#define QDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHA_SHIFT)) & QDC_IMR_FPHA_MASK)
15195/* @} */
15196
15197/* @name TST - Test Register */
15198/* @{ */
15199#define QDC_TST_TEST_COUNT_MASK (0xFFU)
15200#define QDC_TST_TEST_COUNT_SHIFT (0U)
15201#define QDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_COUNT_SHIFT)) & QDC_TST_TEST_COUNT_MASK)
15202#define QDC_TST_TEST_PERIOD_MASK (0x1F00U)
15203#define QDC_TST_TEST_PERIOD_SHIFT (8U)
15204#define QDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_PERIOD_SHIFT)) & QDC_TST_TEST_PERIOD_MASK)
15205#define QDC_TST_QDN_MASK (0x2000U)
15206#define QDC_TST_QDN_SHIFT (13U)
15207/* QDN - Quadrature Decoder Negative Signal
15208 * 0b0..Leaves quadrature decoder signal in a positive direction
15209 * 0b1..Generates a negative quadrature decoder signal
15210 */
15211#define QDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_QDN_SHIFT)) & QDC_TST_QDN_MASK)
15212#define QDC_TST_TCE_MASK (0x4000U)
15213#define QDC_TST_TCE_SHIFT (14U)
15214/* TCE - Test Counter Enable
15215 * 0b0..Test count is not enabled
15216 * 0b1..Test count is enabled
15217 */
15218#define QDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TCE_SHIFT)) & QDC_TST_TCE_MASK)
15219#define QDC_TST_TEN_MASK (0x8000U)
15220#define QDC_TST_TEN_SHIFT (15U)
15221/* TEN - Test Mode Enable
15222 * 0b0..Test module is not enabled
15223 * 0b1..Test module is enabled
15224 */
15225#define QDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEN_SHIFT)) & QDC_TST_TEN_MASK)
15226/* @} */
15227
15228/* @name CTRL2 - Control 2 Register */
15229/* @{ */
15230#define QDC_CTRL2_UPDHLD_MASK (0x1U)
15231#define QDC_CTRL2_UPDHLD_SHIFT (0U)
15232/* UPDHLD - Update Hold Registers
15233 * 0b0..Disable updates of hold registers on rising edge of TRIGGER
15234 * 0b1..Enable updates of hold registers on rising edge of TRIGGER
15235 */
15236#define QDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDHLD_SHIFT)) & QDC_CTRL2_UPDHLD_MASK)
15237#define QDC_CTRL2_UPDPOS_MASK (0x2U)
15238#define QDC_CTRL2_UPDPOS_SHIFT (1U)
15239/* UPDPOS - Update Position Registers
15240 * 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER
15241 * 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER
15242 */
15243#define QDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDPOS_SHIFT)) & QDC_CTRL2_UPDPOS_MASK)
15244#define QDC_CTRL2_MOD_MASK (0x4U)
15245#define QDC_CTRL2_MOD_SHIFT (2U)
15246/* MOD - Enable Modulo Counting
15247 * 0b0..Disable modulo counting
15248 * 0b1..Enable modulo counting
15249 */
15250#define QDC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_MOD_SHIFT)) & QDC_CTRL2_MOD_MASK)
15251#define QDC_CTRL2_DIR_MASK (0x8U)
15252#define QDC_CTRL2_DIR_SHIFT (3U)
15253/* DIR - Count Direction Flag
15254 * 0b0..Last count was in the down direction
15255 * 0b1..Last count was in the up direction
15256 */
15257#define QDC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_DIR_SHIFT)) & QDC_CTRL2_DIR_MASK)
15258#define QDC_CTRL2_RUIE_MASK (0x10U)
15259#define QDC_CTRL2_RUIE_SHIFT (4U)
15260/* RUIE - Roll-under Interrupt Enable
15261 * 0b0..Roll-under interrupt is disabled
15262 * 0b1..Roll-under interrupt is enabled
15263 */
15264#define QDC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIE_SHIFT)) & QDC_CTRL2_RUIE_MASK)
15265#define QDC_CTRL2_RUIRQ_MASK (0x20U)
15266#define QDC_CTRL2_RUIRQ_SHIFT (5U)
15267/* RUIRQ - Roll-under Interrupt Request
15268 * 0b0..No roll-under has occurred
15269 * 0b1..Roll-under has occurred
15270 */
15271#define QDC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIRQ_SHIFT)) & QDC_CTRL2_RUIRQ_MASK)
15272#define QDC_CTRL2_ROIE_MASK (0x40U)
15273#define QDC_CTRL2_ROIE_SHIFT (6U)
15274/* ROIE - Roll-over Interrupt Enable
15275 * 0b0..Roll-over interrupt is disabled
15276 * 0b1..Roll-over interrupt is enabled
15277 */
15278#define QDC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIE_SHIFT)) & QDC_CTRL2_ROIE_MASK)
15279#define QDC_CTRL2_ROIRQ_MASK (0x80U)
15280#define QDC_CTRL2_ROIRQ_SHIFT (7U)
15281/* ROIRQ - Roll-over Interrupt Request
15282 * 0b0..No roll-over has occurred
15283 * 0b1..Roll-over has occurred
15284 */
15285#define QDC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIRQ_SHIFT)) & QDC_CTRL2_ROIRQ_MASK)
15286#define QDC_CTRL2_REVMOD_MASK (0x100U)
15287#define QDC_CTRL2_REVMOD_SHIFT (8U)
15288/* REVMOD - Revolution Counter Modulus Enable
15289 * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV).
15290 * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV).
15291 */
15292#define QDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_REVMOD_SHIFT)) & QDC_CTRL2_REVMOD_MASK)
15293#define QDC_CTRL2_OUTCTL_MASK (0x200U)
15294#define QDC_CTRL2_OUTCTL_SHIFT (9U)
15295/* OUTCTL - Output Control
15296 * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP).
15297 * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.
15298 */
15299#define QDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_OUTCTL_SHIFT)) & QDC_CTRL2_OUTCTL_MASK)
15300#define QDC_CTRL2_SABIE_MASK (0x400U)
15301#define QDC_CTRL2_SABIE_SHIFT (10U)
15302/* SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
15303 * 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled.
15304 * 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled.
15305 */
15306#define QDC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIE_SHIFT)) & QDC_CTRL2_SABIE_MASK)
15307#define QDC_CTRL2_SABIRQ_MASK (0x800U)
15308#define QDC_CTRL2_SABIRQ_SHIFT (11U)
15309/* SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
15310 * 0b0..No simultaneous change of PHASEA and PHASEB has occurred.
15311 * 0b1..A simultaneous change of PHASEA and PHASEB has occurred.
15312 */
15313#define QDC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIRQ_SHIFT)) & QDC_CTRL2_SABIRQ_MASK)
15314/* @} */
15315
15316/* @name UMOD - Upper Modulus Register */
15317/* @{ */
15318#define QDC_UMOD_MOD_MASK (0xFFFFU)
15319#define QDC_UMOD_MOD_SHIFT (0U)
15320#define QDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_UMOD_MOD_SHIFT)) & QDC_UMOD_MOD_MASK)
15321/* @} */
15322
15323/* @name LMOD - Lower Modulus Register */
15324/* @{ */
15325#define QDC_LMOD_MOD_MASK (0xFFFFU)
15326#define QDC_LMOD_MOD_SHIFT (0U)
15327#define QDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_LMOD_MOD_SHIFT)) & QDC_LMOD_MOD_MASK)
15328/* @} */
15329
15330/* @name UCOMP - Upper Position Compare Register */
15331/* @{ */
15332#define QDC_UCOMP_COMP_MASK (0xFFFFU)
15333#define QDC_UCOMP_COMP_SHIFT (0U)
15334#define QDC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_UCOMP_COMP_SHIFT)) & QDC_UCOMP_COMP_MASK)
15335/* @} */
15336
15337/* @name LCOMP - Lower Position Compare Register */
15338/* @{ */
15339#define QDC_LCOMP_COMP_MASK (0xFFFFU)
15340#define QDC_LCOMP_COMP_SHIFT (0U)
15341#define QDC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_LCOMP_COMP_SHIFT)) & QDC_LCOMP_COMP_MASK)
15342/* @} */
15343
15344
15345/*
15346 * @}
15347 */ /* end of group QDC_Register_Masks */
15348
15349
15350/* QDC - Peripheral instance base addresses */
15351/* Peripheral QDC1 base address */
15352#define QDC1_BASE (0x403C8000u)
15353/* Peripheral QDC1 base pointer */
15354#define QDC1 ((QDC_Type *)QDC1_BASE)
15355/* Peripheral QDC2 base address */
15356#define QDC2_BASE (0x403CC000u)
15357/* Peripheral QDC2 base pointer */
15358#define QDC2 ((QDC_Type *)QDC2_BASE)
15359/* Peripheral QDC3 base address */
15360#define QDC3_BASE (0x403D0000u)
15361/* Peripheral QDC3 base pointer */
15362#define QDC3 ((QDC_Type *)QDC3_BASE)
15363/* Peripheral QDC4 base address */
15364#define QDC4_BASE (0x403D4000u)
15365/* Peripheral QDC4 base pointer */
15366#define QDC4 ((QDC_Type *)QDC4_BASE)
15367/* Array initializer of QDC peripheral base addresses */
15368#define QDC_BASE_ADDRS { 0u, QDC1_BASE, QDC2_BASE, QDC3_BASE, QDC4_BASE }
15369/* Array initializer of QDC peripheral base pointers */
15370#define QDC_BASE_PTRS { (QDC_Type *)0u, QDC1, QDC2, QDC3, QDC4 }
15371/* Interrupt vectors for the QDC peripheral type */
15372#define QDC_COMPARE_IRQS { NotAvail_IRQn, QDC1_IRQn, QDC2_IRQn, QDC3_IRQn, QDC4_IRQn }
15373#define QDC_HOME_IRQS { NotAvail_IRQn, QDC1_IRQn, QDC2_IRQn, QDC3_IRQn, QDC4_IRQn }
15374#define QDC_WDOG_IRQS { NotAvail_IRQn, QDC1_IRQn, QDC2_IRQn, QDC3_IRQn, QDC4_IRQn }
15375#define QDC_INDEX_IRQS { NotAvail_IRQn, QDC1_IRQn, QDC2_IRQn, QDC3_IRQn, QDC4_IRQn }
15376#define QDC_INPUT_SWITCH_IRQS { NotAvail_IRQn, QDC1_IRQn, QDC2_IRQn, QDC3_IRQn, QDC4_IRQn }
15377
15378/*
15379 * @}
15380 */ /* end of group QDC_Peripheral_Access_Layer */
15381
15382
15383/* ----------------------------------------------------------------------------
15384 -- ENET Peripheral Access Layer
15385 ---------------------------------------------------------------------------- */
15386
15387/*
15388 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
15389 * @{
15390 */
15391
15392/* ENET - Register Layout Typedef */
15393typedef struct {
15394 uint8_t RESERVED_0[4];
15395 __IO uint32_t EIR;
15396 __IO uint32_t EIMR;
15397 uint8_t RESERVED_1[4];
15398 __IO uint32_t RDAR;
15399 __IO uint32_t TDAR;
15400 uint8_t RESERVED_2[12];
15401 __IO uint32_t ECR;
15402 uint8_t RESERVED_3[24];
15403 __IO uint32_t MMFR;
15404 __IO uint32_t MSCR;
15405 uint8_t RESERVED_4[28];
15406 __IO uint32_t MIBC;
15407 uint8_t RESERVED_5[28];
15408 __IO uint32_t RCR;
15409 uint8_t RESERVED_6[60];
15410 __IO uint32_t TCR;
15411 uint8_t RESERVED_7[28];
15412 __IO uint32_t PALR;
15413 __IO uint32_t PAUR;
15414 __IO uint32_t OPD;
15415 __IO uint32_t TXIC;
15416 uint8_t RESERVED_8[12];
15417 __IO uint32_t RXIC;
15418 uint8_t RESERVED_9[20];
15419 __IO uint32_t IAUR;
15420 __IO uint32_t IALR;
15421 __IO uint32_t GAUR;
15422 __IO uint32_t GALR;
15423 uint8_t RESERVED_10[28];
15424 __IO uint32_t TFWR;
15425 uint8_t RESERVED_11[56];
15426 __IO uint32_t RDSR;
15427 __IO uint32_t TDSR;
15428 __IO uint32_t MRBR;
15429 uint8_t RESERVED_12[4];
15430 __IO uint32_t RSFL;
15431 __IO uint32_t RSEM;
15432 __IO uint32_t RAEM;
15433 __IO uint32_t RAFL;
15434 __IO uint32_t TSEM;
15435 __IO uint32_t TAEM;
15436 __IO uint32_t TAFL;
15437 __IO uint32_t TIPG;
15438 __IO uint32_t FTRL;
15439 uint8_t RESERVED_13[12];
15440 __IO uint32_t TACC;
15441 __IO uint32_t RACC;
15442 uint8_t RESERVED_14[56];
15443 uint32_t RMON_T_DROP;
15444 __I uint32_t RMON_T_PACKETS;
15445 __I uint32_t RMON_T_BC_PKT;
15446 __I uint32_t RMON_T_MC_PKT;
15447 __I uint32_t RMON_T_CRC_ALIGN;
15448 __I uint32_t RMON_T_UNDERSIZE;
15449 __I uint32_t RMON_T_OVERSIZE;
15450 __I uint32_t RMON_T_FRAG;
15451 __I uint32_t RMON_T_JAB;
15452 __I uint32_t RMON_T_COL;
15453 __I uint32_t RMON_T_P64;
15454 __I uint32_t RMON_T_P65TO127;
15455 __I uint32_t RMON_T_P128TO255;
15456 __I uint32_t RMON_T_P256TO511;
15457 __I uint32_t RMON_T_P512TO1023;
15458 __I uint32_t RMON_T_P1024TO2047;
15459 __I uint32_t RMON_T_P_GTE2048;
15460 __I uint32_t RMON_T_OCTETS;
15461 uint32_t IEEE_T_DROP;
15462 __I uint32_t IEEE_T_FRAME_OK;
15463 __I uint32_t IEEE_T_1COL;
15464 __I uint32_t IEEE_T_MCOL;
15465 __I uint32_t IEEE_T_DEF;
15466 __I uint32_t IEEE_T_LCOL;
15467 __I uint32_t IEEE_T_EXCOL;
15468 __I uint32_t IEEE_T_MACERR;
15469 __I uint32_t IEEE_T_CSERR;
15470 __I uint32_t IEEE_T_SQE;
15471 __I uint32_t IEEE_T_FDXFC;
15472 __I uint32_t IEEE_T_OCTETS_OK;
15473 uint8_t RESERVED_15[12];
15474 __I uint32_t RMON_R_PACKETS;
15475 __I uint32_t RMON_R_BC_PKT;
15476 __I uint32_t RMON_R_MC_PKT;
15477 __I uint32_t RMON_R_CRC_ALIGN;
15478 __I uint32_t RMON_R_UNDERSIZE;
15479 __I uint32_t RMON_R_OVERSIZE;
15480 __I uint32_t RMON_R_FRAG;
15481 __I uint32_t RMON_R_JAB;
15482 uint32_t RMON_R_RESVD_0;
15483 __I uint32_t RMON_R_P64;
15484 __I uint32_t RMON_R_P65TO127;
15485 __I uint32_t RMON_R_P128TO255;
15486 __I uint32_t RMON_R_P256TO511;
15487 __I uint32_t RMON_R_P512TO1023;
15488 __I uint32_t RMON_R_P1024TO2047;
15489 __I uint32_t RMON_R_P_GTE2048;
15490 __I uint32_t RMON_R_OCTETS;
15491 __I uint32_t IEEE_R_DROP;
15492 __I uint32_t IEEE_R_FRAME_OK;
15493 __I uint32_t IEEE_R_CRC;
15494 __I uint32_t IEEE_R_ALIGN;
15495 __I uint32_t IEEE_R_MACERR;
15496 __I uint32_t IEEE_R_FDXFC;
15497 __I uint32_t IEEE_R_OCTETS_OK;
15498 uint8_t RESERVED_16[284];
15499 __IO uint32_t ATCR;
15500 __IO uint32_t ATVR;
15501 __IO uint32_t ATOFF;
15502 __IO uint32_t ATPER;
15503 __IO uint32_t ATCOR;
15504 __IO uint32_t ATINC;
15505 __I uint32_t ATSTMP;
15506 uint8_t RESERVED_17[488];
15507 __IO uint32_t TGSR;
15508 struct { /* offset: 0x608, array step: 0x8 */
15509 __IO uint32_t TCSR;
15510 __IO uint32_t TCCR;
15511 } CHANNEL[4];
15512} ENET_Type;
15513
15514/* ----------------------------------------------------------------------------
15515 -- ENET Register Masks
15516 ---------------------------------------------------------------------------- */
15517
15518/*
15519 * @addtogroup ENET_Register_Masks ENET Register Masks
15520 * @{
15521 */
15522
15523/* @name EIR - Interrupt Event Register */
15524/* @{ */
15525#define ENET_EIR_TS_TIMER_MASK (0x8000U)
15526#define ENET_EIR_TS_TIMER_SHIFT (15U)
15527#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
15528#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
15529#define ENET_EIR_TS_AVAIL_SHIFT (16U)
15530#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
15531#define ENET_EIR_WAKEUP_MASK (0x20000U)
15532#define ENET_EIR_WAKEUP_SHIFT (17U)
15533#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
15534#define ENET_EIR_PLR_MASK (0x40000U)
15535#define ENET_EIR_PLR_SHIFT (18U)
15536#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
15537#define ENET_EIR_UN_MASK (0x80000U)
15538#define ENET_EIR_UN_SHIFT (19U)
15539#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
15540#define ENET_EIR_RL_MASK (0x100000U)
15541#define ENET_EIR_RL_SHIFT (20U)
15542#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
15543#define ENET_EIR_LC_MASK (0x200000U)
15544#define ENET_EIR_LC_SHIFT (21U)
15545#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
15546#define ENET_EIR_EBERR_MASK (0x400000U)
15547#define ENET_EIR_EBERR_SHIFT (22U)
15548#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
15549#define ENET_EIR_MII_MASK (0x800000U)
15550#define ENET_EIR_MII_SHIFT (23U)
15551#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
15552#define ENET_EIR_RXB_MASK (0x1000000U)
15553#define ENET_EIR_RXB_SHIFT (24U)
15554#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
15555#define ENET_EIR_RXF_MASK (0x2000000U)
15556#define ENET_EIR_RXF_SHIFT (25U)
15557#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
15558#define ENET_EIR_TXB_MASK (0x4000000U)
15559#define ENET_EIR_TXB_SHIFT (26U)
15560#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
15561#define ENET_EIR_TXF_MASK (0x8000000U)
15562#define ENET_EIR_TXF_SHIFT (27U)
15563#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
15564#define ENET_EIR_GRA_MASK (0x10000000U)
15565#define ENET_EIR_GRA_SHIFT (28U)
15566#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
15567#define ENET_EIR_BABT_MASK (0x20000000U)
15568#define ENET_EIR_BABT_SHIFT (29U)
15569#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
15570#define ENET_EIR_BABR_MASK (0x40000000U)
15571#define ENET_EIR_BABR_SHIFT (30U)
15572#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
15573/* @} */
15574
15575/* @name EIMR - Interrupt Mask Register */
15576/* @{ */
15577#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
15578#define ENET_EIMR_TS_TIMER_SHIFT (15U)
15579#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
15580#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
15581#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
15582#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
15583#define ENET_EIMR_WAKEUP_MASK (0x20000U)
15584#define ENET_EIMR_WAKEUP_SHIFT (17U)
15585#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
15586#define ENET_EIMR_PLR_MASK (0x40000U)
15587#define ENET_EIMR_PLR_SHIFT (18U)
15588#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
15589#define ENET_EIMR_UN_MASK (0x80000U)
15590#define ENET_EIMR_UN_SHIFT (19U)
15591#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
15592#define ENET_EIMR_RL_MASK (0x100000U)
15593#define ENET_EIMR_RL_SHIFT (20U)
15594#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
15595#define ENET_EIMR_LC_MASK (0x200000U)
15596#define ENET_EIMR_LC_SHIFT (21U)
15597#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
15598#define ENET_EIMR_EBERR_MASK (0x400000U)
15599#define ENET_EIMR_EBERR_SHIFT (22U)
15600#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
15601#define ENET_EIMR_MII_MASK (0x800000U)
15602#define ENET_EIMR_MII_SHIFT (23U)
15603#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
15604#define ENET_EIMR_RXB_MASK (0x1000000U)
15605#define ENET_EIMR_RXB_SHIFT (24U)
15606#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
15607#define ENET_EIMR_RXF_MASK (0x2000000U)
15608#define ENET_EIMR_RXF_SHIFT (25U)
15609#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
15610#define ENET_EIMR_TXB_MASK (0x4000000U)
15611#define ENET_EIMR_TXB_SHIFT (26U)
15612/* TXB - TXB Interrupt Mask
15613 * 0b0..The corresponding interrupt source is masked.
15614 * 0b1..The corresponding interrupt source is not masked.
15615 */
15616#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
15617#define ENET_EIMR_TXF_MASK (0x8000000U)
15618#define ENET_EIMR_TXF_SHIFT (27U)
15619/* TXF - TXF Interrupt Mask
15620 * 0b0..The corresponding interrupt source is masked.
15621 * 0b1..The corresponding interrupt source is not masked.
15622 */
15623#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
15624#define ENET_EIMR_GRA_MASK (0x10000000U)
15625#define ENET_EIMR_GRA_SHIFT (28U)
15626/* GRA - GRA Interrupt Mask
15627 * 0b0..The corresponding interrupt source is masked.
15628 * 0b1..The corresponding interrupt source is not masked.
15629 */
15630#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
15631#define ENET_EIMR_BABT_MASK (0x20000000U)
15632#define ENET_EIMR_BABT_SHIFT (29U)
15633/* BABT - BABT Interrupt Mask
15634 * 0b0..The corresponding interrupt source is masked.
15635 * 0b1..The corresponding interrupt source is not masked.
15636 */
15637#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
15638#define ENET_EIMR_BABR_MASK (0x40000000U)
15639#define ENET_EIMR_BABR_SHIFT (30U)
15640/* BABR - BABR Interrupt Mask
15641 * 0b0..The corresponding interrupt source is masked.
15642 * 0b1..The corresponding interrupt source is not masked.
15643 */
15644#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
15645/* @} */
15646
15647/* @name RDAR - Receive Descriptor Active Register */
15648/* @{ */
15649#define ENET_RDAR_RDAR_MASK (0x1000000U)
15650#define ENET_RDAR_RDAR_SHIFT (24U)
15651#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
15652/* @} */
15653
15654/* @name TDAR - Transmit Descriptor Active Register */
15655/* @{ */
15656#define ENET_TDAR_TDAR_MASK (0x1000000U)
15657#define ENET_TDAR_TDAR_SHIFT (24U)
15658#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
15659/* @} */
15660
15661/* @name ECR - Ethernet Control Register */
15662/* @{ */
15663#define ENET_ECR_RESET_MASK (0x1U)
15664#define ENET_ECR_RESET_SHIFT (0U)
15665#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
15666#define ENET_ECR_ETHEREN_MASK (0x2U)
15667#define ENET_ECR_ETHEREN_SHIFT (1U)
15668/* ETHEREN - Ethernet Enable
15669 * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
15670 * 0b1..MAC is enabled, and reception and transmission are possible.
15671 */
15672#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
15673#define ENET_ECR_MAGICEN_MASK (0x4U)
15674#define ENET_ECR_MAGICEN_SHIFT (2U)
15675/* MAGICEN - Magic Packet Detection Enable
15676 * 0b0..Magic detection logic disabled.
15677 * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
15678 */
15679#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
15680#define ENET_ECR_SLEEP_MASK (0x8U)
15681#define ENET_ECR_SLEEP_SHIFT (3U)
15682/* SLEEP - Sleep Mode Enable
15683 * 0b0..Normal operating mode.
15684 * 0b1..Sleep mode.
15685 */
15686#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
15687#define ENET_ECR_EN1588_MASK (0x10U)
15688#define ENET_ECR_EN1588_SHIFT (4U)
15689/* EN1588 - EN1588 Enable
15690 * 0b0..Legacy FEC buffer descriptors and functions enabled.
15691 * 0b1..Enhanced frame time-stamping functions enabled.
15692 */
15693#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
15694#define ENET_ECR_DBGEN_MASK (0x40U)
15695#define ENET_ECR_DBGEN_SHIFT (6U)
15696/* DBGEN - Debug Enable
15697 * 0b0..MAC continues operation in debug mode.
15698 * 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
15699 */
15700#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
15701#define ENET_ECR_DBSWP_MASK (0x100U)
15702#define ENET_ECR_DBSWP_SHIFT (8U)
15703/* DBSWP - Descriptor Byte Swapping Enable
15704 * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
15705 * 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
15706 */
15707#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
15708/* @} */
15709
15710/* @name MMFR - MII Management Frame Register */
15711/* @{ */
15712#define ENET_MMFR_DATA_MASK (0xFFFFU)
15713#define ENET_MMFR_DATA_SHIFT (0U)
15714#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
15715#define ENET_MMFR_TA_MASK (0x30000U)
15716#define ENET_MMFR_TA_SHIFT (16U)
15717#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
15718#define ENET_MMFR_RA_MASK (0x7C0000U)
15719#define ENET_MMFR_RA_SHIFT (18U)
15720#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
15721#define ENET_MMFR_PA_MASK (0xF800000U)
15722#define ENET_MMFR_PA_SHIFT (23U)
15723#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
15724#define ENET_MMFR_OP_MASK (0x30000000U)
15725#define ENET_MMFR_OP_SHIFT (28U)
15726#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
15727#define ENET_MMFR_ST_MASK (0xC0000000U)
15728#define ENET_MMFR_ST_SHIFT (30U)
15729#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
15730/* @} */
15731
15732/* @name MSCR - MII Speed Control Register */
15733/* @{ */
15734#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
15735#define ENET_MSCR_MII_SPEED_SHIFT (1U)
15736#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
15737#define ENET_MSCR_DIS_PRE_MASK (0x80U)
15738#define ENET_MSCR_DIS_PRE_SHIFT (7U)
15739/* DIS_PRE - Disable Preamble
15740 * 0b0..Preamble enabled.
15741 * 0b1..Preamble (32 ones) is not prepended to the MII management frame.
15742 */
15743#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
15744#define ENET_MSCR_HOLDTIME_MASK (0x700U)
15745#define ENET_MSCR_HOLDTIME_SHIFT (8U)
15746/* HOLDTIME - Hold time On MDIO Output
15747 * 0b000..1 internal module clock cycle
15748 * 0b001..2 internal module clock cycles
15749 * 0b010..3 internal module clock cycles
15750 * 0b111..8 internal module clock cycles
15751 */
15752#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
15753/* @} */
15754
15755/* @name MIBC - MIB Control Register */
15756/* @{ */
15757#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
15758#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
15759/* MIB_CLEAR - MIB Clear
15760 * 0b0..See note above.
15761 * 0b1..All statistics counters are reset to 0.
15762 */
15763#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
15764#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
15765#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
15766/* MIB_IDLE - MIB Idle
15767 * 0b0..The MIB block is updating MIB counters.
15768 * 0b1..The MIB block is not currently updating any MIB counters.
15769 */
15770#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
15771#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
15772#define ENET_MIBC_MIB_DIS_SHIFT (31U)
15773/* MIB_DIS - Disable MIB Logic
15774 * 0b0..MIB logic is enabled.
15775 * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
15776 */
15777#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
15778/* @} */
15779
15780/* @name RCR - Receive Control Register */
15781/* @{ */
15782#define ENET_RCR_LOOP_MASK (0x1U)
15783#define ENET_RCR_LOOP_SHIFT (0U)
15784/* LOOP - Internal Loopback
15785 * 0b0..Loopback disabled.
15786 * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
15787 */
15788#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
15789#define ENET_RCR_DRT_MASK (0x2U)
15790#define ENET_RCR_DRT_SHIFT (1U)
15791/* DRT - Disable Receive On Transmit
15792 * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
15793 * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
15794 */
15795#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
15796#define ENET_RCR_MII_MODE_MASK (0x4U)
15797#define ENET_RCR_MII_MODE_SHIFT (2U)
15798/* MII_MODE - Media Independent Interface Mode
15799 * 0b0..Reserved.
15800 * 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
15801 */
15802#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
15803#define ENET_RCR_PROM_MASK (0x8U)
15804#define ENET_RCR_PROM_SHIFT (3U)
15805/* PROM - Promiscuous Mode
15806 * 0b0..Disabled.
15807 * 0b1..Enabled.
15808 */
15809#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
15810#define ENET_RCR_BC_REJ_MASK (0x10U)
15811#define ENET_RCR_BC_REJ_SHIFT (4U)
15812#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
15813#define ENET_RCR_FCE_MASK (0x20U)
15814#define ENET_RCR_FCE_SHIFT (5U)
15815#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
15816#define ENET_RCR_RMII_MODE_MASK (0x100U)
15817#define ENET_RCR_RMII_MODE_SHIFT (8U)
15818/* RMII_MODE - RMII Mode Enable
15819 * 0b0..MAC configured for MII mode.
15820 * 0b1..MAC configured for RMII operation.
15821 */
15822#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
15823#define ENET_RCR_RMII_10T_MASK (0x200U)
15824#define ENET_RCR_RMII_10T_SHIFT (9U)
15825/* RMII_10T
15826 * 0b0..100-Mbit/s operation.
15827 * 0b1..10-Mbit/s operation.
15828 */
15829#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
15830#define ENET_RCR_PADEN_MASK (0x1000U)
15831#define ENET_RCR_PADEN_SHIFT (12U)
15832/* PADEN - Enable Frame Padding Remove On Receive
15833 * 0b0..No padding is removed on receive by the MAC.
15834 * 0b1..Padding is removed from received frames.
15835 */
15836#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
15837#define ENET_RCR_PAUFWD_MASK (0x2000U)
15838#define ENET_RCR_PAUFWD_SHIFT (13U)
15839/* PAUFWD - Terminate/Forward Pause Frames
15840 * 0b0..Pause frames are terminated and discarded in the MAC.
15841 * 0b1..Pause frames are forwarded to the user application.
15842 */
15843#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
15844#define ENET_RCR_CRCFWD_MASK (0x4000U)
15845#define ENET_RCR_CRCFWD_SHIFT (14U)
15846/* CRCFWD - Terminate/Forward Received CRC
15847 * 0b0..The CRC field of received frames is transmitted to the user application.
15848 * 0b1..The CRC field is stripped from the frame.
15849 */
15850#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
15851#define ENET_RCR_CFEN_MASK (0x8000U)
15852#define ENET_RCR_CFEN_SHIFT (15U)
15853/* CFEN - MAC Control Frame Enable
15854 * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
15855 * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
15856 */
15857#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
15858#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
15859#define ENET_RCR_MAX_FL_SHIFT (16U)
15860#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
15861#define ENET_RCR_NLC_MASK (0x40000000U)
15862#define ENET_RCR_NLC_SHIFT (30U)
15863/* NLC - Payload Length Check Disable
15864 * 0b0..The payload length check is disabled.
15865 * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
15866 */
15867#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
15868#define ENET_RCR_GRS_MASK (0x80000000U)
15869#define ENET_RCR_GRS_SHIFT (31U)
15870#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
15871/* @} */
15872
15873/* @name TCR - Transmit Control Register */
15874/* @{ */
15875#define ENET_TCR_GTS_MASK (0x1U)
15876#define ENET_TCR_GTS_SHIFT (0U)
15877#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
15878#define ENET_TCR_FDEN_MASK (0x4U)
15879#define ENET_TCR_FDEN_SHIFT (2U)
15880#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
15881#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
15882#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
15883/* TFC_PAUSE - Transmit Frame Control Pause
15884 * 0b0..No PAUSE frame transmitted.
15885 * 0b1..The MAC stops transmission of data frames after the current transmission is complete.
15886 */
15887#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
15888#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
15889#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
15890#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
15891#define ENET_TCR_ADDSEL_MASK (0xE0U)
15892#define ENET_TCR_ADDSEL_SHIFT (5U)
15893/* ADDSEL - Source MAC Address Select On Transmit
15894 * 0b000..Node MAC address programmed on PADDR1/2 registers.
15895 * 0b100..Reserved.
15896 * 0b101..Reserved.
15897 * 0b110..Reserved.
15898 */
15899#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
15900#define ENET_TCR_ADDINS_MASK (0x100U)
15901#define ENET_TCR_ADDINS_SHIFT (8U)
15902/* ADDINS - Set MAC Address On Transmit
15903 * 0b0..The source MAC address is not modified by the MAC.
15904 * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
15905 */
15906#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
15907#define ENET_TCR_CRCFWD_MASK (0x200U)
15908#define ENET_TCR_CRCFWD_SHIFT (9U)
15909/* CRCFWD - Forward Frame From Application With CRC
15910 * 0b0..TxBD[TC] controls whether the frame has a CRC from the application.
15911 * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
15912 */
15913#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
15914/* @} */
15915
15916/* @name PALR - Physical Address Lower Register */
15917/* @{ */
15918#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
15919#define ENET_PALR_PADDR1_SHIFT (0U)
15920#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
15921/* @} */
15922
15923/* @name PAUR - Physical Address Upper Register */
15924/* @{ */
15925#define ENET_PAUR_TYPE_MASK (0xFFFFU)
15926#define ENET_PAUR_TYPE_SHIFT (0U)
15927#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
15928#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
15929#define ENET_PAUR_PADDR2_SHIFT (16U)
15930#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
15931/* @} */
15932
15933/* @name OPD - Opcode/Pause Duration Register */
15934/* @{ */
15935#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
15936#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
15937#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
15938#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
15939#define ENET_OPD_OPCODE_SHIFT (16U)
15940#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
15941/* @} */
15942
15943/* @name TXIC - Transmit Interrupt Coalescing Register */
15944/* @{ */
15945#define ENET_TXIC_ICTT_MASK (0xFFFFU)
15946#define ENET_TXIC_ICTT_SHIFT (0U)
15947#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
15948#define ENET_TXIC_ICFT_MASK (0xFF00000U)
15949#define ENET_TXIC_ICFT_SHIFT (20U)
15950#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
15951#define ENET_TXIC_ICCS_MASK (0x40000000U)
15952#define ENET_TXIC_ICCS_SHIFT (30U)
15953/* ICCS - Interrupt Coalescing Timer Clock Source Select
15954 * 0b0..Use MII/GMII TX clocks.
15955 * 0b1..Use ENET system clock.
15956 */
15957#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
15958#define ENET_TXIC_ICEN_MASK (0x80000000U)
15959#define ENET_TXIC_ICEN_SHIFT (31U)
15960/* ICEN - Interrupt Coalescing Enable
15961 * 0b0..Disable Interrupt coalescing.
15962 * 0b1..Enable Interrupt coalescing.
15963 */
15964#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
15965/* @} */
15966
15967/* @name RXIC - Receive Interrupt Coalescing Register */
15968/* @{ */
15969#define ENET_RXIC_ICTT_MASK (0xFFFFU)
15970#define ENET_RXIC_ICTT_SHIFT (0U)
15971#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
15972#define ENET_RXIC_ICFT_MASK (0xFF00000U)
15973#define ENET_RXIC_ICFT_SHIFT (20U)
15974#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
15975#define ENET_RXIC_ICCS_MASK (0x40000000U)
15976#define ENET_RXIC_ICCS_SHIFT (30U)
15977/* ICCS - Interrupt Coalescing Timer Clock Source Select
15978 * 0b0..Use MII/GMII TX clocks.
15979 * 0b1..Use ENET system clock.
15980 */
15981#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
15982#define ENET_RXIC_ICEN_MASK (0x80000000U)
15983#define ENET_RXIC_ICEN_SHIFT (31U)
15984/* ICEN - Interrupt Coalescing Enable
15985 * 0b0..Disable Interrupt coalescing.
15986 * 0b1..Enable Interrupt coalescing.
15987 */
15988#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
15989/* @} */
15990
15991/* @name IAUR - Descriptor Individual Upper Address Register */
15992/* @{ */
15993#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
15994#define ENET_IAUR_IADDR1_SHIFT (0U)
15995#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
15996/* @} */
15997
15998/* @name IALR - Descriptor Individual Lower Address Register */
15999/* @{ */
16000#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
16001#define ENET_IALR_IADDR2_SHIFT (0U)
16002#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
16003/* @} */
16004
16005/* @name GAUR - Descriptor Group Upper Address Register */
16006/* @{ */
16007#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
16008#define ENET_GAUR_GADDR1_SHIFT (0U)
16009#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
16010/* @} */
16011
16012/* @name GALR - Descriptor Group Lower Address Register */
16013/* @{ */
16014#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
16015#define ENET_GALR_GADDR2_SHIFT (0U)
16016#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
16017/* @} */
16018
16019/* @name TFWR - Transmit FIFO Watermark Register */
16020/* @{ */
16021#define ENET_TFWR_TFWR_MASK (0x3FU)
16022#define ENET_TFWR_TFWR_SHIFT (0U)
16023/* TFWR - Transmit FIFO Write
16024 * 0b000000..64 bytes written.
16025 * 0b000001..64 bytes written.
16026 * 0b000010..128 bytes written.
16027 * 0b000011..192 bytes written.
16028 * 0b011111..1984 bytes written.
16029 */
16030#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
16031#define ENET_TFWR_STRFWD_MASK (0x100U)
16032#define ENET_TFWR_STRFWD_SHIFT (8U)
16033/* STRFWD - Store And Forward Enable
16034 * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
16035 * 0b1..Enabled.
16036 */
16037#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
16038/* @} */
16039
16040/* @name RDSR - Receive Descriptor Ring Start Register */
16041/* @{ */
16042#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
16043#define ENET_RDSR_R_DES_START_SHIFT (3U)
16044#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
16045/* @} */
16046
16047/* @name TDSR - Transmit Buffer Descriptor Ring Start Register */
16048/* @{ */
16049#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
16050#define ENET_TDSR_X_DES_START_SHIFT (3U)
16051#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
16052/* @} */
16053
16054/* @name MRBR - Maximum Receive Buffer Size Register */
16055/* @{ */
16056#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
16057#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
16058#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
16059/* @} */
16060
16061/* @name RSFL - Receive FIFO Section Full Threshold */
16062/* @{ */
16063#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
16064#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
16065#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
16066/* @} */
16067
16068/* @name RSEM - Receive FIFO Section Empty Threshold */
16069/* @{ */
16070#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
16071#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
16072#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
16073#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
16074#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
16075#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
16076/* @} */
16077
16078/* @name RAEM - Receive FIFO Almost Empty Threshold */
16079/* @{ */
16080#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
16081#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
16082#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
16083/* @} */
16084
16085/* @name RAFL - Receive FIFO Almost Full Threshold */
16086/* @{ */
16087#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
16088#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
16089#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
16090/* @} */
16091
16092/* @name TSEM - Transmit FIFO Section Empty Threshold */
16093/* @{ */
16094#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
16095#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
16096#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
16097/* @} */
16098
16099/* @name TAEM - Transmit FIFO Almost Empty Threshold */
16100/* @{ */
16101#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
16102#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
16103#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
16104/* @} */
16105
16106/* @name TAFL - Transmit FIFO Almost Full Threshold */
16107/* @{ */
16108#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
16109#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
16110#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
16111/* @} */
16112
16113/* @name TIPG - Transmit Inter-Packet Gap */
16114/* @{ */
16115#define ENET_TIPG_IPG_MASK (0x1FU)
16116#define ENET_TIPG_IPG_SHIFT (0U)
16117#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
16118/* @} */
16119
16120/* @name FTRL - Frame Truncation Length */
16121/* @{ */
16122#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
16123#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
16124#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
16125/* @} */
16126
16127/* @name TACC - Transmit Accelerator Function Configuration */
16128/* @{ */
16129#define ENET_TACC_SHIFT16_MASK (0x1U)
16130#define ENET_TACC_SHIFT16_SHIFT (0U)
16131/* SHIFT16 - TX FIFO Shift-16
16132 * 0b0..Disabled.
16133 * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
16134 * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
16135 * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
16136 * extended to a 16-byte header.
16137 */
16138#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
16139#define ENET_TACC_IPCHK_MASK (0x8U)
16140#define ENET_TACC_IPCHK_SHIFT (3U)
16141/* IPCHK
16142 * 0b0..Checksum is not inserted.
16143 * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
16144 * be cleared. If a non-IP frame is transmitted the frame is not modified.
16145 */
16146#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
16147#define ENET_TACC_PROCHK_MASK (0x10U)
16148#define ENET_TACC_PROCHK_SHIFT (4U)
16149/* PROCHK
16150 * 0b0..Checksum not inserted.
16151 * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
16152 * frame. The checksum field must be cleared. The other frames are not modified.
16153 */
16154#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
16155/* @} */
16156
16157/* @name RACC - Receive Accelerator Function Configuration */
16158/* @{ */
16159#define ENET_RACC_PADREM_MASK (0x1U)
16160#define ENET_RACC_PADREM_SHIFT (0U)
16161/* PADREM - Enable Padding Removal For Short IP Frames
16162 * 0b0..Padding not removed.
16163 * 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
16164 */
16165#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
16166#define ENET_RACC_IPDIS_MASK (0x2U)
16167#define ENET_RACC_IPDIS_SHIFT (1U)
16168/* IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
16169 * 0b0..Frames with wrong IPv4 header checksum are not discarded.
16170 * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
16171 * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
16172 * store and forward mode (RSFL cleared).
16173 */
16174#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
16175#define ENET_RACC_PRODIS_MASK (0x4U)
16176#define ENET_RACC_PRODIS_SHIFT (2U)
16177/* PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
16178 * 0b0..Frames with wrong checksum are not discarded.
16179 * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
16180 * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
16181 * cleared).
16182 */
16183#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
16184#define ENET_RACC_LINEDIS_MASK (0x40U)
16185#define ENET_RACC_LINEDIS_SHIFT (6U)
16186/* LINEDIS - Enable Discard Of Frames With MAC Layer Errors
16187 * 0b0..Frames with errors are not discarded.
16188 * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
16189 */
16190#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
16191#define ENET_RACC_SHIFT16_MASK (0x80U)
16192#define ENET_RACC_SHIFT16_SHIFT (7U)
16193/* SHIFT16 - RX FIFO Shift-16
16194 * 0b0..Disabled.
16195 * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
16196 */
16197#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
16198/* @} */
16199
16200/* @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
16201/* @{ */
16202#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
16203#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
16204#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
16205/* @} */
16206
16207/* @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
16208/* @{ */
16209#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
16210#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
16211#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
16212/* @} */
16213
16214/* @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
16215/* @{ */
16216#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
16217#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
16218#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
16219/* @} */
16220
16221/* @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
16222/* @{ */
16223#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
16224#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
16225#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
16226/* @} */
16227
16228/* @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
16229/* @{ */
16230#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
16231#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
16232#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
16233/* @} */
16234
16235/* @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
16236/* @{ */
16237#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
16238#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
16239#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
16240/* @} */
16241
16242/* @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
16243/* @{ */
16244#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
16245#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
16246#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
16247/* @} */
16248
16249/* @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
16250/* @{ */
16251#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
16252#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
16253#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
16254/* @} */
16255
16256/* @name RMON_T_COL - Tx Collision Count Statistic Register */
16257/* @{ */
16258#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
16259#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
16260#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
16261/* @} */
16262
16263/* @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
16264/* @{ */
16265#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
16266#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
16267#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
16268/* @} */
16269
16270/* @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
16271/* @{ */
16272#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
16273#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
16274#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
16275/* @} */
16276
16277/* @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
16278/* @{ */
16279#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
16280#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
16281#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
16282/* @} */
16283
16284/* @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
16285/* @{ */
16286#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
16287#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
16288#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
16289/* @} */
16290
16291/* @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
16292/* @{ */
16293#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
16294#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
16295#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
16296/* @} */
16297
16298/* @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
16299/* @{ */
16300#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
16301#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
16302#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
16303/* @} */
16304
16305/* @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
16306/* @{ */
16307#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
16308#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
16309#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
16310/* @} */
16311
16312/* @name RMON_T_OCTETS - Tx Octets Statistic Register */
16313/* @{ */
16314#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
16315#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
16316#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
16317/* @} */
16318
16319/* @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
16320/* @{ */
16321#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
16322#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
16323#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
16324/* @} */
16325
16326/* @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
16327/* @{ */
16328#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
16329#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
16330#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
16331/* @} */
16332
16333/* @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
16334/* @{ */
16335#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
16336#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
16337#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
16338/* @} */
16339
16340/* @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
16341/* @{ */
16342#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
16343#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
16344#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
16345/* @} */
16346
16347/* @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
16348/* @{ */
16349#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
16350#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
16351#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
16352/* @} */
16353
16354/* @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
16355/* @{ */
16356#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
16357#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
16358#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
16359/* @} */
16360
16361/* @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
16362/* @{ */
16363#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
16364#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
16365#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
16366/* @} */
16367
16368/* @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
16369/* @{ */
16370#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
16371#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
16372#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
16373/* @} */
16374
16375/* @name IEEE_T_SQE - Reserved Statistic Register */
16376/* @{ */
16377#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
16378#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
16379#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
16380/* @} */
16381
16382/* @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
16383/* @{ */
16384#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
16385#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
16386#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
16387/* @} */
16388
16389/* @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
16390/* @{ */
16391#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
16392#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
16393#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
16394/* @} */
16395
16396/* @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
16397/* @{ */
16398#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
16399#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
16400#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
16401/* @} */
16402
16403/* @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
16404/* @{ */
16405#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
16406#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
16407#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
16408/* @} */
16409
16410/* @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
16411/* @{ */
16412#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
16413#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
16414#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
16415/* @} */
16416
16417/* @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
16418/* @{ */
16419#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
16420#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
16421#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
16422/* @} */
16423
16424/* @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
16425/* @{ */
16426#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
16427#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
16428#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
16429/* @} */
16430
16431/* @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
16432/* @{ */
16433#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
16434#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
16435#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
16436/* @} */
16437
16438/* @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
16439/* @{ */
16440#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
16441#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
16442#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
16443/* @} */
16444
16445/* @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
16446/* @{ */
16447#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
16448#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
16449#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
16450/* @} */
16451
16452/* @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
16453/* @{ */
16454#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
16455#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
16456#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
16457/* @} */
16458
16459/* @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
16460/* @{ */
16461#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
16462#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
16463#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
16464/* @} */
16465
16466/* @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
16467/* @{ */
16468#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
16469#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
16470#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
16471/* @} */
16472
16473/* @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
16474/* @{ */
16475#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
16476#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
16477#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
16478/* @} */
16479
16480/* @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
16481/* @{ */
16482#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
16483#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
16484#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
16485/* @} */
16486
16487/* @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
16488/* @{ */
16489#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
16490#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
16491#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
16492/* @} */
16493
16494/* @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
16495/* @{ */
16496#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
16497#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
16498#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
16499/* @} */
16500
16501/* @name RMON_R_OCTETS - Rx Octets Statistic Register */
16502/* @{ */
16503#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
16504#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
16505#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
16506/* @} */
16507
16508/* @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
16509/* @{ */
16510#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
16511#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
16512#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
16513/* @} */
16514
16515/* @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
16516/* @{ */
16517#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
16518#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
16519#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
16520/* @} */
16521
16522/* @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
16523/* @{ */
16524#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
16525#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
16526#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
16527/* @} */
16528
16529/* @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
16530/* @{ */
16531#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
16532#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
16533#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
16534/* @} */
16535
16536/* @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
16537/* @{ */
16538#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
16539#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
16540#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
16541/* @} */
16542
16543/* @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
16544/* @{ */
16545#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
16546#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
16547#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
16548/* @} */
16549
16550/* @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
16551/* @{ */
16552#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
16553#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
16554#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
16555/* @} */
16556
16557/* @name ATCR - Adjustable Timer Control Register */
16558/* @{ */
16559#define ENET_ATCR_EN_MASK (0x1U)
16560#define ENET_ATCR_EN_SHIFT (0U)
16561/* EN - Enable Timer
16562 * 0b0..The timer stops at the current value.
16563 * 0b1..The timer starts incrementing.
16564 */
16565#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
16566#define ENET_ATCR_OFFEN_MASK (0x4U)
16567#define ENET_ATCR_OFFEN_SHIFT (2U)
16568/* OFFEN - Enable One-Shot Offset Event
16569 * 0b0..Disable.
16570 * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
16571 * when the offset event is reached, so no further event occurs until the field is set again. The timer
16572 * offset value must be set before setting this field.
16573 */
16574#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
16575#define ENET_ATCR_OFFRST_MASK (0x8U)
16576#define ENET_ATCR_OFFRST_SHIFT (3U)
16577/* OFFRST - Reset Timer On Offset Event
16578 * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
16579 * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
16580 */
16581#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
16582#define ENET_ATCR_PEREN_MASK (0x10U)
16583#define ENET_ATCR_PEREN_SHIFT (4U)
16584/* PEREN - Enable Periodical Event
16585 * 0b0..Disable.
16586 * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
16587 * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
16588 * setting this bit. Not all devices contain the event signal output. See the chip configuration details.
16589 */
16590#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
16591#define ENET_ATCR_PINPER_MASK (0x80U)
16592#define ENET_ATCR_PINPER_SHIFT (7U)
16593/* PINPER
16594 * 0b0..Disable.
16595 * 0b1..Enable.
16596 */
16597#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
16598#define ENET_ATCR_RESTART_MASK (0x200U)
16599#define ENET_ATCR_RESTART_SHIFT (9U)
16600#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
16601#define ENET_ATCR_CAPTURE_MASK (0x800U)
16602#define ENET_ATCR_CAPTURE_SHIFT (11U)
16603/* CAPTURE - Capture Timer Value
16604 * 0b0..No effect.
16605 * 0b1..The current time is captured and can be read from the ATVR register.
16606 */
16607#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
16608#define ENET_ATCR_SLAVE_MASK (0x2000U)
16609#define ENET_ATCR_SLAVE_SHIFT (13U)
16610/* SLAVE - Enable Timer Slave Mode
16611 * 0b0..The timer is active and all configuration fields in this register are relevant.
16612 * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
16613 * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
16614 */
16615#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
16616/* @} */
16617
16618/* @name ATVR - Timer Value Register */
16619/* @{ */
16620#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
16621#define ENET_ATVR_ATIME_SHIFT (0U)
16622#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
16623/* @} */
16624
16625/* @name ATOFF - Timer Offset Register */
16626/* @{ */
16627#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
16628#define ENET_ATOFF_OFFSET_SHIFT (0U)
16629#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
16630/* @} */
16631
16632/* @name ATPER - Timer Period Register */
16633/* @{ */
16634#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
16635#define ENET_ATPER_PERIOD_SHIFT (0U)
16636#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
16637/* @} */
16638
16639/* @name ATCOR - Timer Correction Register */
16640/* @{ */
16641#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
16642#define ENET_ATCOR_COR_SHIFT (0U)
16643#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
16644/* @} */
16645
16646/* @name ATINC - Time-Stamping Clock Period Register */
16647/* @{ */
16648#define ENET_ATINC_INC_MASK (0x7FU)
16649#define ENET_ATINC_INC_SHIFT (0U)
16650#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
16651#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
16652#define ENET_ATINC_INC_CORR_SHIFT (8U)
16653#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
16654/* @} */
16655
16656/* @name ATSTMP - Timestamp of Last Transmitted Frame */
16657/* @{ */
16658#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
16659#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
16660#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
16661/* @} */
16662
16663/* @name TGSR - Timer Global Status Register */
16664/* @{ */
16665#define ENET_TGSR_TF0_MASK (0x1U)
16666#define ENET_TGSR_TF0_SHIFT (0U)
16667/* TF0 - Copy Of Timer Flag For Channel 0
16668 * 0b0..Timer Flag for Channel 0 is clear
16669 * 0b1..Timer Flag for Channel 0 is set
16670 */
16671#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
16672#define ENET_TGSR_TF1_MASK (0x2U)
16673#define ENET_TGSR_TF1_SHIFT (1U)
16674/* TF1 - Copy Of Timer Flag For Channel 1
16675 * 0b0..Timer Flag for Channel 1 is clear
16676 * 0b1..Timer Flag for Channel 1 is set
16677 */
16678#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
16679#define ENET_TGSR_TF2_MASK (0x4U)
16680#define ENET_TGSR_TF2_SHIFT (2U)
16681/* TF2 - Copy Of Timer Flag For Channel 2
16682 * 0b0..Timer Flag for Channel 2 is clear
16683 * 0b1..Timer Flag for Channel 2 is set
16684 */
16685#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
16686#define ENET_TGSR_TF3_MASK (0x8U)
16687#define ENET_TGSR_TF3_SHIFT (3U)
16688/* TF3 - Copy Of Timer Flag For Channel 3
16689 * 0b0..Timer Flag for Channel 3 is clear
16690 * 0b1..Timer Flag for Channel 3 is set
16691 */
16692#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
16693/* @} */
16694
16695/* @name TCSR - Timer Control Status Register */
16696/* @{ */
16697#define ENET_TCSR_TDRE_MASK (0x1U)
16698#define ENET_TCSR_TDRE_SHIFT (0U)
16699/* TDRE - Timer DMA Request Enable
16700 * 0b0..DMA request is disabled
16701 * 0b1..DMA request is enabled
16702 */
16703#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
16704#define ENET_TCSR_TMODE_MASK (0x3CU)
16705#define ENET_TCSR_TMODE_SHIFT (2U)
16706/* TMODE - Timer Mode
16707 * 0b0000..Timer Channel is disabled.
16708 * 0b0001..Timer Channel is configured for Input Capture on rising edge.
16709 * 0b0010..Timer Channel is configured for Input Capture on falling edge.
16710 * 0b0011..Timer Channel is configured for Input Capture on both edges.
16711 * 0b0100..Timer Channel is configured for Output Compare - software only.
16712 * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
16713 * 0b0110..Timer Channel is configured for Output Compare - clear output on compare.
16714 * 0b0111..Timer Channel is configured for Output Compare - set output on compare.
16715 * 0b1000..Reserved
16716 * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
16717 * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
16718 * 0b110x..Reserved
16719 * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
16720 * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
16721 */
16722#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
16723#define ENET_TCSR_TIE_MASK (0x40U)
16724#define ENET_TCSR_TIE_SHIFT (6U)
16725/* TIE - Timer Interrupt Enable
16726 * 0b0..Interrupt is disabled
16727 * 0b1..Interrupt is enabled
16728 */
16729#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
16730#define ENET_TCSR_TF_MASK (0x80U)
16731#define ENET_TCSR_TF_SHIFT (7U)
16732/* TF - Timer Flag
16733 * 0b0..Input Capture or Output Compare has not occurred.
16734 * 0b1..Input Capture or Output Compare has occurred.
16735 */
16736#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
16737#define ENET_TCSR_TPWC_MASK (0xF800U)
16738#define ENET_TCSR_TPWC_SHIFT (11U)
16739/* TPWC - Timer PulseWidth Control
16740 * 0b00000..Pulse width is one 1588-clock cycle.
16741 * 0b00001..Pulse width is two 1588-clock cycles.
16742 * 0b00010..Pulse width is three 1588-clock cycles.
16743 * 0b00011..Pulse width is four 1588-clock cycles.
16744 * 0b11111..Pulse width is 32 1588-clock cycles.
16745 */
16746#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
16747/* @} */
16748
16749/* The count of ENET_TCSR */
16750#define ENET_TCSR_COUNT (4U)
16751
16752/* @name TCCR - Timer Compare Capture Register */
16753/* @{ */
16754#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
16755#define ENET_TCCR_TCC_SHIFT (0U)
16756#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
16757/* @} */
16758
16759/* The count of ENET_TCCR */
16760#define ENET_TCCR_COUNT (4U)
16761
16762
16763/*
16764 * @}
16765 */ /* end of group ENET_Register_Masks */
16766
16767
16768/* ENET - Peripheral instance base addresses */
16769/* Peripheral ENET base address */
16770#define ENET_BASE (0x402D8000u)
16771/* Peripheral ENET base pointer */
16772#define ENET ((ENET_Type *)ENET_BASE)
16773/* Peripheral ENET2 base address */
16774#define ENET2_BASE (0x402D4000u)
16775/* Peripheral ENET2 base pointer */
16776#define ENET2 ((ENET_Type *)ENET2_BASE)
16777/* Array initializer of ENET peripheral base addresses */
16778#define ENET_BASE_ADDRS { ENET_BASE, 0u, ENET2_BASE }
16779/* Array initializer of ENET peripheral base pointers */
16780#define ENET_BASE_PTRS { ENET, (ENET_Type *)0u, ENET2 }
16781/* Interrupt vectors for the ENET peripheral type */
16782#define ENET_Transmit_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
16783#define ENET_Receive_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
16784#define ENET_Error_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn }
16785#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, NotAvail_IRQn, ENET2_1588_Timer_IRQn }
16786/* ENET Buffer Descriptor and Buffer Address Alignment. */
16787#define ENET_BUFF_ALIGNMENT (64U)
16788
16789
16790/*
16791 * @}
16792 */ /* end of group ENET_Peripheral_Access_Layer */
16793
16794
16795/* ----------------------------------------------------------------------------
16796 -- EWM Peripheral Access Layer
16797 ---------------------------------------------------------------------------- */
16798
16799/*
16800 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
16801 * @{
16802 */
16803
16804/* EWM - Register Layout Typedef */
16805typedef struct {
16806 __IO uint8_t CTRL;
16807 __O uint8_t SERV;
16808 __IO uint8_t CMPL;
16809 __IO uint8_t CMPH;
16810 __IO uint8_t CLKCTRL;
16811 __IO uint8_t CLKPRESCALER;
16812} EWM_Type;
16813
16814/* ----------------------------------------------------------------------------
16815 -- EWM Register Masks
16816 ---------------------------------------------------------------------------- */
16817
16818/*
16819 * @addtogroup EWM_Register_Masks EWM Register Masks
16820 * @{
16821 */
16822
16823/* @name CTRL - Control Register */
16824/* @{ */
16825#define EWM_CTRL_EWMEN_MASK (0x1U)
16826#define EWM_CTRL_EWMEN_SHIFT (0U)
16827#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
16828#define EWM_CTRL_ASSIN_MASK (0x2U)
16829#define EWM_CTRL_ASSIN_SHIFT (1U)
16830#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
16831#define EWM_CTRL_INEN_MASK (0x4U)
16832#define EWM_CTRL_INEN_SHIFT (2U)
16833#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
16834#define EWM_CTRL_INTEN_MASK (0x8U)
16835#define EWM_CTRL_INTEN_SHIFT (3U)
16836#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
16837/* @} */
16838
16839/* @name SERV - Service Register */
16840/* @{ */
16841#define EWM_SERV_SERVICE_MASK (0xFFU)
16842#define EWM_SERV_SERVICE_SHIFT (0U)
16843#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
16844/* @} */
16845
16846/* @name CMPL - Compare Low Register */
16847/* @{ */
16848#define EWM_CMPL_COMPAREL_MASK (0xFFU)
16849#define EWM_CMPL_COMPAREL_SHIFT (0U)
16850#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
16851/* @} */
16852
16853/* @name CMPH - Compare High Register */
16854/* @{ */
16855#define EWM_CMPH_COMPAREH_MASK (0xFFU)
16856#define EWM_CMPH_COMPAREH_SHIFT (0U)
16857#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
16858/* @} */
16859
16860/* @name CLKCTRL - Clock Control Register */
16861/* @{ */
16862#define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
16863#define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
16864#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
16865/* @} */
16866
16867/* @name CLKPRESCALER - Clock Prescaler Register */
16868/* @{ */
16869#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
16870#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
16871#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
16872/* @} */
16873
16874
16875/*
16876 * @}
16877 */ /* end of group EWM_Register_Masks */
16878
16879
16880/* EWM - Peripheral instance base addresses */
16881/* Peripheral EWM base address */
16882#define EWM_BASE (0x400B4000u)
16883/* Peripheral EWM base pointer */
16884#define EWM ((EWM_Type *)EWM_BASE)
16885/* Array initializer of EWM peripheral base addresses */
16886#define EWM_BASE_ADDRS { EWM_BASE }
16887/* Array initializer of EWM peripheral base pointers */
16888#define EWM_BASE_PTRS { EWM }
16889/* Interrupt vectors for the EWM peripheral type */
16890#define EWM_IRQS { EWM_IRQn }
16891
16892/*
16893 * @}
16894 */ /* end of group EWM_Peripheral_Access_Layer */
16895
16896
16897/* ----------------------------------------------------------------------------
16898 -- FLEXIO Peripheral Access Layer
16899 ---------------------------------------------------------------------------- */
16900
16901/*
16902 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
16903 * @{
16904 */
16905
16906/* FLEXIO - Register Layout Typedef */
16907typedef struct {
16908 __I uint32_t VERID;
16909 __I uint32_t PARAM;
16910 __IO uint32_t CTRL;
16911 __I uint32_t PIN;
16912 __IO uint32_t SHIFTSTAT;
16913 __IO uint32_t SHIFTERR;
16914 __IO uint32_t TIMSTAT;
16915 uint8_t RESERVED_0[4];
16916 __IO uint32_t SHIFTSIEN;
16917 __IO uint32_t SHIFTEIEN;
16918 __IO uint32_t TIMIEN;
16919 uint8_t RESERVED_1[4];
16920 __IO uint32_t SHIFTSDEN;
16921 uint8_t RESERVED_2[12];
16922 __IO uint32_t SHIFTSTATE;
16923 uint8_t RESERVED_3[60];
16924 __IO uint32_t SHIFTCTL[4];
16925 uint8_t RESERVED_4[112];
16926 __IO uint32_t SHIFTCFG[4];
16927 uint8_t RESERVED_5[240];
16928 __IO uint32_t SHIFTBUF[4];
16929 uint8_t RESERVED_6[112];
16930 __IO uint32_t SHIFTBUFBIS[4];
16931 uint8_t RESERVED_7[112];
16932 __IO uint32_t SHIFTBUFBYS[4];
16933 uint8_t RESERVED_8[112];
16934 __IO uint32_t SHIFTBUFBBS[4];
16935 uint8_t RESERVED_9[112];
16936 __IO uint32_t TIMCTL[4];
16937 uint8_t RESERVED_10[112];
16938 __IO uint32_t TIMCFG[4];
16939 uint8_t RESERVED_11[112];
16940 __IO uint32_t TIMCMP[4];
16941 uint8_t RESERVED_12[368];
16942 __IO uint32_t SHIFTBUFNBS[4];
16943 uint8_t RESERVED_13[112];
16944 __IO uint32_t SHIFTBUFHWS[4];
16945 uint8_t RESERVED_14[112];
16946 __IO uint32_t SHIFTBUFNIS[4];
16947} FLEXIO_Type;
16948
16949/* ----------------------------------------------------------------------------
16950 -- FLEXIO Register Masks
16951 ---------------------------------------------------------------------------- */
16952
16953/*
16954 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
16955 * @{
16956 */
16957
16958/* @name VERID - Version ID Register */
16959/* @{ */
16960#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
16961#define FLEXIO_VERID_FEATURE_SHIFT (0U)
16962/* FEATURE - Feature Specification Number
16963 * 0b0000000000000000..Standard features implemented.
16964 * 0b0000000000000001..Supports state, logic and parallel modes.
16965 */
16966#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
16967#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
16968#define FLEXIO_VERID_MINOR_SHIFT (16U)
16969#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
16970#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
16971#define FLEXIO_VERID_MAJOR_SHIFT (24U)
16972#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
16973/* @} */
16974
16975/* @name PARAM - Parameter Register */
16976/* @{ */
16977#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
16978#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
16979#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
16980#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
16981#define FLEXIO_PARAM_TIMER_SHIFT (8U)
16982#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
16983#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
16984#define FLEXIO_PARAM_PIN_SHIFT (16U)
16985#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
16986#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
16987#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
16988#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
16989/* @} */
16990
16991/* @name CTRL - FlexIO Control Register */
16992/* @{ */
16993#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
16994#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
16995/* FLEXEN - FlexIO Enable
16996 * 0b0..FlexIO module is disabled.
16997 * 0b1..FlexIO module is enabled.
16998 */
16999#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
17000#define FLEXIO_CTRL_SWRST_MASK (0x2U)
17001#define FLEXIO_CTRL_SWRST_SHIFT (1U)
17002/* SWRST - Software Reset
17003 * 0b0..Software reset is disabled
17004 * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
17005 */
17006#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
17007#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
17008#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
17009/* FASTACC - Fast Access
17010 * 0b0..Configures for normal register accesses to FlexIO
17011 * 0b1..Configures for fast register accesses to FlexIO
17012 */
17013#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
17014#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
17015#define FLEXIO_CTRL_DBGE_SHIFT (30U)
17016/* DBGE - Debug Enable
17017 * 0b0..FlexIO is disabled in debug modes.
17018 * 0b1..FlexIO is enabled in debug modes
17019 */
17020#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
17021#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
17022#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
17023/* DOZEN - Doze Enable
17024 * 0b0..FlexIO enabled in Doze modes.
17025 * 0b1..FlexIO disabled in Doze modes.
17026 */
17027#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
17028/* @} */
17029
17030/* @name PIN - Pin State Register */
17031/* @{ */
17032#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
17033#define FLEXIO_PIN_PDI_SHIFT (0U)
17034#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */
17035/* @} */
17036
17037/* @name SHIFTSTAT - Shifter Status Register */
17038/* @{ */
17039#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
17040#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
17041#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
17042/* @} */
17043
17044/* @name SHIFTERR - Shifter Error Register */
17045/* @{ */
17046#define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
17047#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
17048#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
17049/* @} */
17050
17051/* @name TIMSTAT - Timer Status Register */
17052/* @{ */
17053#define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
17054#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
17055#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
17056/* @} */
17057
17058/* @name SHIFTSIEN - Shifter Status Interrupt Enable */
17059/* @{ */
17060#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
17061#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
17062#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
17063/* @} */
17064
17065/* @name SHIFTEIEN - Shifter Error Interrupt Enable */
17066/* @{ */
17067#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
17068#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
17069#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
17070/* @} */
17071
17072/* @name TIMIEN - Timer Interrupt Enable Register */
17073/* @{ */
17074#define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
17075#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
17076#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
17077/* @} */
17078
17079/* @name SHIFTSDEN - Shifter Status DMA Enable */
17080/* @{ */
17081#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
17082#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
17083#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
17084/* @} */
17085
17086/* @name SHIFTSTATE - Shifter State Register */
17087/* @{ */
17088#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
17089#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
17090#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
17091/* @} */
17092
17093/* @name SHIFTCTL - Shifter Control N Register */
17094/* @{ */
17095#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
17096#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
17097/* SMOD - Shifter Mode
17098 * 0b000..Disabled.
17099 * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
17100 * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
17101 * 0b011..Reserved.
17102 * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
17103 * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
17104 * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
17105 * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
17106 */
17107#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
17108#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
17109#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
17110/* PINPOL - Shifter Pin Polarity
17111 * 0b0..Pin is active high
17112 * 0b1..Pin is active low
17113 */
17114#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
17115#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
17116#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
17117#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
17118#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
17119#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
17120/* PINCFG - Shifter Pin Configuration
17121 * 0b00..Shifter pin output disabled
17122 * 0b01..Shifter pin open drain or bidirectional output enable
17123 * 0b10..Shifter pin bidirectional output data
17124 * 0b11..Shifter pin output
17125 */
17126#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
17127#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
17128#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
17129/* TIMPOL - Timer Polarity
17130 * 0b0..Shift on posedge of Shift clock
17131 * 0b1..Shift on negedge of Shift clock
17132 */
17133#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
17134#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
17135#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
17136#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
17137/* @} */
17138
17139/* The count of FLEXIO_SHIFTCTL */
17140#define FLEXIO_SHIFTCTL_COUNT (4U)
17141
17142/* @name SHIFTCFG - Shifter Configuration N Register */
17143/* @{ */
17144#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
17145#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
17146/* SSTART - Shifter Start bit
17147 * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
17148 * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
17149 * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
17150 * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
17151 */
17152#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
17153#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
17154#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
17155/* SSTOP - Shifter Stop bit
17156 * 0b00..Stop bit disabled for transmitter/receiver/match store
17157 * 0b01..Reserved for transmitter/receiver/match store
17158 * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
17159 * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
17160 */
17161#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
17162#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
17163#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
17164/* INSRC - Input Source
17165 * 0b0..Pin
17166 * 0b1..Shifter N+1 Output
17167 */
17168#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
17169#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
17170#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
17171#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
17172/* @} */
17173
17174/* The count of FLEXIO_SHIFTCFG */
17175#define FLEXIO_SHIFTCFG_COUNT (4U)
17176
17177/* @name SHIFTBUF - Shifter Buffer N Register */
17178/* @{ */
17179#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
17180#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
17181#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
17182/* @} */
17183
17184/* The count of FLEXIO_SHIFTBUF */
17185#define FLEXIO_SHIFTBUF_COUNT (4U)
17186
17187/* @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
17188/* @{ */
17189#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
17190#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
17191#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
17192/* @} */
17193
17194/* The count of FLEXIO_SHIFTBUFBIS */
17195#define FLEXIO_SHIFTBUFBIS_COUNT (4U)
17196
17197/* @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
17198/* @{ */
17199#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
17200#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
17201#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
17202/* @} */
17203
17204/* The count of FLEXIO_SHIFTBUFBYS */
17205#define FLEXIO_SHIFTBUFBYS_COUNT (4U)
17206
17207/* @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
17208/* @{ */
17209#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
17210#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
17211#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
17212/* @} */
17213
17214/* The count of FLEXIO_SHIFTBUFBBS */
17215#define FLEXIO_SHIFTBUFBBS_COUNT (4U)
17216
17217/* @name TIMCTL - Timer Control N Register */
17218/* @{ */
17219#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
17220#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
17221/* TIMOD - Timer Mode
17222 * 0b00..Timer Disabled.
17223 * 0b01..Dual 8-bit counters baud mode.
17224 * 0b10..Dual 8-bit counters PWM high mode.
17225 * 0b11..Single 16-bit counter mode.
17226 */
17227#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
17228#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
17229#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
17230/* PINPOL - Timer Pin Polarity
17231 * 0b0..Pin is active high
17232 * 0b1..Pin is active low
17233 */
17234#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
17235#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
17236#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
17237#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */
17238#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
17239#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
17240/* PINCFG - Timer Pin Configuration
17241 * 0b00..Timer pin output disabled
17242 * 0b01..Timer pin open drain or bidirectional output enable
17243 * 0b10..Timer pin bidirectional output data
17244 * 0b11..Timer pin output
17245 */
17246#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
17247#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
17248#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
17249/* TRGSRC - Trigger Source
17250 * 0b0..External trigger selected
17251 * 0b1..Internal trigger selected
17252 */
17253#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
17254#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
17255#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
17256/* TRGPOL - Trigger Polarity
17257 * 0b0..Trigger active high
17258 * 0b1..Trigger active low
17259 */
17260#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
17261#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
17262#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
17263#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */
17264/* @} */
17265
17266/* The count of FLEXIO_TIMCTL */
17267#define FLEXIO_TIMCTL_COUNT (4U)
17268
17269/* @name TIMCFG - Timer Configuration N Register */
17270/* @{ */
17271#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
17272#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
17273/* TSTART - Timer Start Bit
17274 * 0b0..Start bit disabled
17275 * 0b1..Start bit enabled
17276 */
17277#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
17278#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
17279#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
17280/* TSTOP - Timer Stop Bit
17281 * 0b00..Stop bit disabled
17282 * 0b01..Stop bit is enabled on timer compare
17283 * 0b10..Stop bit is enabled on timer disable
17284 * 0b11..Stop bit is enabled on timer compare and timer disable
17285 */
17286#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
17287#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
17288#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
17289/* TIMENA - Timer Enable
17290 * 0b000..Timer always enabled
17291 * 0b001..Timer enabled on Timer N-1 enable
17292 * 0b010..Timer enabled on Trigger high
17293 * 0b011..Timer enabled on Trigger high and Pin high
17294 * 0b100..Timer enabled on Pin rising edge
17295 * 0b101..Timer enabled on Pin rising edge and Trigger high
17296 * 0b110..Timer enabled on Trigger rising edge
17297 * 0b111..Timer enabled on Trigger rising or falling edge
17298 */
17299#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
17300#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
17301#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
17302/* TIMDIS - Timer Disable
17303 * 0b000..Timer never disabled
17304 * 0b001..Timer disabled on Timer N-1 disable
17305 * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
17306 * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
17307 * 0b100..Timer disabled on Pin rising or falling edge
17308 * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
17309 * 0b110..Timer disabled on Trigger falling edge
17310 * 0b111..Reserved
17311 */
17312#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
17313#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
17314#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
17315/* TIMRST - Timer Reset
17316 * 0b000..Timer never reset
17317 * 0b001..Reserved
17318 * 0b010..Timer reset on Timer Pin equal to Timer Output
17319 * 0b011..Timer reset on Timer Trigger equal to Timer Output
17320 * 0b100..Timer reset on Timer Pin rising edge
17321 * 0b101..Reserved
17322 * 0b110..Timer reset on Trigger rising edge
17323 * 0b111..Timer reset on Trigger rising or falling edge
17324 */
17325#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
17326#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
17327#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
17328/* TIMDEC - Timer Decrement
17329 * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output.
17330 * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
17331 * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
17332 * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
17333 */
17334#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
17335#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
17336#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
17337/* TIMOUT - Timer Output
17338 * 0b00..Timer output is logic one when enabled and is not affected by timer reset
17339 * 0b01..Timer output is logic zero when enabled and is not affected by timer reset
17340 * 0b10..Timer output is logic one when enabled and on timer reset
17341 * 0b11..Timer output is logic zero when enabled and on timer reset
17342 */
17343#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
17344/* @} */
17345
17346/* The count of FLEXIO_TIMCFG */
17347#define FLEXIO_TIMCFG_COUNT (4U)
17348
17349/* @name TIMCMP - Timer Compare N Register */
17350/* @{ */
17351#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
17352#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
17353#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
17354/* @} */
17355
17356/* The count of FLEXIO_TIMCMP */
17357#define FLEXIO_TIMCMP_COUNT (4U)
17358
17359/* @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
17360/* @{ */
17361#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
17362#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
17363#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
17364/* @} */
17365
17366/* The count of FLEXIO_SHIFTBUFNBS */
17367#define FLEXIO_SHIFTBUFNBS_COUNT (4U)
17368
17369/* @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
17370/* @{ */
17371#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
17372#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
17373#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
17374/* @} */
17375
17376/* The count of FLEXIO_SHIFTBUFHWS */
17377#define FLEXIO_SHIFTBUFHWS_COUNT (4U)
17378
17379/* @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
17380/* @{ */
17381#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
17382#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
17383#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
17384/* @} */
17385
17386/* The count of FLEXIO_SHIFTBUFNIS */
17387#define FLEXIO_SHIFTBUFNIS_COUNT (4U)
17388
17389
17390/*
17391 * @}
17392 */ /* end of group FLEXIO_Register_Masks */
17393
17394
17395/* FLEXIO - Peripheral instance base addresses */
17396/* Peripheral FLEXIO1 base address */
17397#define FLEXIO1_BASE (0x401AC000u)
17398/* Peripheral FLEXIO1 base pointer */
17399#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
17400/* Peripheral FLEXIO2 base address */
17401#define FLEXIO2_BASE (0x401B0000u)
17402/* Peripheral FLEXIO2 base pointer */
17403#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
17404/* Peripheral FLEXIO3 base address */
17405#define FLEXIO3_BASE (0x42020000u)
17406/* Peripheral FLEXIO3 base pointer */
17407#define FLEXIO3 ((FLEXIO_Type *)FLEXIO3_BASE)
17408/* Array initializer of FLEXIO peripheral base addresses */
17409#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE, FLEXIO3_BASE }
17410/* Array initializer of FLEXIO peripheral base pointers */
17411#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2, FLEXIO3 }
17412/* Interrupt vectors for the FLEXIO peripheral type */
17413#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn, FLEXIO3_IRQn }
17414
17415/*
17416 * @}
17417 */ /* end of group FLEXIO_Peripheral_Access_Layer */
17418
17419
17420/* ----------------------------------------------------------------------------
17421 -- FLEXRAM Peripheral Access Layer
17422 ---------------------------------------------------------------------------- */
17423
17424/*
17425 * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer
17426 * @{
17427 */
17428
17429/* FLEXRAM - Register Layout Typedef */
17430typedef struct {
17431 __IO uint32_t TCM_CTRL;
17432 uint8_t RESERVED_0[12];
17433 __IO uint32_t INT_STATUS;
17434 __IO uint32_t INT_STAT_EN;
17435 __IO uint32_t INT_SIG_EN;
17436} FLEXRAM_Type;
17437
17438/* ----------------------------------------------------------------------------
17439 -- FLEXRAM Register Masks
17440 ---------------------------------------------------------------------------- */
17441
17442/*
17443 * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks
17444 * @{
17445 */
17446
17447/* @name TCM_CTRL - TCM CRTL Register */
17448/* @{ */
17449#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
17450#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
17451/* TCM_WWAIT_EN - TCM Write Wait Mode Enable
17452 * 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.
17453 * 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
17454 */
17455#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
17456#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
17457#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
17458/* TCM_RWAIT_EN - TCM Read Wait Mode Enable
17459 * 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.
17460 * 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
17461 */
17462#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
17463#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
17464#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
17465#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
17466/* @} */
17467
17468/* @name INT_STATUS - Interrupt Status Register */
17469/* @{ */
17470#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
17471#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
17472/* ITCM_ERR_STATUS - ITCM Access Error Status
17473 * 0b0..ITCM access error does not happen
17474 * 0b1..ITCM access error happens.
17475 */
17476#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
17477#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
17478#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
17479/* DTCM_ERR_STATUS - DTCM Access Error Status
17480 * 0b0..DTCM access error does not happen
17481 * 0b1..DTCM access error happens.
17482 */
17483#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
17484#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
17485#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
17486/* OCRAM_ERR_STATUS - OCRAM Access Error Status
17487 * 0b0..OCRAM access error does not happen
17488 * 0b1..OCRAM access error happens.
17489 */
17490#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
17491/* @} */
17492
17493/* @name INT_STAT_EN - Interrupt Status Enable Register */
17494/* @{ */
17495#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
17496#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
17497/* ITCM_ERR_STAT_EN - ITCM Access Error Status Enable
17498 * 0b0..Masked
17499 * 0b1..Enabled
17500 */
17501#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
17502#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
17503#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
17504/* DTCM_ERR_STAT_EN - DTCM Access Error Status Enable
17505 * 0b0..Masked
17506 * 0b1..Enabled
17507 */
17508#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
17509#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
17510#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
17511/* OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable
17512 * 0b0..Masked
17513 * 0b1..Enabled
17514 */
17515#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
17516/* @} */
17517
17518/* @name INT_SIG_EN - Interrupt Enable Register */
17519/* @{ */
17520#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
17521#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
17522/* ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable
17523 * 0b0..Masked
17524 * 0b1..Enabled
17525 */
17526#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
17527#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
17528#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
17529/* DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable
17530 * 0b0..Masked
17531 * 0b1..Enabled
17532 */
17533#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
17534#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
17535#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
17536/* OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable
17537 * 0b0..Masked
17538 * 0b1..Enabled
17539 */
17540#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
17541/* @} */
17542
17543
17544/*
17545 * @}
17546 */ /* end of group FLEXRAM_Register_Masks */
17547
17548
17549/* FLEXRAM - Peripheral instance base addresses */
17550/* Peripheral FLEXRAM base address */
17551#define FLEXRAM_BASE (0x400B0000u)
17552/* Peripheral FLEXRAM base pointer */
17553#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
17554/* Array initializer of FLEXRAM peripheral base addresses */
17555#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
17556/* Array initializer of FLEXRAM peripheral base pointers */
17557#define FLEXRAM_BASE_PTRS { FLEXRAM }
17558/* Interrupt vectors for the FLEXRAM peripheral type */
17559#define FLEXRAM_IRQS { FLEXRAM_IRQn }
17560
17561/*
17562 * @}
17563 */ /* end of group FLEXRAM_Peripheral_Access_Layer */
17564
17565
17566/* ----------------------------------------------------------------------------
17567 -- FLEXSPI Peripheral Access Layer
17568 ---------------------------------------------------------------------------- */
17569
17570/*
17571 * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
17572 * @{
17573 */
17574
17575/* FLEXSPI - Register Layout Typedef */
17576typedef struct {
17577 __IO uint32_t MCR0;
17578 __IO uint32_t MCR1;
17579 __IO uint32_t MCR2;
17580 __IO uint32_t AHBCR;
17581 __IO uint32_t INTEN;
17582 __IO uint32_t INTR;
17583 __IO uint32_t LUTKEY;
17584 __IO uint32_t LUTCR;
17585 __IO uint32_t AHBRXBUFCR[4];
17586 uint8_t RESERVED_0[48];
17587 __IO uint32_t FLSHCR0[4];
17588 __IO uint32_t FLSHCR1[4];
17589 __IO uint32_t FLSHCR2[4];
17590 uint8_t RESERVED_1[4];
17591 __IO uint32_t FLSHCR4;
17592 uint8_t RESERVED_2[8];
17593 __IO uint32_t IPCR0;
17594 __IO uint32_t IPCR1;
17595 uint8_t RESERVED_3[8];
17596 __IO uint32_t IPCMD;
17597 uint32_t DLPR;
17598 __IO uint32_t IPRXFCR;
17599 __IO uint32_t IPTXFCR;
17600 __IO uint32_t DLLCR[2];
17601 uint8_t RESERVED_5[24];
17602 __I uint32_t STS0;
17603 __I uint32_t STS1;
17604 __I uint32_t STS2;
17605 __I uint32_t AHBSPNDSTS;
17606 __I uint32_t IPRXFSTS;
17607 __I uint32_t IPTXFSTS;
17608 uint8_t RESERVED_6[8];
17609 __I uint32_t RFDR[32];
17610 __O uint32_t TFDR[32];
17611 __IO uint32_t LUT[64];
17612} FLEXSPI_Type;
17613
17614/* ----------------------------------------------------------------------------
17615 -- FLEXSPI Register Masks
17616 ---------------------------------------------------------------------------- */
17617
17618/*
17619 * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
17620 * @{
17621 */
17622
17623/* @name MCR0 - Module Control Register 0 */
17624/* @{ */
17625#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
17626#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
17627#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
17628#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
17629#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
17630#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
17631#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
17632#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
17633/* RXCLKSRC - Sample Clock source selection for Flash Reading
17634 * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
17635 * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
17636 * 0b10..Reserved
17637 * 0b11..Flash provided Read strobe and input from DQS pad
17638 */
17639#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
17640#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
17641#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
17642/* ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
17643 * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
17644 * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
17645 */
17646#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
17647#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
17648#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
17649/* ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
17650 * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
17651 * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
17652 */
17653#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
17654#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
17655#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
17656/* HSEN - Half Speed Serial Flash access Enable.
17657 * 0b0..Disable divide by 2 of serial flash clock for half speed commands.
17658 * 0b1..Enable divide by 2 of serial flash clock for half speed commands.
17659 */
17660#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
17661#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
17662#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
17663/* DOZEEN - Doze mode enable bit
17664 * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
17665 * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
17666 */
17667#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
17668#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
17669#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
17670/* COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]).
17671 * 0b0..Disable.
17672 * 0b1..Enable.
17673 */
17674#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
17675#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
17676#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
17677/* SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications,
17678 * external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is
17679 * enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2).
17680 * 0b0..Disable.
17681 * 0b1..Enable.
17682 */
17683#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
17684#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
17685#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
17686#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
17687#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
17688#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
17689#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
17690/* @} */
17691
17692/* @name MCR1 - Module Control Register 1 */
17693/* @{ */
17694#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
17695#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
17696#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
17697#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
17698#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
17699#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
17700/* @} */
17701
17702/* @name MCR2 - Module Control Register 2 */
17703/* @{ */
17704#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
17705#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
17706/* CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
17707 * automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
17708 * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
17709 * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
17710 * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
17711 * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
17712 */
17713#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
17714#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
17715#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
17716#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
17717#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
17718#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
17719/* SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
17720 * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
17721 * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
17722 * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
17723 * ignored.
17724 * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
17725 */
17726#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
17727#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
17728#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
17729/* SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA).
17730 * In this case, port B flash access is not available. After change the value of this feild,
17731 * MCR0[SWRESET] should be set.
17732 * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available.
17733 * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available.
17734 */
17735#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
17736#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
17737#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
17738#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
17739/* @} */
17740
17741/* @name AHBCR - AHB Bus Control Register */
17742/* @{ */
17743#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
17744#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
17745/* APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
17746 * 0b0..Flash will be accessed in Individual mode.
17747 * 0b1..Flash will be accessed in Parallel mode.
17748 */
17749#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
17750#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
17751#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
17752/* CACHABLEEN - Enable AHB bus cachable read access support.
17753 * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
17754 * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
17755 */
17756#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
17757#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
17758#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
17759/* BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
17760 * of AHB write access, refer for more details about AHB bufferable write.
17761 * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
17762 * ready after all data is transmitted to External device and AHB command finished.
17763 * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
17764 * granted by arbitrator and will not wait for AHB command finished.
17765 */
17766#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
17767#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
17768#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
17769#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
17770#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
17771#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
17772/* READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
17773 * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
17774 * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB
17775 * burst required to meet the alignment requirement.
17776 */
17777#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
17778/* @} */
17779
17780/* @name INTEN - Interrupt Enable Register */
17781/* @{ */
17782#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
17783#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
17784#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
17785#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
17786#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
17787#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
17788#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
17789#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
17790#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
17791#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
17792#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
17793#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
17794#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
17795#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
17796#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
17797#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
17798#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
17799#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
17800#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
17801#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
17802#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
17803#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
17804#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
17805#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
17806#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
17807#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
17808#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
17809#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
17810#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
17811#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
17812#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
17813#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
17814#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
17815/* @} */
17816
17817/* @name INTR - Interrupt Register */
17818/* @{ */
17819#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
17820#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
17821#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
17822#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
17823#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
17824#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
17825#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
17826#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
17827#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
17828#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
17829#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
17830#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
17831#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
17832#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
17833#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
17834#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
17835#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
17836#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
17837#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
17838#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
17839#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
17840#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
17841#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
17842#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
17843#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
17844#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
17845#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
17846#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
17847#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
17848#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
17849#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
17850#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
17851#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
17852/* @} */
17853
17854/* @name LUTKEY - LUT Key Register */
17855/* @{ */
17856#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
17857#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
17858#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
17859/* @} */
17860
17861/* @name LUTCR - LUT Control Register */
17862/* @{ */
17863#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
17864#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
17865#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
17866#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
17867#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
17868#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
17869/* @} */
17870
17871/* @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */
17872/* @{ */
17873#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU)
17874#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
17875#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
17876#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
17877#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
17878#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
17879#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U)
17880#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
17881#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
17882#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
17883#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
17884#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
17885/* @} */
17886
17887/* The count of FLEXSPI_AHBRXBUFCR0 */
17888#define FLEXSPI_AHBRXBUFCR0_COUNT (4U)
17889
17890/* @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */
17891/* @{ */
17892#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
17893#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
17894#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
17895/* @} */
17896
17897/* The count of FLEXSPI_FLSHCR0 */
17898#define FLEXSPI_FLSHCR0_COUNT (4U)
17899
17900/* @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */
17901/* @{ */
17902#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
17903#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
17904#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
17905#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
17906#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
17907#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
17908#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
17909#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
17910#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
17911#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
17912#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
17913#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
17914#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
17915#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
17916/* CSINTERVALUNIT - CS interval unit
17917 * 0b0..The CS interval unit is 1 serial clock cycle
17918 * 0b1..The CS interval unit is 256 serial clock cycle
17919 */
17920#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
17921#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
17922#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
17923#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
17924/* @} */
17925
17926/* The count of FLEXSPI_FLSHCR1 */
17927#define FLEXSPI_FLSHCR1_COUNT (4U)
17928
17929/* @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */
17930/* @{ */
17931#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
17932#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
17933#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
17934#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
17935#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
17936#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
17937#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
17938#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
17939#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
17940#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
17941#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
17942#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
17943#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
17944#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
17945#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
17946#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
17947#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
17948/* AWRWAITUNIT - AWRWAIT unit
17949 * 0b000..The AWRWAIT unit is 2 ahb clock cycle
17950 * 0b001..The AWRWAIT unit is 8 ahb clock cycle
17951 * 0b010..The AWRWAIT unit is 32 ahb clock cycle
17952 * 0b011..The AWRWAIT unit is 128 ahb clock cycle
17953 * 0b100..The AWRWAIT unit is 512 ahb clock cycle
17954 * 0b101..The AWRWAIT unit is 2048 ahb clock cycle
17955 * 0b110..The AWRWAIT unit is 8192 ahb clock cycle
17956 * 0b111..The AWRWAIT unit is 32768 ahb clock cycle
17957 */
17958#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
17959#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
17960#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
17961#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
17962/* @} */
17963
17964/* The count of FLEXSPI_FLSHCR2 */
17965#define FLEXSPI_FLSHCR2_COUNT (4U)
17966
17967/* @name FLSHCR4 - Flash Control Register 4 */
17968/* @{ */
17969#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
17970#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
17971/* WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
17972 * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
17973 * burst start address alignment when flash is accessed in individual mode.
17974 * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
17975 * burst start address alignment when flash is accessed in individual mode.
17976 */
17977#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
17978#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
17979#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
17980/* WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
17981 * memory device on port A, this bit must be set.
17982 * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
17983 * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
17984 */
17985#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
17986#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
17987#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
17988/* WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
17989 * memory device on port B, this bit must be set.
17990 * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
17991 * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
17992 */
17993#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
17994/* @} */
17995
17996/* @name IPCR0 - IP Control Register 0 */
17997/* @{ */
17998#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
17999#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
18000#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
18001/* @} */
18002
18003/* @name IPCR1 - IP Control Register 1 */
18004/* @{ */
18005#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
18006#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
18007#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
18008#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
18009#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
18010#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
18011#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
18012#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
18013#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
18014#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
18015#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
18016/* IPAREN - Parallel mode Enabled for IP command.
18017 * 0b0..Flash will be accessed in Individual mode.
18018 * 0b1..Flash will be accessed in Parallel mode.
18019 */
18020#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
18021/* @} */
18022
18023/* @name IPCMD - IP Command Register */
18024/* @{ */
18025#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
18026#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
18027#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
18028/* @} */
18029
18030/* @name IPRXFCR - IP RX FIFO Control Register */
18031/* @{ */
18032#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
18033#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
18034#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
18035#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
18036#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
18037/* RXDMAEN - IP RX FIFO reading by DMA enabled.
18038 * 0b0..IP RX FIFO would be read by processor.
18039 * 0b1..IP RX FIFO would be read by DMA.
18040 */
18041#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
18042#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU)
18043#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
18044#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
18045/* @} */
18046
18047/* @name IPTXFCR - IP TX FIFO Control Register */
18048/* @{ */
18049#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
18050#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
18051#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
18052#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
18053#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
18054/* TXDMAEN - IP TX FIFO filling by DMA enabled.
18055 * 0b0..IP TX FIFO would be filled by processor.
18056 * 0b1..IP TX FIFO would be filled by DMA.
18057 */
18058#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
18059#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU)
18060#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
18061#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
18062/* @} */
18063
18064/* @name DLLCR - DLL Control Register 0 */
18065/* @{ */
18066#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
18067#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
18068#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
18069#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
18070#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
18071#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
18072#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
18073#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
18074#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
18075#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
18076#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
18077#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
18078#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
18079#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
18080#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
18081/* @} */
18082
18083/* The count of FLEXSPI_DLLCR */
18084#define FLEXSPI_DLLCR_COUNT (2U)
18085
18086/* @name STS0 - Status Register 0 */
18087/* @{ */
18088#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
18089#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
18090#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
18091#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
18092#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
18093#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
18094#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
18095#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
18096/* ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
18097 * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
18098 * 0b00..Triggered by AHB read command (triggered by AHB read).
18099 * 0b01..Triggered by AHB write command (triggered by AHB Write).
18100 * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
18101 * 0b11..Triggered by suspended command (resumed).
18102 */
18103#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
18104/* @} */
18105
18106/* @name STS1 - Status Register 1 */
18107/* @{ */
18108#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
18109#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
18110#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
18111#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
18112#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
18113/* AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
18114 * cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
18115 * 0b0000..No error.
18116 * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
18117 * 0b0011..There is unknown instruction opcode in the sequence.
18118 * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
18119 * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
18120 * 0b1110..Sequence execution timeout.
18121 */
18122#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
18123#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
18124#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
18125#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
18126#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
18127#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
18128/* IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
18129 * cleared when INTR[IPCMDERR] is write-1-clear(w1c).
18130 * 0b0000..No error.
18131 * 0b0010..IP command with JMP_ON_CS instruction used in the sequence.
18132 * 0b0011..There is unknown instruction opcode in the sequence.
18133 * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
18134 * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
18135 * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
18136 * 0b1110..Sequence execution timeout.
18137 * 0b1111..Flash boundary crossed.
18138 */
18139#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
18140/* @} */
18141
18142/* @name STS2 - Status Register 2 */
18143/* @{ */
18144#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
18145#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
18146#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
18147#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
18148#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
18149#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
18150#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
18151#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
18152#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
18153#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
18154#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
18155#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
18156#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
18157#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
18158#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
18159#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
18160#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
18161#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
18162#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
18163#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
18164#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
18165#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
18166#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
18167#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
18168/* @} */
18169
18170/* @name AHBSPNDSTS - AHB Suspend Status Register */
18171/* @{ */
18172#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
18173#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
18174#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
18175#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
18176#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
18177#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
18178#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
18179#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
18180#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
18181/* @} */
18182
18183/* @name IPRXFSTS - IP RX FIFO Status Register */
18184/* @{ */
18185#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
18186#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
18187#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
18188#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
18189#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
18190#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
18191/* @} */
18192
18193/* @name IPTXFSTS - IP TX FIFO Status Register */
18194/* @{ */
18195#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
18196#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
18197#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
18198#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
18199#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
18200#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
18201/* @} */
18202
18203/* @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
18204/* @{ */
18205#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
18206#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
18207#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
18208/* @} */
18209
18210/* The count of FLEXSPI_RFDR */
18211#define FLEXSPI_RFDR_COUNT (32U)
18212
18213/* @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
18214/* @{ */
18215#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
18216#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
18217#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
18218/* @} */
18219
18220/* The count of FLEXSPI_TFDR */
18221#define FLEXSPI_TFDR_COUNT (32U)
18222
18223/* @name LUT - LUT 0..LUT 63 */
18224/* @{ */
18225#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
18226#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
18227#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
18228#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
18229#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
18230#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
18231#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
18232#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
18233#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
18234#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
18235#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
18236#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
18237#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
18238#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
18239#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
18240#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
18241#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
18242#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
18243/* @} */
18244
18245/* The count of FLEXSPI_LUT */
18246#define FLEXSPI_LUT_COUNT (64U)
18247
18248
18249/*
18250 * @}
18251 */ /* end of group FLEXSPI_Register_Masks */
18252
18253
18254/* FLEXSPI - Peripheral instance base addresses */
18255/* Peripheral FLEXSPI base address */
18256#define FLEXSPI_BASE (0x402A8000u)
18257/* Peripheral FLEXSPI base pointer */
18258#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE)
18259/* Peripheral FLEXSPI2 base address */
18260#define FLEXSPI2_BASE (0x402A4000u)
18261/* Peripheral FLEXSPI2 base pointer */
18262#define FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE)
18263/* Array initializer of FLEXSPI peripheral base addresses */
18264#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE, 0u, FLEXSPI2_BASE }
18265/* Array initializer of FLEXSPI peripheral base pointers */
18266#define FLEXSPI_BASE_PTRS { FLEXSPI, (FLEXSPI_Type *)0u, FLEXSPI2 }
18267/* Interrupt vectors for the FLEXSPI peripheral type */
18268#define FLEXSPI_IRQS { FLEXSPI_IRQn, NotAvail_IRQn, FLEXSPI2_IRQn }
18269/* FlexSPI AMBA address. */
18270#define FlexSPI_AMBA_BASE (0x60000000U)
18271/* FlexSPI ASFM address. */
18272#define FlexSPI_ASFM_BASE (0x60000000U)
18273/* Base Address of AHB address space mapped to IP RX FIFO. */
18274#define FlexSPI_ARDF_BASE (0x7FC00000U)
18275/* Base Address of AHB address space mapped to IP TX FIFO. */
18276#define FlexSPI_ATDF_BASE (0x7F800000U)
18277/* FlexSPI2 AMBA address. */
18278#define FlexSPI2_AMBA_BASE (0x70000000U)
18279/* FlexSPI ASFM address. */
18280#define FlexSPI2_ASFM_BASE (0x70000000U)
18281/* Base Address of AHB address space mapped to IP RX FIFO. */
18282#define FlexSPI2_ARDF_BASE (0x7F400000U)
18283/* Base Address of AHB address space mapped to IP TX FIFO. */
18284#define FlexSPI2_ATDF_BASE (0x7F000000U)
18285
18286
18287/*
18288 * @}
18289 */ /* end of group FLEXSPI_Peripheral_Access_Layer */
18290
18291
18292/* ----------------------------------------------------------------------------
18293 -- GPC Peripheral Access Layer
18294 ---------------------------------------------------------------------------- */
18295
18296/*
18297 * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
18298 * @{
18299 */
18300
18301/* GPC - Register Layout Typedef */
18302typedef struct {
18303 __IO uint32_t CNTR;
18304 uint8_t RESERVED_0[4];
18305 __IO uint32_t IMR[4];
18306 __I uint32_t ISR[4];
18307 uint8_t RESERVED_1[12];
18308 __IO uint32_t IMR5;
18309 __I uint32_t ISR5;
18310} GPC_Type;
18311
18312/* ----------------------------------------------------------------------------
18313 -- GPC Register Masks
18314 ---------------------------------------------------------------------------- */
18315
18316/*
18317 * @addtogroup GPC_Register_Masks GPC Register Masks
18318 * @{
18319 */
18320
18321/* @name CNTR - GPC Interface control register */
18322/* @{ */
18323#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U)
18324#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U)
18325/* MEGA_PDN_REQ
18326 * 0b0..No Request
18327 * 0b1..Request power down sequence
18328 */
18329#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
18330#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U)
18331#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U)
18332/* MEGA_PUP_REQ
18333 * 0b0..No Request
18334 * 0b1..Request power up sequence
18335 */
18336#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
18337#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U)
18338#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U)
18339/* PDRAM0_PGE
18340 * 0b1..FlexRAM PDRAM0 domain will be power down once when CPU core is power down.
18341 * 0b0..FlexRAM PDRAM0 domain will keep power on even if CPU core is power down.
18342 */
18343#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
18344/* @} */
18345
18346/* @name IMR - IRQ masking register 1..IRQ masking register 4 */
18347/* @{ */
18348#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU)
18349#define GPC_IMR_IMR1_SHIFT (0U)
18350#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
18351#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU)
18352#define GPC_IMR_IMR2_SHIFT (0U)
18353#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
18354#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU)
18355#define GPC_IMR_IMR3_SHIFT (0U)
18356#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
18357#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU)
18358#define GPC_IMR_IMR4_SHIFT (0U)
18359#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
18360/* @} */
18361
18362/* The count of GPC_IMR */
18363#define GPC_IMR_COUNT (4U)
18364
18365/* @name ISR - IRQ status resister 1..IRQ status resister 4 */
18366/* @{ */
18367#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU)
18368#define GPC_ISR_ISR1_SHIFT (0U)
18369#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
18370#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU)
18371#define GPC_ISR_ISR2_SHIFT (0U)
18372#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
18373#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU)
18374#define GPC_ISR_ISR3_SHIFT (0U)
18375#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
18376#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU)
18377#define GPC_ISR_ISR4_SHIFT (0U)
18378#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
18379/* @} */
18380
18381/* The count of GPC_ISR */
18382#define GPC_ISR_COUNT (4U)
18383
18384/* @name IMR5 - IRQ masking register 5 */
18385/* @{ */
18386#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU)
18387#define GPC_IMR5_IMR5_SHIFT (0U)
18388#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
18389/* @} */
18390
18391/* @name ISR5 - IRQ status resister 5 */
18392/* @{ */
18393#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU)
18394#define GPC_ISR5_ISR4_SHIFT (0U)
18395#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK)
18396/* @} */
18397
18398
18399/*
18400 * @}
18401 */ /* end of group GPC_Register_Masks */
18402
18403
18404/* GPC - Peripheral instance base addresses */
18405/* Peripheral GPC base address */
18406#define GPC_BASE (0x400F4000u)
18407/* Peripheral GPC base pointer */
18408#define GPC ((GPC_Type *)GPC_BASE)
18409/* Array initializer of GPC peripheral base addresses */
18410#define GPC_BASE_ADDRS { GPC_BASE }
18411/* Array initializer of GPC peripheral base pointers */
18412#define GPC_BASE_PTRS { GPC }
18413/* Interrupt vectors for the GPC peripheral type */
18414#define GPC_IRQS { GPC_IRQn }
18415
18416/*
18417 * @}
18418 */ /* end of group GPC_Peripheral_Access_Layer */
18419
18420
18421/* ----------------------------------------------------------------------------
18422 -- GPIO Peripheral Access Layer
18423 ---------------------------------------------------------------------------- */
18424
18425/*
18426 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
18427 * @{
18428 */
18429
18430/* GPIO - Register Layout Typedef */
18431typedef struct {
18432 __IO uint32_t DR;
18433 __IO uint32_t GDIR;
18434 __I uint32_t PSR;
18435 __IO uint32_t ICR1;
18436 __IO uint32_t ICR2;
18437 __IO uint32_t IMR;
18438 __IO uint32_t ISR;
18439 __IO uint32_t EDGE_SEL;
18440 uint8_t RESERVED_0[100];
18441 __O uint32_t DR_SET;
18442 __O uint32_t DR_CLEAR;
18443 __O uint32_t DR_TOGGLE;
18444} GPIO_Type;
18445
18446/* ----------------------------------------------------------------------------
18447 -- GPIO Register Masks
18448 ---------------------------------------------------------------------------- */
18449
18450/*
18451 * @addtogroup GPIO_Register_Masks GPIO Register Masks
18452 * @{
18453 */
18454
18455/* @name DR - GPIO data register */
18456/* @{ */
18457#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
18458#define GPIO_DR_DR_SHIFT (0U)
18459#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
18460/* @} */
18461
18462/* @name GDIR - GPIO direction register */
18463/* @{ */
18464#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
18465#define GPIO_GDIR_GDIR_SHIFT (0U)
18466#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
18467/* @} */
18468
18469/* @name PSR - GPIO pad status register */
18470/* @{ */
18471#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
18472#define GPIO_PSR_PSR_SHIFT (0U)
18473#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
18474/* @} */
18475
18476/* @name ICR1 - GPIO interrupt configuration register1 */
18477/* @{ */
18478#define GPIO_ICR1_ICR0_MASK (0x3U)
18479#define GPIO_ICR1_ICR0_SHIFT (0U)
18480/* ICR0 - ICR0
18481 * 0b00..Interrupt n is low-level sensitive.
18482 * 0b01..Interrupt n is high-level sensitive.
18483 * 0b10..Interrupt n is rising-edge sensitive.
18484 * 0b11..Interrupt n is falling-edge sensitive.
18485 */
18486#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
18487#define GPIO_ICR1_ICR1_MASK (0xCU)
18488#define GPIO_ICR1_ICR1_SHIFT (2U)
18489/* ICR1 - ICR1
18490 * 0b00..Interrupt n is low-level sensitive.
18491 * 0b01..Interrupt n is high-level sensitive.
18492 * 0b10..Interrupt n is rising-edge sensitive.
18493 * 0b11..Interrupt n is falling-edge sensitive.
18494 */
18495#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
18496#define GPIO_ICR1_ICR2_MASK (0x30U)
18497#define GPIO_ICR1_ICR2_SHIFT (4U)
18498/* ICR2 - ICR2
18499 * 0b00..Interrupt n is low-level sensitive.
18500 * 0b01..Interrupt n is high-level sensitive.
18501 * 0b10..Interrupt n is rising-edge sensitive.
18502 * 0b11..Interrupt n is falling-edge sensitive.
18503 */
18504#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
18505#define GPIO_ICR1_ICR3_MASK (0xC0U)
18506#define GPIO_ICR1_ICR3_SHIFT (6U)
18507/* ICR3 - ICR3
18508 * 0b00..Interrupt n is low-level sensitive.
18509 * 0b01..Interrupt n is high-level sensitive.
18510 * 0b10..Interrupt n is rising-edge sensitive.
18511 * 0b11..Interrupt n is falling-edge sensitive.
18512 */
18513#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
18514#define GPIO_ICR1_ICR4_MASK (0x300U)
18515#define GPIO_ICR1_ICR4_SHIFT (8U)
18516/* ICR4 - ICR4
18517 * 0b00..Interrupt n is low-level sensitive.
18518 * 0b01..Interrupt n is high-level sensitive.
18519 * 0b10..Interrupt n is rising-edge sensitive.
18520 * 0b11..Interrupt n is falling-edge sensitive.
18521 */
18522#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
18523#define GPIO_ICR1_ICR5_MASK (0xC00U)
18524#define GPIO_ICR1_ICR5_SHIFT (10U)
18525/* ICR5 - ICR5
18526 * 0b00..Interrupt n is low-level sensitive.
18527 * 0b01..Interrupt n is high-level sensitive.
18528 * 0b10..Interrupt n is rising-edge sensitive.
18529 * 0b11..Interrupt n is falling-edge sensitive.
18530 */
18531#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
18532#define GPIO_ICR1_ICR6_MASK (0x3000U)
18533#define GPIO_ICR1_ICR6_SHIFT (12U)
18534/* ICR6 - ICR6
18535 * 0b00..Interrupt n is low-level sensitive.
18536 * 0b01..Interrupt n is high-level sensitive.
18537 * 0b10..Interrupt n is rising-edge sensitive.
18538 * 0b11..Interrupt n is falling-edge sensitive.
18539 */
18540#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
18541#define GPIO_ICR1_ICR7_MASK (0xC000U)
18542#define GPIO_ICR1_ICR7_SHIFT (14U)
18543/* ICR7 - ICR7
18544 * 0b00..Interrupt n is low-level sensitive.
18545 * 0b01..Interrupt n is high-level sensitive.
18546 * 0b10..Interrupt n is rising-edge sensitive.
18547 * 0b11..Interrupt n is falling-edge sensitive.
18548 */
18549#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
18550#define GPIO_ICR1_ICR8_MASK (0x30000U)
18551#define GPIO_ICR1_ICR8_SHIFT (16U)
18552/* ICR8 - ICR8
18553 * 0b00..Interrupt n is low-level sensitive.
18554 * 0b01..Interrupt n is high-level sensitive.
18555 * 0b10..Interrupt n is rising-edge sensitive.
18556 * 0b11..Interrupt n is falling-edge sensitive.
18557 */
18558#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
18559#define GPIO_ICR1_ICR9_MASK (0xC0000U)
18560#define GPIO_ICR1_ICR9_SHIFT (18U)
18561/* ICR9 - ICR9
18562 * 0b00..Interrupt n is low-level sensitive.
18563 * 0b01..Interrupt n is high-level sensitive.
18564 * 0b10..Interrupt n is rising-edge sensitive.
18565 * 0b11..Interrupt n is falling-edge sensitive.
18566 */
18567#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
18568#define GPIO_ICR1_ICR10_MASK (0x300000U)
18569#define GPIO_ICR1_ICR10_SHIFT (20U)
18570/* ICR10 - ICR10
18571 * 0b00..Interrupt n is low-level sensitive.
18572 * 0b01..Interrupt n is high-level sensitive.
18573 * 0b10..Interrupt n is rising-edge sensitive.
18574 * 0b11..Interrupt n is falling-edge sensitive.
18575 */
18576#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
18577#define GPIO_ICR1_ICR11_MASK (0xC00000U)
18578#define GPIO_ICR1_ICR11_SHIFT (22U)
18579/* ICR11 - ICR11
18580 * 0b00..Interrupt n is low-level sensitive.
18581 * 0b01..Interrupt n is high-level sensitive.
18582 * 0b10..Interrupt n is rising-edge sensitive.
18583 * 0b11..Interrupt n is falling-edge sensitive.
18584 */
18585#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
18586#define GPIO_ICR1_ICR12_MASK (0x3000000U)
18587#define GPIO_ICR1_ICR12_SHIFT (24U)
18588/* ICR12 - ICR12
18589 * 0b00..Interrupt n is low-level sensitive.
18590 * 0b01..Interrupt n is high-level sensitive.
18591 * 0b10..Interrupt n is rising-edge sensitive.
18592 * 0b11..Interrupt n is falling-edge sensitive.
18593 */
18594#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
18595#define GPIO_ICR1_ICR13_MASK (0xC000000U)
18596#define GPIO_ICR1_ICR13_SHIFT (26U)
18597/* ICR13 - ICR13
18598 * 0b00..Interrupt n is low-level sensitive.
18599 * 0b01..Interrupt n is high-level sensitive.
18600 * 0b10..Interrupt n is rising-edge sensitive.
18601 * 0b11..Interrupt n is falling-edge sensitive.
18602 */
18603#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
18604#define GPIO_ICR1_ICR14_MASK (0x30000000U)
18605#define GPIO_ICR1_ICR14_SHIFT (28U)
18606/* ICR14 - ICR14
18607 * 0b00..Interrupt n is low-level sensitive.
18608 * 0b01..Interrupt n is high-level sensitive.
18609 * 0b10..Interrupt n is rising-edge sensitive.
18610 * 0b11..Interrupt n is falling-edge sensitive.
18611 */
18612#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
18613#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
18614#define GPIO_ICR1_ICR15_SHIFT (30U)
18615/* ICR15 - ICR15
18616 * 0b00..Interrupt n is low-level sensitive.
18617 * 0b01..Interrupt n is high-level sensitive.
18618 * 0b10..Interrupt n is rising-edge sensitive.
18619 * 0b11..Interrupt n is falling-edge sensitive.
18620 */
18621#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
18622/* @} */
18623
18624/* @name ICR2 - GPIO interrupt configuration register2 */
18625/* @{ */
18626#define GPIO_ICR2_ICR16_MASK (0x3U)
18627#define GPIO_ICR2_ICR16_SHIFT (0U)
18628/* ICR16 - ICR16
18629 * 0b00..Interrupt n is low-level sensitive.
18630 * 0b01..Interrupt n is high-level sensitive.
18631 * 0b10..Interrupt n is rising-edge sensitive.
18632 * 0b11..Interrupt n is falling-edge sensitive.
18633 */
18634#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
18635#define GPIO_ICR2_ICR17_MASK (0xCU)
18636#define GPIO_ICR2_ICR17_SHIFT (2U)
18637/* ICR17 - ICR17
18638 * 0b00..Interrupt n is low-level sensitive.
18639 * 0b01..Interrupt n is high-level sensitive.
18640 * 0b10..Interrupt n is rising-edge sensitive.
18641 * 0b11..Interrupt n is falling-edge sensitive.
18642 */
18643#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
18644#define GPIO_ICR2_ICR18_MASK (0x30U)
18645#define GPIO_ICR2_ICR18_SHIFT (4U)
18646/* ICR18 - ICR18
18647 * 0b00..Interrupt n is low-level sensitive.
18648 * 0b01..Interrupt n is high-level sensitive.
18649 * 0b10..Interrupt n is rising-edge sensitive.
18650 * 0b11..Interrupt n is falling-edge sensitive.
18651 */
18652#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
18653#define GPIO_ICR2_ICR19_MASK (0xC0U)
18654#define GPIO_ICR2_ICR19_SHIFT (6U)
18655/* ICR19 - ICR19
18656 * 0b00..Interrupt n is low-level sensitive.
18657 * 0b01..Interrupt n is high-level sensitive.
18658 * 0b10..Interrupt n is rising-edge sensitive.
18659 * 0b11..Interrupt n is falling-edge sensitive.
18660 */
18661#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
18662#define GPIO_ICR2_ICR20_MASK (0x300U)
18663#define GPIO_ICR2_ICR20_SHIFT (8U)
18664/* ICR20 - ICR20
18665 * 0b00..Interrupt n is low-level sensitive.
18666 * 0b01..Interrupt n is high-level sensitive.
18667 * 0b10..Interrupt n is rising-edge sensitive.
18668 * 0b11..Interrupt n is falling-edge sensitive.
18669 */
18670#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
18671#define GPIO_ICR2_ICR21_MASK (0xC00U)
18672#define GPIO_ICR2_ICR21_SHIFT (10U)
18673/* ICR21 - ICR21
18674 * 0b00..Interrupt n is low-level sensitive.
18675 * 0b01..Interrupt n is high-level sensitive.
18676 * 0b10..Interrupt n is rising-edge sensitive.
18677 * 0b11..Interrupt n is falling-edge sensitive.
18678 */
18679#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
18680#define GPIO_ICR2_ICR22_MASK (0x3000U)
18681#define GPIO_ICR2_ICR22_SHIFT (12U)
18682/* ICR22 - ICR22
18683 * 0b00..Interrupt n is low-level sensitive.
18684 * 0b01..Interrupt n is high-level sensitive.
18685 * 0b10..Interrupt n is rising-edge sensitive.
18686 * 0b11..Interrupt n is falling-edge sensitive.
18687 */
18688#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
18689#define GPIO_ICR2_ICR23_MASK (0xC000U)
18690#define GPIO_ICR2_ICR23_SHIFT (14U)
18691/* ICR23 - ICR23
18692 * 0b00..Interrupt n is low-level sensitive.
18693 * 0b01..Interrupt n is high-level sensitive.
18694 * 0b10..Interrupt n is rising-edge sensitive.
18695 * 0b11..Interrupt n is falling-edge sensitive.
18696 */
18697#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
18698#define GPIO_ICR2_ICR24_MASK (0x30000U)
18699#define GPIO_ICR2_ICR24_SHIFT (16U)
18700/* ICR24 - ICR24
18701 * 0b00..Interrupt n is low-level sensitive.
18702 * 0b01..Interrupt n is high-level sensitive.
18703 * 0b10..Interrupt n is rising-edge sensitive.
18704 * 0b11..Interrupt n is falling-edge sensitive.
18705 */
18706#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
18707#define GPIO_ICR2_ICR25_MASK (0xC0000U)
18708#define GPIO_ICR2_ICR25_SHIFT (18U)
18709/* ICR25 - ICR25
18710 * 0b00..Interrupt n is low-level sensitive.
18711 * 0b01..Interrupt n is high-level sensitive.
18712 * 0b10..Interrupt n is rising-edge sensitive.
18713 * 0b11..Interrupt n is falling-edge sensitive.
18714 */
18715#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
18716#define GPIO_ICR2_ICR26_MASK (0x300000U)
18717#define GPIO_ICR2_ICR26_SHIFT (20U)
18718/* ICR26 - ICR26
18719 * 0b00..Interrupt n is low-level sensitive.
18720 * 0b01..Interrupt n is high-level sensitive.
18721 * 0b10..Interrupt n is rising-edge sensitive.
18722 * 0b11..Interrupt n is falling-edge sensitive.
18723 */
18724#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
18725#define GPIO_ICR2_ICR27_MASK (0xC00000U)
18726#define GPIO_ICR2_ICR27_SHIFT (22U)
18727/* ICR27 - ICR27
18728 * 0b00..Interrupt n is low-level sensitive.
18729 * 0b01..Interrupt n is high-level sensitive.
18730 * 0b10..Interrupt n is rising-edge sensitive.
18731 * 0b11..Interrupt n is falling-edge sensitive.
18732 */
18733#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
18734#define GPIO_ICR2_ICR28_MASK (0x3000000U)
18735#define GPIO_ICR2_ICR28_SHIFT (24U)
18736/* ICR28 - ICR28
18737 * 0b00..Interrupt n is low-level sensitive.
18738 * 0b01..Interrupt n is high-level sensitive.
18739 * 0b10..Interrupt n is rising-edge sensitive.
18740 * 0b11..Interrupt n is falling-edge sensitive.
18741 */
18742#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
18743#define GPIO_ICR2_ICR29_MASK (0xC000000U)
18744#define GPIO_ICR2_ICR29_SHIFT (26U)
18745/* ICR29 - ICR29
18746 * 0b00..Interrupt n is low-level sensitive.
18747 * 0b01..Interrupt n is high-level sensitive.
18748 * 0b10..Interrupt n is rising-edge sensitive.
18749 * 0b11..Interrupt n is falling-edge sensitive.
18750 */
18751#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
18752#define GPIO_ICR2_ICR30_MASK (0x30000000U)
18753#define GPIO_ICR2_ICR30_SHIFT (28U)
18754/* ICR30 - ICR30
18755 * 0b00..Interrupt n is low-level sensitive.
18756 * 0b01..Interrupt n is high-level sensitive.
18757 * 0b10..Interrupt n is rising-edge sensitive.
18758 * 0b11..Interrupt n is falling-edge sensitive.
18759 */
18760#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
18761#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
18762#define GPIO_ICR2_ICR31_SHIFT (30U)
18763/* ICR31 - ICR31
18764 * 0b00..Interrupt n is low-level sensitive.
18765 * 0b01..Interrupt n is high-level sensitive.
18766 * 0b10..Interrupt n is rising-edge sensitive.
18767 * 0b11..Interrupt n is falling-edge sensitive.
18768 */
18769#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
18770/* @} */
18771
18772/* @name IMR - GPIO interrupt mask register */
18773/* @{ */
18774#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
18775#define GPIO_IMR_IMR_SHIFT (0U)
18776#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
18777/* @} */
18778
18779/* @name ISR - GPIO interrupt status register */
18780/* @{ */
18781#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
18782#define GPIO_ISR_ISR_SHIFT (0U)
18783#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
18784/* @} */
18785
18786/* @name EDGE_SEL - GPIO edge select register */
18787/* @{ */
18788#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
18789#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
18790#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
18791/* @} */
18792
18793/* @name DR_SET - GPIO data register SET */
18794/* @{ */
18795#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
18796#define GPIO_DR_SET_DR_SET_SHIFT (0U)
18797#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
18798/* @} */
18799
18800/* @name DR_CLEAR - GPIO data register CLEAR */
18801/* @{ */
18802#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
18803#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
18804#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
18805/* @} */
18806
18807/* @name DR_TOGGLE - GPIO data register TOGGLE */
18808/* @{ */
18809#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
18810#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
18811#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
18812/* @} */
18813
18814
18815/*
18816 * @}
18817 */ /* end of group GPIO_Register_Masks */
18818
18819
18820/* GPIO - Peripheral instance base addresses */
18821/* Peripheral GPIO1 base address */
18822#define GPIO1_BASE (0x401B8000u)
18823/* Peripheral GPIO1 base pointer */
18824#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
18825/* Peripheral GPIO2 base address */
18826#define GPIO2_BASE (0x401BC000u)
18827/* Peripheral GPIO2 base pointer */
18828#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
18829/* Peripheral GPIO3 base address */
18830#define GPIO3_BASE (0x401C0000u)
18831/* Peripheral GPIO3 base pointer */
18832#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
18833/* Peripheral GPIO4 base address */
18834#define GPIO4_BASE (0x401C4000u)
18835/* Peripheral GPIO4 base pointer */
18836#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
18837/* Peripheral GPIO5 base address */
18838#define GPIO5_BASE (0x400C0000u)
18839/* Peripheral GPIO5 base pointer */
18840#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
18841/* Peripheral GPIO6 base address */
18842#define GPIO6_BASE (0x42000000u)
18843/* Peripheral GPIO6 base pointer */
18844#define GPIO6 ((GPIO_Type *)GPIO6_BASE)
18845/* Peripheral GPIO7 base address */
18846#define GPIO7_BASE (0x42004000u)
18847/* Peripheral GPIO7 base pointer */
18848#define GPIO7 ((GPIO_Type *)GPIO7_BASE)
18849/* Peripheral GPIO8 base address */
18850#define GPIO8_BASE (0x42008000u)
18851/* Peripheral GPIO8 base pointer */
18852#define GPIO8 ((GPIO_Type *)GPIO8_BASE)
18853/* Peripheral GPIO9 base address */
18854#define GPIO9_BASE (0x4200C000u)
18855/* Peripheral GPIO9 base pointer */
18856#define GPIO9 ((GPIO_Type *)GPIO9_BASE)
18857/* Array initializer of GPIO peripheral base addresses */
18858#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE }
18859/* Array initializer of GPIO peripheral base pointers */
18860#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 }
18861/* Interrupt vectors for the GPIO peripheral type */
18862#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
18863#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }
18864#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn }
18865
18866/*
18867 * @}
18868 */ /* end of group GPIO_Peripheral_Access_Layer */
18869
18870
18871/* ----------------------------------------------------------------------------
18872 -- GPT Peripheral Access Layer
18873 ---------------------------------------------------------------------------- */
18874
18875/*
18876 * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
18877 * @{
18878 */
18879
18880/* GPT - Register Layout Typedef */
18881typedef struct {
18882 __IO uint32_t CR;
18883 __IO uint32_t PR;
18884 __IO uint32_t SR;
18885 __IO uint32_t IR;
18886 __IO uint32_t OCR[3];
18887 __I uint32_t ICR[2];
18888 __I uint32_t CNT;
18889} GPT_Type;
18890
18891/* ----------------------------------------------------------------------------
18892 -- GPT Register Masks
18893 ---------------------------------------------------------------------------- */
18894
18895/*
18896 * @addtogroup GPT_Register_Masks GPT Register Masks
18897 * @{
18898 */
18899
18900/* @name CR - GPT Control Register */
18901/* @{ */
18902#define GPT_CR_EN_MASK (0x1U)
18903#define GPT_CR_EN_SHIFT (0U)
18904/* EN
18905 * 0b0..GPT is disabled.
18906 * 0b1..GPT is enabled.
18907 */
18908#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
18909#define GPT_CR_ENMOD_MASK (0x2U)
18910#define GPT_CR_ENMOD_SHIFT (1U)
18911/* ENMOD
18912 * 0b0..GPT counter will retain its value when it is disabled.
18913 * 0b1..GPT counter value is reset to 0 when it is disabled.
18914 */
18915#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
18916#define GPT_CR_DBGEN_MASK (0x4U)
18917#define GPT_CR_DBGEN_SHIFT (2U)
18918/* DBGEN
18919 * 0b0..GPT is disabled in debug mode.
18920 * 0b1..GPT is enabled in debug mode.
18921 */
18922#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
18923#define GPT_CR_WAITEN_MASK (0x8U)
18924#define GPT_CR_WAITEN_SHIFT (3U)
18925/* WAITEN
18926 * 0b0..GPT is disabled in wait mode.
18927 * 0b1..GPT is enabled in wait mode.
18928 */
18929#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
18930#define GPT_CR_DOZEEN_MASK (0x10U)
18931#define GPT_CR_DOZEEN_SHIFT (4U)
18932/* DOZEEN
18933 * 0b0..GPT is disabled in doze mode.
18934 * 0b1..GPT is enabled in doze mode.
18935 */
18936#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
18937#define GPT_CR_STOPEN_MASK (0x20U)
18938#define GPT_CR_STOPEN_SHIFT (5U)
18939/* STOPEN
18940 * 0b0..GPT is disabled in Stop mode.
18941 * 0b1..GPT is enabled in Stop mode.
18942 */
18943#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
18944#define GPT_CR_CLKSRC_MASK (0x1C0U)
18945#define GPT_CR_CLKSRC_SHIFT (6U)
18946/* CLKSRC
18947 * 0b000..No clock
18948 * 0b001..Peripheral Clock (ipg_clk)
18949 * 0b010..High Frequency Reference Clock (ipg_clk_highfreq)
18950 * 0b011..External Clock
18951 * 0b100..Low Frequency Reference Clock (ipg_clk_32k)
18952 * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
18953 */
18954#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
18955#define GPT_CR_FRR_MASK (0x200U)
18956#define GPT_CR_FRR_SHIFT (9U)
18957/* FRR
18958 * 0b0..Restart mode
18959 * 0b1..Free-Run mode
18960 */
18961#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
18962#define GPT_CR_EN_24M_MASK (0x400U)
18963#define GPT_CR_EN_24M_SHIFT (10U)
18964/* EN_24M
18965 * 0b0..24M clock disabled
18966 * 0b1..24M clock enabled
18967 */
18968#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
18969#define GPT_CR_SWR_MASK (0x8000U)
18970#define GPT_CR_SWR_SHIFT (15U)
18971/* SWR
18972 * 0b0..GPT is not in reset state
18973 * 0b1..GPT is in reset state
18974 */
18975#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
18976#define GPT_CR_IM1_MASK (0x30000U)
18977#define GPT_CR_IM1_SHIFT (16U)
18978#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
18979#define GPT_CR_IM2_MASK (0xC0000U)
18980#define GPT_CR_IM2_SHIFT (18U)
18981/* IM2
18982 * 0b00..capture disabled
18983 * 0b01..capture on rising edge only
18984 * 0b10..capture on falling edge only
18985 * 0b11..capture on both edges
18986 */
18987#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
18988#define GPT_CR_OM1_MASK (0x700000U)
18989#define GPT_CR_OM1_SHIFT (20U)
18990#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
18991#define GPT_CR_OM2_MASK (0x3800000U)
18992#define GPT_CR_OM2_SHIFT (23U)
18993#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
18994#define GPT_CR_OM3_MASK (0x1C000000U)
18995#define GPT_CR_OM3_SHIFT (26U)
18996/* OM3
18997 * 0b000..Output disconnected. No response on pin.
18998 * 0b001..Toggle output pin
18999 * 0b010..Clear output pin
19000 * 0b011..Set output pin
19001 * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
19002 */
19003#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
19004#define GPT_CR_FO1_MASK (0x20000000U)
19005#define GPT_CR_FO1_SHIFT (29U)
19006#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
19007#define GPT_CR_FO2_MASK (0x40000000U)
19008#define GPT_CR_FO2_SHIFT (30U)
19009#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
19010#define GPT_CR_FO3_MASK (0x80000000U)
19011#define GPT_CR_FO3_SHIFT (31U)
19012/* FO3
19013 * 0b0..Writing a 0 has no effect.
19014 * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
19015 */
19016#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
19017/* @} */
19018
19019/* @name PR - GPT Prescaler Register */
19020/* @{ */
19021#define GPT_PR_PRESCALER_MASK (0xFFFU)
19022#define GPT_PR_PRESCALER_SHIFT (0U)
19023/* PRESCALER
19024 * 0b000000000000..Divide by 1
19025 * 0b000000000001..Divide by 2
19026 * 0b111111111111..Divide by 4096
19027 */
19028#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
19029#define GPT_PR_PRESCALER24M_MASK (0xF000U)
19030#define GPT_PR_PRESCALER24M_SHIFT (12U)
19031/* PRESCALER24M
19032 * 0b0000..Divide by 1
19033 * 0b0001..Divide by 2
19034 * 0b1111..Divide by 16
19035 */
19036#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
19037/* @} */
19038
19039/* @name SR - GPT Status Register */
19040/* @{ */
19041#define GPT_SR_OF1_MASK (0x1U)
19042#define GPT_SR_OF1_SHIFT (0U)
19043#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
19044#define GPT_SR_OF2_MASK (0x2U)
19045#define GPT_SR_OF2_SHIFT (1U)
19046#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
19047#define GPT_SR_OF3_MASK (0x4U)
19048#define GPT_SR_OF3_SHIFT (2U)
19049/* OF3
19050 * 0b0..Compare event has not occurred.
19051 * 0b1..Compare event has occurred.
19052 */
19053#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
19054#define GPT_SR_IF1_MASK (0x8U)
19055#define GPT_SR_IF1_SHIFT (3U)
19056#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
19057#define GPT_SR_IF2_MASK (0x10U)
19058#define GPT_SR_IF2_SHIFT (4U)
19059/* IF2
19060 * 0b0..Capture event has not occurred.
19061 * 0b1..Capture event has occurred.
19062 */
19063#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
19064#define GPT_SR_ROV_MASK (0x20U)
19065#define GPT_SR_ROV_SHIFT (5U)
19066/* ROV
19067 * 0b0..Rollover has not occurred.
19068 * 0b1..Rollover has occurred.
19069 */
19070#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
19071/* @} */
19072
19073/* @name IR - GPT Interrupt Register */
19074/* @{ */
19075#define GPT_IR_OF1IE_MASK (0x1U)
19076#define GPT_IR_OF1IE_SHIFT (0U)
19077#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
19078#define GPT_IR_OF2IE_MASK (0x2U)
19079#define GPT_IR_OF2IE_SHIFT (1U)
19080#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
19081#define GPT_IR_OF3IE_MASK (0x4U)
19082#define GPT_IR_OF3IE_SHIFT (2U)
19083/* OF3IE
19084 * 0b0..Output Compare Channel n interrupt is disabled.
19085 * 0b1..Output Compare Channel n interrupt is enabled.
19086 */
19087#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
19088#define GPT_IR_IF1IE_MASK (0x8U)
19089#define GPT_IR_IF1IE_SHIFT (3U)
19090#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
19091#define GPT_IR_IF2IE_MASK (0x10U)
19092#define GPT_IR_IF2IE_SHIFT (4U)
19093/* IF2IE
19094 * 0b0..IF2IE Input Capture n Interrupt Enable is disabled.
19095 * 0b1..IF2IE Input Capture n Interrupt Enable is enabled.
19096 */
19097#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
19098#define GPT_IR_ROVIE_MASK (0x20U)
19099#define GPT_IR_ROVIE_SHIFT (5U)
19100/* ROVIE
19101 * 0b0..Rollover interrupt is disabled.
19102 * 0b1..Rollover interrupt enabled.
19103 */
19104#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
19105/* @} */
19106
19107/* @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
19108/* @{ */
19109#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
19110#define GPT_OCR_COMP_SHIFT (0U)
19111#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
19112/* @} */
19113
19114/* The count of GPT_OCR */
19115#define GPT_OCR_COUNT (3U)
19116
19117/* @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
19118/* @{ */
19119#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
19120#define GPT_ICR_CAPT_SHIFT (0U)
19121#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
19122/* @} */
19123
19124/* The count of GPT_ICR */
19125#define GPT_ICR_COUNT (2U)
19126
19127/* @name CNT - GPT Counter Register */
19128/* @{ */
19129#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
19130#define GPT_CNT_COUNT_SHIFT (0U)
19131#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
19132/* @} */
19133
19134
19135/*
19136 * @}
19137 */ /* end of group GPT_Register_Masks */
19138
19139
19140/* GPT - Peripheral instance base addresses */
19141/* Peripheral GPT1 base address */
19142#define GPT1_BASE (0x401EC000u)
19143/* Peripheral GPT1 base pointer */
19144#define GPT1 ((GPT_Type *)GPT1_BASE)
19145/* Peripheral GPT2 base address */
19146#define GPT2_BASE (0x401F0000u)
19147/* Peripheral GPT2 base pointer */
19148#define GPT2 ((GPT_Type *)GPT2_BASE)
19149/* Array initializer of GPT peripheral base addresses */
19150#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE }
19151/* Array initializer of GPT peripheral base pointers */
19152#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 }
19153/* Interrupt vectors for the GPT peripheral type */
19154#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn }
19155
19156/*
19157 * @}
19158 */ /* end of group GPT_Peripheral_Access_Layer */
19159
19160
19161/* ----------------------------------------------------------------------------
19162 -- I2S Peripheral Access Layer
19163 ---------------------------------------------------------------------------- */
19164
19165/*
19166 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
19167 * @{
19168 */
19169
19170/* I2S - Register Layout Typedef */
19171typedef struct {
19172 __I uint32_t VERID;
19173 __I uint32_t PARAM;
19174 __IO uint32_t TCSR;
19175 __IO uint32_t TCR1;
19176 __IO uint32_t TCR2;
19177 __IO uint32_t TCR3;
19178 __IO uint32_t TCR4;
19179 __IO uint32_t TCR5;
19180 __O uint32_t TDR[4];
19181 uint8_t RESERVED_0[16];
19182 __I uint32_t TFR[4];
19183 uint8_t RESERVED_1[16];
19184 __IO uint32_t TMR;
19185 uint8_t RESERVED_2[36];
19186 __IO uint32_t RCSR;
19187 __IO uint32_t RCR1;
19188 __IO uint32_t RCR2;
19189 __IO uint32_t RCR3;
19190 __IO uint32_t RCR4;
19191 __IO uint32_t RCR5;
19192 __I uint32_t RDR[4];
19193 uint8_t RESERVED_3[16];
19194 __I uint32_t RFR[4];
19195 uint8_t RESERVED_4[16];
19196 __IO uint32_t RMR;
19197} I2S_Type;
19198
19199/* ----------------------------------------------------------------------------
19200 -- I2S Register Masks
19201 ---------------------------------------------------------------------------- */
19202
19203/*
19204 * @addtogroup I2S_Register_Masks I2S Register Masks
19205 * @{
19206 */
19207
19208/* @name VERID - Version ID Register */
19209/* @{ */
19210#define I2S_VERID_FEATURE_MASK (0xFFFFU)
19211#define I2S_VERID_FEATURE_SHIFT (0U)
19212/* FEATURE - Feature Specification Number
19213 * 0b0000000000000000..Standard feature set.
19214 */
19215#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
19216#define I2S_VERID_MINOR_MASK (0xFF0000U)
19217#define I2S_VERID_MINOR_SHIFT (16U)
19218#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
19219#define I2S_VERID_MAJOR_MASK (0xFF000000U)
19220#define I2S_VERID_MAJOR_SHIFT (24U)
19221#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
19222/* @} */
19223
19224/* @name PARAM - Parameter Register */
19225/* @{ */
19226#define I2S_PARAM_DATALINE_MASK (0xFU)
19227#define I2S_PARAM_DATALINE_SHIFT (0U)
19228#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
19229#define I2S_PARAM_FIFO_MASK (0xF00U)
19230#define I2S_PARAM_FIFO_SHIFT (8U)
19231#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
19232#define I2S_PARAM_FRAME_MASK (0xF0000U)
19233#define I2S_PARAM_FRAME_SHIFT (16U)
19234#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
19235/* @} */
19236
19237/* @name TCSR - SAI Transmit Control Register */
19238/* @{ */
19239#define I2S_TCSR_FRDE_MASK (0x1U)
19240#define I2S_TCSR_FRDE_SHIFT (0U)
19241/* FRDE - FIFO Request DMA Enable
19242 * 0b0..Disables the DMA request.
19243 * 0b1..Enables the DMA request.
19244 */
19245#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
19246#define I2S_TCSR_FWDE_MASK (0x2U)
19247#define I2S_TCSR_FWDE_SHIFT (1U)
19248/* FWDE - FIFO Warning DMA Enable
19249 * 0b0..Disables the DMA request.
19250 * 0b1..Enables the DMA request.
19251 */
19252#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
19253#define I2S_TCSR_FRIE_MASK (0x100U)
19254#define I2S_TCSR_FRIE_SHIFT (8U)
19255/* FRIE - FIFO Request Interrupt Enable
19256 * 0b0..Disables the interrupt.
19257 * 0b1..Enables the interrupt.
19258 */
19259#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
19260#define I2S_TCSR_FWIE_MASK (0x200U)
19261#define I2S_TCSR_FWIE_SHIFT (9U)
19262/* FWIE - FIFO Warning Interrupt Enable
19263 * 0b0..Disables the interrupt.
19264 * 0b1..Enables the interrupt.
19265 */
19266#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
19267#define I2S_TCSR_FEIE_MASK (0x400U)
19268#define I2S_TCSR_FEIE_SHIFT (10U)
19269/* FEIE - FIFO Error Interrupt Enable
19270 * 0b0..Disables the interrupt.
19271 * 0b1..Enables the interrupt.
19272 */
19273#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
19274#define I2S_TCSR_SEIE_MASK (0x800U)
19275#define I2S_TCSR_SEIE_SHIFT (11U)
19276/* SEIE - Sync Error Interrupt Enable
19277 * 0b0..Disables interrupt.
19278 * 0b1..Enables interrupt.
19279 */
19280#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
19281#define I2S_TCSR_WSIE_MASK (0x1000U)
19282#define I2S_TCSR_WSIE_SHIFT (12U)
19283/* WSIE - Word Start Interrupt Enable
19284 * 0b0..Disables interrupt.
19285 * 0b1..Enables interrupt.
19286 */
19287#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
19288#define I2S_TCSR_FRF_MASK (0x10000U)
19289#define I2S_TCSR_FRF_SHIFT (16U)
19290/* FRF - FIFO Request Flag
19291 * 0b0..Transmit FIFO watermark has not been reached.
19292 * 0b1..Transmit FIFO watermark has been reached.
19293 */
19294#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
19295#define I2S_TCSR_FWF_MASK (0x20000U)
19296#define I2S_TCSR_FWF_SHIFT (17U)
19297/* FWF - FIFO Warning Flag
19298 * 0b0..No enabled transmit FIFO is empty.
19299 * 0b1..Enabled transmit FIFO is empty.
19300 */
19301#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
19302#define I2S_TCSR_FEF_MASK (0x40000U)
19303#define I2S_TCSR_FEF_SHIFT (18U)
19304/* FEF - FIFO Error Flag
19305 * 0b0..Transmit underrun not detected.
19306 * 0b1..Transmit underrun detected.
19307 */
19308#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
19309#define I2S_TCSR_SEF_MASK (0x80000U)
19310#define I2S_TCSR_SEF_SHIFT (19U)
19311/* SEF - Sync Error Flag
19312 * 0b0..Sync error not detected.
19313 * 0b1..Frame sync error detected.
19314 */
19315#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
19316#define I2S_TCSR_WSF_MASK (0x100000U)
19317#define I2S_TCSR_WSF_SHIFT (20U)
19318/* WSF - Word Start Flag
19319 * 0b0..Start of word not detected.
19320 * 0b1..Start of word detected.
19321 */
19322#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
19323#define I2S_TCSR_SR_MASK (0x1000000U)
19324#define I2S_TCSR_SR_SHIFT (24U)
19325/* SR - Software Reset
19326 * 0b0..No effect.
19327 * 0b1..Software reset.
19328 */
19329#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
19330#define I2S_TCSR_FR_MASK (0x2000000U)
19331#define I2S_TCSR_FR_SHIFT (25U)
19332/* FR - FIFO Reset
19333 * 0b0..No effect.
19334 * 0b1..FIFO reset.
19335 */
19336#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
19337#define I2S_TCSR_BCE_MASK (0x10000000U)
19338#define I2S_TCSR_BCE_SHIFT (28U)
19339/* BCE - Bit Clock Enable
19340 * 0b0..Transmit bit clock is disabled.
19341 * 0b1..Transmit bit clock is enabled.
19342 */
19343#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
19344#define I2S_TCSR_DBGE_MASK (0x20000000U)
19345#define I2S_TCSR_DBGE_SHIFT (29U)
19346/* DBGE - Debug Enable
19347 * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
19348 * 0b1..Transmitter is enabled in Debug mode.
19349 */
19350#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
19351#define I2S_TCSR_STOPE_MASK (0x40000000U)
19352#define I2S_TCSR_STOPE_SHIFT (30U)
19353/* STOPE - Stop Enable
19354 * 0b0..Transmitter disabled in Stop mode.
19355 * 0b1..Transmitter enabled in Stop mode.
19356 */
19357#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
19358#define I2S_TCSR_TE_MASK (0x80000000U)
19359#define I2S_TCSR_TE_SHIFT (31U)
19360/* TE - Transmitter Enable
19361 * 0b0..Transmitter is disabled.
19362 * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
19363 */
19364#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
19365/* @} */
19366
19367/* @name TCR1 - SAI Transmit Configuration 1 Register */
19368/* @{ */
19369#define I2S_TCR1_TFW_MASK (0x1FU)
19370#define I2S_TCR1_TFW_SHIFT (0U)
19371#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
19372/* @} */
19373
19374/* @name TCR2 - SAI Transmit Configuration 2 Register */
19375/* @{ */
19376#define I2S_TCR2_DIV_MASK (0xFFU)
19377#define I2S_TCR2_DIV_SHIFT (0U)
19378#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
19379#define I2S_TCR2_BCD_MASK (0x1000000U)
19380#define I2S_TCR2_BCD_SHIFT (24U)
19381/* BCD - Bit Clock Direction
19382 * 0b0..Bit clock is generated externally in Slave mode.
19383 * 0b1..Bit clock is generated internally in Master mode.
19384 */
19385#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
19386#define I2S_TCR2_BCP_MASK (0x2000000U)
19387#define I2S_TCR2_BCP_SHIFT (25U)
19388/* BCP - Bit Clock Polarity
19389 * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
19390 * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
19391 */
19392#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
19393#define I2S_TCR2_MSEL_MASK (0xC000000U)
19394#define I2S_TCR2_MSEL_SHIFT (26U)
19395/* MSEL - MCLK Select
19396 * 0b00..Bus Clock selected.
19397 * 0b01..Master Clock (MCLK) 1 option selected.
19398 * 0b10..Master Clock (MCLK) 2 option selected.
19399 * 0b11..Master Clock (MCLK) 3 option selected.
19400 */
19401#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
19402#define I2S_TCR2_BCI_MASK (0x10000000U)
19403#define I2S_TCR2_BCI_SHIFT (28U)
19404/* BCI - Bit Clock Input
19405 * 0b0..No effect.
19406 * 0b1..Internal logic is clocked as if bit clock was externally generated.
19407 */
19408#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
19409#define I2S_TCR2_BCS_MASK (0x20000000U)
19410#define I2S_TCR2_BCS_SHIFT (29U)
19411/* BCS - Bit Clock Swap
19412 * 0b0..Use the normal bit clock source.
19413 * 0b1..Swap the bit clock source.
19414 */
19415#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
19416#define I2S_TCR2_SYNC_MASK (0xC0000000U)
19417#define I2S_TCR2_SYNC_SHIFT (30U)
19418/* SYNC - Synchronous Mode
19419 * 0b00..Asynchronous mode.
19420 * 0b01..Synchronous with receiver.
19421 * 0b10..Reserved.
19422 * 0b11..Reserved.
19423 */
19424#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
19425/* @} */
19426
19427/* @name TCR3 - SAI Transmit Configuration 3 Register */
19428/* @{ */
19429#define I2S_TCR3_WDFL_MASK (0x1FU)
19430#define I2S_TCR3_WDFL_SHIFT (0U)
19431#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
19432#define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
19433#define I2S_TCR3_TCE_SHIFT (16U)
19434#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
19435#define I2S_TCR3_CFR_MASK (0xF000000U)
19436#define I2S_TCR3_CFR_SHIFT (24U)
19437#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
19438/* @} */
19439
19440/* @name TCR4 - SAI Transmit Configuration 4 Register */
19441/* @{ */
19442#define I2S_TCR4_FSD_MASK (0x1U)
19443#define I2S_TCR4_FSD_SHIFT (0U)
19444/* FSD - Frame Sync Direction
19445 * 0b0..Frame sync is generated externally in Slave mode.
19446 * 0b1..Frame sync is generated internally in Master mode.
19447 */
19448#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
19449#define I2S_TCR4_FSP_MASK (0x2U)
19450#define I2S_TCR4_FSP_SHIFT (1U)
19451/* FSP - Frame Sync Polarity
19452 * 0b0..Frame sync is active high.
19453 * 0b1..Frame sync is active low.
19454 */
19455#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
19456#define I2S_TCR4_ONDEM_MASK (0x4U)
19457#define I2S_TCR4_ONDEM_SHIFT (2U)
19458/* ONDEM - On Demand Mode
19459 * 0b0..Internal frame sync is generated continuously.
19460 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
19461 */
19462#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
19463#define I2S_TCR4_FSE_MASK (0x8U)
19464#define I2S_TCR4_FSE_SHIFT (3U)
19465/* FSE - Frame Sync Early
19466 * 0b0..Frame sync asserts with the first bit of the frame.
19467 * 0b1..Frame sync asserts one bit before the first bit of the frame.
19468 */
19469#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
19470#define I2S_TCR4_MF_MASK (0x10U)
19471#define I2S_TCR4_MF_SHIFT (4U)
19472/* MF - MSB First
19473 * 0b0..LSB is transmitted first.
19474 * 0b1..MSB is transmitted first.
19475 */
19476#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
19477#define I2S_TCR4_CHMOD_MASK (0x20U)
19478#define I2S_TCR4_CHMOD_SHIFT (5U)
19479/* CHMOD - Channel Mode
19480 * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
19481 * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
19482 */
19483#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
19484#define I2S_TCR4_SYWD_MASK (0x1F00U)
19485#define I2S_TCR4_SYWD_SHIFT (8U)
19486#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
19487#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
19488#define I2S_TCR4_FRSZ_SHIFT (16U)
19489#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
19490#define I2S_TCR4_FPACK_MASK (0x3000000U)
19491#define I2S_TCR4_FPACK_SHIFT (24U)
19492/* FPACK - FIFO Packing Mode
19493 * 0b00..FIFO packing is disabled
19494 * 0b01..Reserved
19495 * 0b10..8-bit FIFO packing is enabled
19496 * 0b11..16-bit FIFO packing is enabled
19497 */
19498#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
19499#define I2S_TCR4_FCOMB_MASK (0xC000000U)
19500#define I2S_TCR4_FCOMB_SHIFT (26U)
19501/* FCOMB - FIFO Combine Mode
19502 * 0b00..FIFO combine mode disabled.
19503 * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
19504 * 0b10..FIFO combine mode enabled on FIFO writes (by software).
19505 * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
19506 */
19507#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
19508#define I2S_TCR4_FCONT_MASK (0x10000000U)
19509#define I2S_TCR4_FCONT_SHIFT (28U)
19510/* FCONT - FIFO Continue on Error
19511 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
19512 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
19513 */
19514#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
19515/* @} */
19516
19517/* @name TCR5 - SAI Transmit Configuration 5 Register */
19518/* @{ */
19519#define I2S_TCR5_FBT_MASK (0x1F00U)
19520#define I2S_TCR5_FBT_SHIFT (8U)
19521#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
19522#define I2S_TCR5_W0W_MASK (0x1F0000U)
19523#define I2S_TCR5_W0W_SHIFT (16U)
19524#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
19525#define I2S_TCR5_WNW_MASK (0x1F000000U)
19526#define I2S_TCR5_WNW_SHIFT (24U)
19527#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
19528/* @} */
19529
19530/* @name TDR - SAI Transmit Data Register */
19531/* @{ */
19532#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
19533#define I2S_TDR_TDR_SHIFT (0U)
19534#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
19535/* @} */
19536
19537/* The count of I2S_TDR */
19538#define I2S_TDR_COUNT (4U)
19539
19540/* @name TFR - SAI Transmit FIFO Register */
19541/* @{ */
19542#define I2S_TFR_RFP_MASK (0x3FU)
19543#define I2S_TFR_RFP_SHIFT (0U)
19544#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
19545#define I2S_TFR_WFP_MASK (0x3F0000U)
19546#define I2S_TFR_WFP_SHIFT (16U)
19547#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
19548#define I2S_TFR_WCP_MASK (0x80000000U)
19549#define I2S_TFR_WCP_SHIFT (31U)
19550/* WCP - Write Channel Pointer
19551 * 0b0..No effect.
19552 * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
19553 */
19554#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
19555/* @} */
19556
19557/* The count of I2S_TFR */
19558#define I2S_TFR_COUNT (4U)
19559
19560/* @name TMR - SAI Transmit Mask Register */
19561/* @{ */
19562#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
19563#define I2S_TMR_TWM_SHIFT (0U)
19564/* TWM - Transmit Word Mask
19565 * 0b00000000000000000000000000000000..Word N is enabled.
19566 * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
19567 */
19568#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
19569/* @} */
19570
19571/* @name RCSR - SAI Receive Control Register */
19572/* @{ */
19573#define I2S_RCSR_FRDE_MASK (0x1U)
19574#define I2S_RCSR_FRDE_SHIFT (0U)
19575/* FRDE - FIFO Request DMA Enable
19576 * 0b0..Disables the DMA request.
19577 * 0b1..Enables the DMA request.
19578 */
19579#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
19580#define I2S_RCSR_FWDE_MASK (0x2U)
19581#define I2S_RCSR_FWDE_SHIFT (1U)
19582/* FWDE - FIFO Warning DMA Enable
19583 * 0b0..Disables the DMA request.
19584 * 0b1..Enables the DMA request.
19585 */
19586#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
19587#define I2S_RCSR_FRIE_MASK (0x100U)
19588#define I2S_RCSR_FRIE_SHIFT (8U)
19589/* FRIE - FIFO Request Interrupt Enable
19590 * 0b0..Disables the interrupt.
19591 * 0b1..Enables the interrupt.
19592 */
19593#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
19594#define I2S_RCSR_FWIE_MASK (0x200U)
19595#define I2S_RCSR_FWIE_SHIFT (9U)
19596/* FWIE - FIFO Warning Interrupt Enable
19597 * 0b0..Disables the interrupt.
19598 * 0b1..Enables the interrupt.
19599 */
19600#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
19601#define I2S_RCSR_FEIE_MASK (0x400U)
19602#define I2S_RCSR_FEIE_SHIFT (10U)
19603/* FEIE - FIFO Error Interrupt Enable
19604 * 0b0..Disables the interrupt.
19605 * 0b1..Enables the interrupt.
19606 */
19607#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
19608#define I2S_RCSR_SEIE_MASK (0x800U)
19609#define I2S_RCSR_SEIE_SHIFT (11U)
19610/* SEIE - Sync Error Interrupt Enable
19611 * 0b0..Disables interrupt.
19612 * 0b1..Enables interrupt.
19613 */
19614#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
19615#define I2S_RCSR_WSIE_MASK (0x1000U)
19616#define I2S_RCSR_WSIE_SHIFT (12U)
19617/* WSIE - Word Start Interrupt Enable
19618 * 0b0..Disables interrupt.
19619 * 0b1..Enables interrupt.
19620 */
19621#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
19622#define I2S_RCSR_FRF_MASK (0x10000U)
19623#define I2S_RCSR_FRF_SHIFT (16U)
19624/* FRF - FIFO Request Flag
19625 * 0b0..Receive FIFO watermark not reached.
19626 * 0b1..Receive FIFO watermark has been reached.
19627 */
19628#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
19629#define I2S_RCSR_FWF_MASK (0x20000U)
19630#define I2S_RCSR_FWF_SHIFT (17U)
19631/* FWF - FIFO Warning Flag
19632 * 0b0..No enabled receive FIFO is full.
19633 * 0b1..Enabled receive FIFO is full.
19634 */
19635#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
19636#define I2S_RCSR_FEF_MASK (0x40000U)
19637#define I2S_RCSR_FEF_SHIFT (18U)
19638/* FEF - FIFO Error Flag
19639 * 0b0..Receive overflow not detected.
19640 * 0b1..Receive overflow detected.
19641 */
19642#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
19643#define I2S_RCSR_SEF_MASK (0x80000U)
19644#define I2S_RCSR_SEF_SHIFT (19U)
19645/* SEF - Sync Error Flag
19646 * 0b0..Sync error not detected.
19647 * 0b1..Frame sync error detected.
19648 */
19649#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
19650#define I2S_RCSR_WSF_MASK (0x100000U)
19651#define I2S_RCSR_WSF_SHIFT (20U)
19652/* WSF - Word Start Flag
19653 * 0b0..Start of word not detected.
19654 * 0b1..Start of word detected.
19655 */
19656#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
19657#define I2S_RCSR_SR_MASK (0x1000000U)
19658#define I2S_RCSR_SR_SHIFT (24U)
19659/* SR - Software Reset
19660 * 0b0..No effect.
19661 * 0b1..Software reset.
19662 */
19663#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
19664#define I2S_RCSR_FR_MASK (0x2000000U)
19665#define I2S_RCSR_FR_SHIFT (25U)
19666/* FR - FIFO Reset
19667 * 0b0..No effect.
19668 * 0b1..FIFO reset.
19669 */
19670#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
19671#define I2S_RCSR_BCE_MASK (0x10000000U)
19672#define I2S_RCSR_BCE_SHIFT (28U)
19673/* BCE - Bit Clock Enable
19674 * 0b0..Receive bit clock is disabled.
19675 * 0b1..Receive bit clock is enabled.
19676 */
19677#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
19678#define I2S_RCSR_DBGE_MASK (0x20000000U)
19679#define I2S_RCSR_DBGE_SHIFT (29U)
19680/* DBGE - Debug Enable
19681 * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
19682 * 0b1..Receiver is enabled in Debug mode.
19683 */
19684#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
19685#define I2S_RCSR_STOPE_MASK (0x40000000U)
19686#define I2S_RCSR_STOPE_SHIFT (30U)
19687/* STOPE - Stop Enable
19688 * 0b0..Receiver disabled in Stop mode.
19689 * 0b1..Receiver enabled in Stop mode.
19690 */
19691#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
19692#define I2S_RCSR_RE_MASK (0x80000000U)
19693#define I2S_RCSR_RE_SHIFT (31U)
19694/* RE - Receiver Enable
19695 * 0b0..Receiver is disabled.
19696 * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
19697 */
19698#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
19699/* @} */
19700
19701/* @name RCR1 - SAI Receive Configuration 1 Register */
19702/* @{ */
19703#define I2S_RCR1_RFW_MASK (0x1FU)
19704#define I2S_RCR1_RFW_SHIFT (0U)
19705#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
19706/* @} */
19707
19708/* @name RCR2 - SAI Receive Configuration 2 Register */
19709/* @{ */
19710#define I2S_RCR2_DIV_MASK (0xFFU)
19711#define I2S_RCR2_DIV_SHIFT (0U)
19712#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
19713#define I2S_RCR2_BCD_MASK (0x1000000U)
19714#define I2S_RCR2_BCD_SHIFT (24U)
19715/* BCD - Bit Clock Direction
19716 * 0b0..Bit clock is generated externally in Slave mode.
19717 * 0b1..Bit clock is generated internally in Master mode.
19718 */
19719#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
19720#define I2S_RCR2_BCP_MASK (0x2000000U)
19721#define I2S_RCR2_BCP_SHIFT (25U)
19722/* BCP - Bit Clock Polarity
19723 * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
19724 * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
19725 */
19726#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
19727#define I2S_RCR2_MSEL_MASK (0xC000000U)
19728#define I2S_RCR2_MSEL_SHIFT (26U)
19729/* MSEL - MCLK Select
19730 * 0b00..Bus Clock selected.
19731 * 0b01..Master Clock (MCLK) 1 option selected.
19732 * 0b10..Master Clock (MCLK) 2 option selected.
19733 * 0b11..Master Clock (MCLK) 3 option selected.
19734 */
19735#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
19736#define I2S_RCR2_BCI_MASK (0x10000000U)
19737#define I2S_RCR2_BCI_SHIFT (28U)
19738/* BCI - Bit Clock Input
19739 * 0b0..No effect.
19740 * 0b1..Internal logic is clocked as if bit clock was externally generated.
19741 */
19742#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
19743#define I2S_RCR2_BCS_MASK (0x20000000U)
19744#define I2S_RCR2_BCS_SHIFT (29U)
19745/* BCS - Bit Clock Swap
19746 * 0b0..Use the normal bit clock source.
19747 * 0b1..Swap the bit clock source.
19748 */
19749#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
19750#define I2S_RCR2_SYNC_MASK (0xC0000000U)
19751#define I2S_RCR2_SYNC_SHIFT (30U)
19752/* SYNC - Synchronous Mode
19753 * 0b00..Asynchronous mode.
19754 * 0b01..Synchronous with transmitter.
19755 * 0b10..Reserved.
19756 * 0b11..Reserved.
19757 */
19758#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
19759/* @} */
19760
19761/* @name RCR3 - SAI Receive Configuration 3 Register */
19762/* @{ */
19763#define I2S_RCR3_WDFL_MASK (0x1FU)
19764#define I2S_RCR3_WDFL_SHIFT (0U)
19765#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
19766#define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
19767#define I2S_RCR3_RCE_SHIFT (16U)
19768#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
19769#define I2S_RCR3_CFR_MASK (0xF000000U)
19770#define I2S_RCR3_CFR_SHIFT (24U)
19771#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
19772/* @} */
19773
19774/* @name RCR4 - SAI Receive Configuration 4 Register */
19775/* @{ */
19776#define I2S_RCR4_FSD_MASK (0x1U)
19777#define I2S_RCR4_FSD_SHIFT (0U)
19778/* FSD - Frame Sync Direction
19779 * 0b0..Frame Sync is generated externally in Slave mode.
19780 * 0b1..Frame Sync is generated internally in Master mode.
19781 */
19782#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
19783#define I2S_RCR4_FSP_MASK (0x2U)
19784#define I2S_RCR4_FSP_SHIFT (1U)
19785/* FSP - Frame Sync Polarity
19786 * 0b0..Frame sync is active high.
19787 * 0b1..Frame sync is active low.
19788 */
19789#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
19790#define I2S_RCR4_ONDEM_MASK (0x4U)
19791#define I2S_RCR4_ONDEM_SHIFT (2U)
19792/* ONDEM - On Demand Mode
19793 * 0b0..Internal frame sync is generated continuously.
19794 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
19795 */
19796#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
19797#define I2S_RCR4_FSE_MASK (0x8U)
19798#define I2S_RCR4_FSE_SHIFT (3U)
19799/* FSE - Frame Sync Early
19800 * 0b0..Frame sync asserts with the first bit of the frame.
19801 * 0b1..Frame sync asserts one bit before the first bit of the frame.
19802 */
19803#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
19804#define I2S_RCR4_MF_MASK (0x10U)
19805#define I2S_RCR4_MF_SHIFT (4U)
19806/* MF - MSB First
19807 * 0b0..LSB is received first.
19808 * 0b1..MSB is received first.
19809 */
19810#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
19811#define I2S_RCR4_SYWD_MASK (0x1F00U)
19812#define I2S_RCR4_SYWD_SHIFT (8U)
19813#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
19814#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
19815#define I2S_RCR4_FRSZ_SHIFT (16U)
19816#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
19817#define I2S_RCR4_FPACK_MASK (0x3000000U)
19818#define I2S_RCR4_FPACK_SHIFT (24U)
19819/* FPACK - FIFO Packing Mode
19820 * 0b00..FIFO packing is disabled
19821 * 0b01..Reserved.
19822 * 0b10..8-bit FIFO packing is enabled
19823 * 0b11..16-bit FIFO packing is enabled
19824 */
19825#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
19826#define I2S_RCR4_FCOMB_MASK (0xC000000U)
19827#define I2S_RCR4_FCOMB_SHIFT (26U)
19828/* FCOMB - FIFO Combine Mode
19829 * 0b00..FIFO combine mode disabled.
19830 * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
19831 * 0b10..FIFO combine mode enabled on FIFO reads (by software).
19832 * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
19833 */
19834#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
19835#define I2S_RCR4_FCONT_MASK (0x10000000U)
19836#define I2S_RCR4_FCONT_SHIFT (28U)
19837/* FCONT - FIFO Continue on Error
19838 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
19839 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
19840 */
19841#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
19842/* @} */
19843
19844/* @name RCR5 - SAI Receive Configuration 5 Register */
19845/* @{ */
19846#define I2S_RCR5_FBT_MASK (0x1F00U)
19847#define I2S_RCR5_FBT_SHIFT (8U)
19848#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
19849#define I2S_RCR5_W0W_MASK (0x1F0000U)
19850#define I2S_RCR5_W0W_SHIFT (16U)
19851#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
19852#define I2S_RCR5_WNW_MASK (0x1F000000U)
19853#define I2S_RCR5_WNW_SHIFT (24U)
19854#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
19855/* @} */
19856
19857/* @name RDR - SAI Receive Data Register */
19858/* @{ */
19859#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
19860#define I2S_RDR_RDR_SHIFT (0U)
19861#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
19862/* @} */
19863
19864/* The count of I2S_RDR */
19865#define I2S_RDR_COUNT (4U)
19866
19867/* @name RFR - SAI Receive FIFO Register */
19868/* @{ */
19869#define I2S_RFR_RFP_MASK (0x3FU)
19870#define I2S_RFR_RFP_SHIFT (0U)
19871#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
19872#define I2S_RFR_RCP_MASK (0x8000U)
19873#define I2S_RFR_RCP_SHIFT (15U)
19874/* RCP - Receive Channel Pointer
19875 * 0b0..No effect.
19876 * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
19877 */
19878#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
19879#define I2S_RFR_WFP_MASK (0x3F0000U)
19880#define I2S_RFR_WFP_SHIFT (16U)
19881#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
19882/* @} */
19883
19884/* The count of I2S_RFR */
19885#define I2S_RFR_COUNT (4U)
19886
19887/* @name RMR - SAI Receive Mask Register */
19888/* @{ */
19889#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
19890#define I2S_RMR_RWM_SHIFT (0U)
19891/* RWM - Receive Word Mask
19892 * 0b00000000000000000000000000000000..Word N is enabled.
19893 * 0b00000000000000000000000000000001..Word N is masked.
19894 */
19895#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
19896/* @} */
19897
19898
19899/*
19900 * @}
19901 */ /* end of group I2S_Register_Masks */
19902
19903
19904/* I2S - Peripheral instance base addresses */
19905/* Peripheral SAI1 base address */
19906#define SAI1_BASE (0x40384000u)
19907/* Peripheral SAI1 base pointer */
19908#define SAI1 ((I2S_Type *)SAI1_BASE)
19909/* Peripheral SAI2 base address */
19910#define SAI2_BASE (0x40388000u)
19911/* Peripheral SAI2 base pointer */
19912#define SAI2 ((I2S_Type *)SAI2_BASE)
19913/* Peripheral SAI3 base address */
19914#define SAI3_BASE (0x4038C000u)
19915/* Peripheral SAI3 base pointer */
19916#define SAI3 ((I2S_Type *)SAI3_BASE)
19917/* Array initializer of I2S peripheral base addresses */
19918#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE }
19919/* Array initializer of I2S peripheral base pointers */
19920#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 }
19921/* Interrupt vectors for the I2S peripheral type */
19922#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn }
19923#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn }
19924
19925/*
19926 * @}
19927 */ /* end of group I2S_Peripheral_Access_Layer */
19928
19929
19930/* ----------------------------------------------------------------------------
19931 -- IOMUXC Peripheral Access Layer
19932 ---------------------------------------------------------------------------- */
19933
19934/*
19935 * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
19936 * @{
19937 */
19938
19939/* IOMUXC - Register Layout Typedef */
19940typedef struct {
19941 uint8_t RESERVED_0[20];
19942 __IO uint32_t SW_MUX_CTL_PAD[124];
19943 __IO uint32_t SW_PAD_CTL_PAD[124];
19944 __IO uint32_t SELECT_INPUT[154];
19945 __IO uint32_t SW_MUX_CTL_PAD_1[22];
19946 __IO uint32_t SW_PAD_CTL_PAD_1[22];
19947 __IO uint32_t SELECT_INPUT_1[33];
19948} IOMUXC_Type;
19949
19950/* ----------------------------------------------------------------------------
19951 -- IOMUXC Register Masks
19952 ---------------------------------------------------------------------------- */
19953
19954/*
19955 * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
19956 * @{
19957 */
19958
19959/* @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */
19960/* @{ */
19961#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
19962#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
19963/* MUX_MODE - MUX Mode Select Field.
19964 * 0b000..Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: semc
19965 * 0b001..Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4
19966 * 0b010..Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2
19967 * 0b011..Select mux mode: ALT3 mux port: XBAR1_XBAR_IN02 of instance: xbar1
19968 * 0b100..Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1
19969 * 0b101..Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4
19970 */
19971#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */
19972#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
19973#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
19974/* SION - Software Input On Field.
19975 * 0b1..Force input path of pad GPIO_EMC_00
19976 * 0b0..Input Path is determined by functionality
19977 */
19978#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
19979/* @} */
19980
19981/* The count of IOMUXC_SW_MUX_CTL_PAD */
19982#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U)
19983
19984/* @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */
19985/* @{ */
19986#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
19987#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
19988/* SRE - Slew Rate Field
19989 * 0b0..Slow Slew Rate
19990 * 0b1..Fast Slew Rate
19991 */
19992#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
19993#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U)
19994#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U)
19995/* DSE - Drive Strength Field
19996 * 0b000..output driver disabled;
19997 * 0b001..R0(150 Ohm @ 3.3V, 260 [email protected])
19998 * 0b010..R0/2
19999 * 0b011..R0/3
20000 * 0b100..R0/4
20001 * 0b101..R0/5
20002 * 0b110..R0/6
20003 * 0b111..R0/7
20004 */
20005#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
20006#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U)
20007#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U)
20008/* SPEED - Speed Field
20009 * 0b00..low(50MHz)
20010 * 0b01..medium(100MHz)
20011 * 0b10..medium(100MHz)
20012 * 0b11..max(200MHz)
20013 */
20014#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)
20015#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U)
20016#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U)
20017/* ODE - Open Drain Enable Field
20018 * 0b0..Open Drain Disabled
20019 * 0b1..Open Drain Enabled
20020 */
20021#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
20022#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U)
20023#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U)
20024/* PKE - Pull / Keep Enable Field
20025 * 0b0..Pull/Keeper Disabled
20026 * 0b1..Pull/Keeper Enabled
20027 */
20028#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK)
20029#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U)
20030#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U)
20031/* PUE - Pull / Keep Select Field
20032 * 0b0..Keeper
20033 * 0b1..Pull
20034 */
20035#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
20036#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U)
20037#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U)
20038/* PUS - Pull Up / Down Config. Field
20039 * 0b00..100K Ohm Pull Down
20040 * 0b01..47K Ohm Pull Up
20041 * 0b10..100K Ohm Pull Up
20042 * 0b11..22K Ohm Pull Up
20043 */
20044#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
20045#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U)
20046#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U)
20047/* HYS - Hyst. Enable Field
20048 * 0b0..Hysteresis Disabled
20049 * 0b1..Hysteresis Enabled
20050 */
20051#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
20052/* @} */
20053
20054/* The count of IOMUXC_SW_PAD_CTL_PAD */
20055#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U)
20056
20057/* @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */
20058/* @{ */
20059#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
20060#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
20061/* DAISY - Selecting Pads Involved in Daisy Chain.
20062 * 0b0..Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3
20063 * 0b1..Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0
20064 */
20065#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */
20066/* @} */
20067
20068/* The count of IOMUXC_SELECT_INPUT */
20069#define IOMUXC_SELECT_INPUT_COUNT (154U)
20070
20071/* @name SW_MUX_CTL_PAD_1 - SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register */
20072/* @{ */
20073#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK (0x7U)
20074#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT (0U)
20075/* MUX_MODE - MUX Mode Select Field.
20076 * 0b000..Select mux mode: ALT0 mux port: FLEXSPI2_B_SCLK of instance: flexspi2
20077 */
20078#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK)
20079#define IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK (0x10U)
20080#define IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT (4U)
20081/* SION - Software Input On Field.
20082 * 0b1..Force input path of pad GPIO_SPI_B0_00
20083 * 0b0..Input Path is determined by functionality
20084 */
20085#define IOMUXC_SW_MUX_CTL_PAD_1_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK)
20086/* @} */
20087
20088/* The count of IOMUXC_SW_MUX_CTL_PAD_1 */
20089#define IOMUXC_SW_MUX_CTL_PAD_1_COUNT (22U)
20090
20091/* @name SW_PAD_CTL_PAD_1 - SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register */
20092/* @{ */
20093#define IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK (0x1U)
20094#define IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT (0U)
20095/* SRE - Slew Rate Field
20096 * 0b0..Slow Slew Rate
20097 * 0b1..Fast Slew Rate
20098 */
20099#define IOMUXC_SW_PAD_CTL_PAD_1_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK)
20100#define IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK (0x38U)
20101#define IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT (3U)
20102/* DSE - Drive Strength Field
20103 * 0b000..output driver disabled;
20104 * 0b001..R0(150 Ohm @ 3.3V, 260 [email protected])
20105 * 0b010..R0/2
20106 * 0b011..R0/3
20107 * 0b100..R0/4
20108 * 0b101..R0/5
20109 * 0b110..R0/6
20110 * 0b111..R0/7
20111 */
20112#define IOMUXC_SW_PAD_CTL_PAD_1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK)
20113#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK (0xC0U)
20114#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT (6U)
20115/* SPEED - Speed Field
20116 * 0b00..low(50MHz)
20117 * 0b01..medium(100MHz)
20118 * 0b10..medium(100MHz)
20119 * 0b11..max(200MHz)
20120 */
20121#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK)
20122#define IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK (0x800U)
20123#define IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT (11U)
20124/* ODE - Open Drain Enable Field
20125 * 0b0..Open Drain Disabled
20126 * 0b1..Open Drain Enabled
20127 */
20128#define IOMUXC_SW_PAD_CTL_PAD_1_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK)
20129#define IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK (0x1000U)
20130#define IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT (12U)
20131/* PKE - Pull / Keep Enable Field
20132 * 0b0..Pull/Keeper Disabled
20133 * 0b1..Pull/Keeper Enabled
20134 */
20135#define IOMUXC_SW_PAD_CTL_PAD_1_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK)
20136#define IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK (0x2000U)
20137#define IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT (13U)
20138/* PUE - Pull / Keep Select Field
20139 * 0b0..Keeper
20140 * 0b1..Pull
20141 */
20142#define IOMUXC_SW_PAD_CTL_PAD_1_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK)
20143#define IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK (0xC000U)
20144#define IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT (14U)
20145/* PUS - Pull Up / Down Config. Field
20146 * 0b00..100K Ohm Pull Down
20147 * 0b01..47K Ohm Pull Up
20148 * 0b10..100K Ohm Pull Up
20149 * 0b11..22K Ohm Pull Up
20150 */
20151#define IOMUXC_SW_PAD_CTL_PAD_1_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK)
20152#define IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK (0x10000U)
20153#define IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT (16U)
20154/* HYS - Hyst. Enable Field
20155 * 0b0..Hysteresis Disabled
20156 * 0b1..Hysteresis Enabled
20157 */
20158#define IOMUXC_SW_PAD_CTL_PAD_1_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK)
20159/* @} */
20160
20161/* The count of IOMUXC_SW_PAD_CTL_PAD_1 */
20162#define IOMUXC_SW_PAD_CTL_PAD_1_COUNT (22U)
20163
20164/* @name SELECT_INPUT_1 - ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register..CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register */
20165/* @{ */
20166#define IOMUXC_SELECT_INPUT_1_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
20167#define IOMUXC_SELECT_INPUT_1_DAISY_SHIFT (0U)
20168/* DAISY - Selecting Pads Involved in Daisy Chain.
20169 * 0b00..Selecting Pad: GPIO_EMC_33 for Mode: ALT9
20170 * 0b01..Selecting Pad: GPIO_SD_B0_01 for Mode: ALT9
20171 * 0b10..Selecting Pad: GPIO_B0_15 for Mode: ALT9
20172 */
20173#define IOMUXC_SELECT_INPUT_1_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_1_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_1_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
20174/* @} */
20175
20176/* The count of IOMUXC_SELECT_INPUT_1 */
20177#define IOMUXC_SELECT_INPUT_1_COUNT (33U)
20178
20179
20180/*
20181 * @}
20182 */ /* end of group IOMUXC_Register_Masks */
20183
20184
20185/* IOMUXC - Peripheral instance base addresses */
20186/* Peripheral IOMUXC base address */
20187#define IOMUXC_BASE (0x401F8000u)
20188/* Peripheral IOMUXC base pointer */
20189#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
20190/* Array initializer of IOMUXC peripheral base addresses */
20191#define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
20192/* Array initializer of IOMUXC peripheral base pointers */
20193#define IOMUXC_BASE_PTRS { IOMUXC }
20194
20195/*
20196 * @}
20197 */ /* end of group IOMUXC_Peripheral_Access_Layer */
20198
20199
20200/* ----------------------------------------------------------------------------
20201 -- IOMUXC_GPR Peripheral Access Layer
20202 ---------------------------------------------------------------------------- */
20203
20204/*
20205 * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
20206 * @{
20207 */
20208
20209/* IOMUXC_GPR - Register Layout Typedef */
20210typedef union {
20211struct {
20212 uint32_t GPR0;
20213 __IO uint32_t GPR1;
20214 __IO uint32_t GPR2;
20215 __IO uint32_t GPR3;
20216 __IO uint32_t GPR4;
20217 __IO uint32_t GPR5;
20218 __IO uint32_t GPR6;
20219 __IO uint32_t GPR7;
20220 __IO uint32_t GPR8;
20221 uint32_t GPR9;
20222 __IO uint32_t GPR10;
20223 __IO uint32_t GPR11;
20224 __IO uint32_t GPR12;
20225 __IO uint32_t GPR13;
20226 __IO uint32_t GPR14;
20227 uint32_t GPR15;
20228 __IO uint32_t GPR16;
20229 __IO uint32_t GPR17;
20230 __IO uint32_t GPR18;
20231 __IO uint32_t GPR19;
20232 __IO uint32_t GPR20;
20233 __IO uint32_t GPR21;
20234 __IO uint32_t GPR22;
20235 __IO uint32_t GPR23;
20236 __IO uint32_t GPR24;
20237 __IO uint32_t GPR25;
20238 __IO uint32_t GPR26;
20239 __IO uint32_t GPR27;
20240 __IO uint32_t GPR28;
20241 __IO uint32_t GPR29;
20242 __IO uint32_t GPR30;
20243 __IO uint32_t GPR31;
20244 __IO uint32_t GPR32;
20245 __IO uint32_t GPR33;
20246 __IO uint32_t GPR34;
20247};
20248 __IO uint32_t GPR[35];
20249} IOMUXC_GPR_Type;
20250
20251/* ----------------------------------------------------------------------------
20252 -- IOMUXC_GPR Register Masks
20253 ---------------------------------------------------------------------------- */
20254
20255/*
20256 * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
20257 * @{
20258 */
20259
20260/* @name GPR1 - GPR1 General Purpose Register */
20261/* @{ */
20262#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U)
20263#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U)
20264/* SAI1_MCLK1_SEL
20265 * 0b000..ccm.ssi1_clk_root
20266 * 0b001..ccm.ssi2_clk_root
20267 * 0b010..ccm.ssi3_clk_root
20268 * 0b011..iomux.sai1_ipg_clk_sai_mclk
20269 * 0b100..iomux.sai2_ipg_clk_sai_mclk
20270 * 0b101..iomux.sai3_ipg_clk_sai_mclk
20271 * 0b110..Reserved
20272 * 0b111..Reserved
20273 */
20274#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK)
20275#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U)
20276#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U)
20277/* SAI1_MCLK2_SEL
20278 * 0b000..ccm.ssi1_clk_root
20279 * 0b001..ccm.ssi2_clk_root
20280 * 0b010..ccm.ssi3_clk_root
20281 * 0b011..iomux.sai1_ipg_clk_sai_mclk
20282 * 0b100..iomux.sai2_ipg_clk_sai_mclk
20283 * 0b101..iomux.sai3_ipg_clk_sai_mclk
20284 * 0b110..Reserved
20285 * 0b111..Reserved
20286 */
20287#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK)
20288#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U)
20289#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U)
20290/* SAI1_MCLK3_SEL
20291 * 0b00..ccm.spdif0_clk_root
20292 * 0b01..iomux.spdif_tx_clk2
20293 * 0b10..spdif.spdif_srclk
20294 * 0b11..spdif.spdif_outclock
20295 */
20296#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK)
20297#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U)
20298#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U)
20299/* SAI2_MCLK3_SEL
20300 * 0b00..ccm.spdif0_clk_root
20301 * 0b01..iomux.spdif_tx_clk2
20302 * 0b10..spdif.spdif_srclk
20303 * 0b11..spdif.spdif_outclock
20304 */
20305#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
20306#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U)
20307#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U)
20308/* SAI3_MCLK3_SEL
20309 * 0b00..ccm.spdif0_clk_root
20310 * 0b01..iomux.spdif_tx_clk2
20311 * 0b10..spdif.spdif_srclk
20312 * 0b11..spdif.spdif_outclock
20313 */
20314#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK)
20315#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U)
20316#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U)
20317/* GINT
20318 * 0b0..Global interrupt request is not asserted.
20319 * 0b1..Global interrupt request is asserted.
20320 */
20321#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK)
20322#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U)
20323#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U)
20324/* ENET1_CLK_SEL
20325 * 0b0..ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function.
20326 * 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the
20327 * clock for both the external PHY and the internal controller.
20328 */
20329#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK)
20330#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U)
20331#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U)
20332/* ENET2_CLK_SEL
20333 * 0b0..ENET2 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET2_REF_CLK function.
20334 * 0b1..Gets ENET2 TX reference clock from the ENET2_TX_CLK pin. In this use case, an external OSC provides the
20335 * clock for both the external PHY and the internal controller.
20336 */
20337#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK)
20338#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U)
20339#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U)
20340/* USB_EXP_MODE
20341 * 0b0..Exposure mode is disabled.
20342 * 0b1..Exposure mode is enabled.
20343 */
20344#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK)
20345#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U)
20346#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U)
20347/* ENET1_TX_CLK_DIR
20348 * 0b0..ENET1_TX_CLK output driver is disabled
20349 * 0b1..ENET1_TX_CLK output driver is enabled
20350 */
20351#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
20352#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U)
20353#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U)
20354/* ENET2_TX_CLK_DIR
20355 * 0b0..ENET2_TX_CLK output driver is disabled
20356 * 0b1..ENET2_TX_CLK output driver is enabled
20357 */
20358#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK)
20359#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U)
20360#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U)
20361/* SAI1_MCLK_DIR
20362 * 0b0..sai1.MCLK is input signal
20363 * 0b1..sai1.MCLK is output signal
20364 */
20365#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK)
20366#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U)
20367#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U)
20368/* SAI2_MCLK_DIR
20369 * 0b0..sai2.MCLK is input signal
20370 * 0b1..sai2.MCLK is output signal
20371 */
20372#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
20373#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U)
20374#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U)
20375/* SAI3_MCLK_DIR
20376 * 0b0..sai3.MCLK is input signal
20377 * 0b1..sai3.MCLK is output signal
20378 */
20379#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK)
20380#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U)
20381#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U)
20382/* EXC_MON
20383 * 0b0..OKAY response
20384 * 0b1..SLVError response (default)
20385 */
20386#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK)
20387#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U)
20388#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U)
20389/* ENET_IPG_CLK_S_EN
20390 * 0b0..ipg_clk_s is gated when there is no IPS access
20391 * 0b1..ipg_clk_s is always on
20392 */
20393#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK)
20394#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U)
20395#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U)
20396/* CM7_FORCE_HCLK_EN
20397 * 0b0..AHB clock is not running (gated)
20398 * 0b1..AHB clock is running (enabled)
20399 */
20400#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK)
20401/* @} */
20402
20403/* @name GPR2 - GPR2 General Purpose Register */
20404/* @{ */
20405#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK (0x1U)
20406#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT (0U)
20407/* AXBS_L_AHBXL_HIGH_PRIORITY
20408 * 0b0..AXBS_L AHBXL master does not have high priority
20409 * 0b1..AXBS_P AHBXL master has high priority
20410 */
20411#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK)
20412#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK (0x2U)
20413#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT (1U)
20414/* AXBS_L_DMA_HIGH_PRIORITY
20415 * 0b0..AXBS_L DMA master does not have high priority
20416 * 0b1..AXBS_L DMA master has high priority
20417 */
20418#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK)
20419#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK (0x4U)
20420#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT (2U)
20421/* AXBS_L_FORCE_ROUND_ROBIN
20422 * 0b0..AXBS_L masters are not arbitored in round robin, depending on DMA and AHBXL master priority settings.
20423 * 0b1..AXBS_L masters are arbitored in round robin
20424 */
20425#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK)
20426#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK (0x8U)
20427#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT (3U)
20428/* AXBS_P_M0_HIGH_PRIORITY
20429 * 0b0..AXBS_P M0 master doesn't have high priority
20430 * 0b1..AXBS_P M0 master has high priority
20431 */
20432#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK)
20433#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK (0x10U)
20434#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT (4U)
20435/* AXBS_P_M1_HIGH_PRIORITY
20436 * 0b0..AXBS_P M1 master does not have high priority
20437 * 0b1..AXBS_P M1 master has high priority
20438 */
20439#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK)
20440#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK (0x20U)
20441#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT (5U)
20442/* AXBS_P_FORCE_ROUND_ROBIN
20443 * 0b0..AXBS_P masters are not arbitored in round robin, depending on M0/M1 master priority settings.
20444 * 0b1..AXBS_P masters are arbitored in round robin
20445 */
20446#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK)
20447#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK (0x40U)
20448#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT (6U)
20449/* CANFD_FILTER_BYPASS
20450 * 0b0..enable CANFD filter
20451 * 0b1..disable CANFD filter
20452 */
20453#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK)
20454#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U)
20455#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U)
20456/* L2_MEM_EN_POWERSAVING
20457 * 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect
20458 * 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP (priority high to low) to enable power saving levels
20459 */
20460#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK)
20461#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U)
20462#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U)
20463/* RAM_AUTO_CLK_GATING_EN
20464 * 0b0..disable automatically gate off RAM clock
20465 * 0b1..enable automatically gate off RAM clock
20466 */
20467#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK)
20468#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U)
20469#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U)
20470/* L2_MEM_DEEPSLEEP
20471 * 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode
20472 * 0b1..force memory into deep sleep mode
20473 */
20474#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK)
20475#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U)
20476#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U)
20477/* MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency.
20478 * 0b00000000..mclk frequency = 1/1 * hmclk frequency
20479 * 0b00000001..mclk frequency = 1/2 * hmclk frequency
20480 * 0b00000010..mclk frequency = 1/3 * hmclk frequency
20481 * 0b00000011..mclk frequency = 1/4 * hmclk frequency
20482 * 0b00000100..mclk frequency = 1/5 * hmclk frequency
20483 * 0b00000101..mclk frequency = 1/6 * hmclk frequency
20484 * 0b00000110..mclk frequency = 1/7 * hmclk frequency
20485 * 0b00000111..mclk frequency = 1/8 * hmclk frequency
20486 * 0b00001000..mclk frequency = 1/9 * hmclk frequency
20487 * 0b00001001..mclk frequency = 1/10 * hmclk frequency
20488 * 0b00001010..mclk frequency = 1/11 * hmclk frequency
20489 * 0b00001011..mclk frequency = 1/12 * hmclk frequency
20490 * 0b00001100..mclk frequency = 1/13 * hmclk frequency
20491 * 0b00001101..mclk frequency = 1/14 * hmclk frequency
20492 * 0b00001110..mclk frequency = 1/15 * hmclk frequency
20493 * 0b00001111..mclk frequency = 1/16 * hmclk frequency
20494 * 0b00010000..mclk frequency = 1/17 * hmclk frequency
20495 * 0b00010001..mclk frequency = 1/18 * hmclk frequency
20496 * 0b00010010..mclk frequency = 1/19 * hmclk frequency
20497 * 0b00010011..mclk frequency = 1/20 * hmclk frequency
20498 * 0b00010100..mclk frequency = 1/21 * hmclk frequency
20499 * 0b00010101..mclk frequency = 1/22 * hmclk frequency
20500 * 0b00010110..mclk frequency = 1/23 * hmclk frequency
20501 * 0b00010111..mclk frequency = 1/24 * hmclk frequency
20502 * 0b00011000..mclk frequency = 1/25 * hmclk frequency
20503 * 0b00011001..mclk frequency = 1/26 * hmclk frequency
20504 * 0b00011010..mclk frequency = 1/27 * hmclk frequency
20505 * 0b00011011..mclk frequency = 1/28 * hmclk frequency
20506 * 0b00011100..mclk frequency = 1/29 * hmclk frequency
20507 * 0b00011101..mclk frequency = 1/30 * hmclk frequency
20508 * 0b00011110..mclk frequency = 1/31 * hmclk frequency
20509 * 0b00011111..mclk frequency = 1/32 * hmclk frequency
20510 * 0b00100000..mclk frequency = 1/33 * hmclk frequency
20511 * 0b00100001..mclk frequency = 1/34 * hmclk frequency
20512 * 0b00100010..mclk frequency = 1/35 * hmclk frequency
20513 * 0b00100011..mclk frequency = 1/36 * hmclk frequency
20514 * 0b00100100..mclk frequency = 1/37 * hmclk frequency
20515 * 0b00100101..mclk frequency = 1/38 * hmclk frequency
20516 * 0b00100110..mclk frequency = 1/39 * hmclk frequency
20517 * 0b00100111..mclk frequency = 1/40 * hmclk frequency
20518 * 0b00101000..mclk frequency = 1/41 * hmclk frequency
20519 * 0b00101001..mclk frequency = 1/42 * hmclk frequency
20520 * 0b00101010..mclk frequency = 1/43 * hmclk frequency
20521 * 0b00101011..mclk frequency = 1/44 * hmclk frequency
20522 * 0b00101100..mclk frequency = 1/45 * hmclk frequency
20523 * 0b00101101..mclk frequency = 1/46 * hmclk frequency
20524 * 0b00101110..mclk frequency = 1/47 * hmclk frequency
20525 * 0b00101111..mclk frequency = 1/48 * hmclk frequency
20526 * 0b00110000..mclk frequency = 1/49 * hmclk frequency
20527 * 0b00110001..mclk frequency = 1/50 * hmclk frequency
20528 * 0b00110010..mclk frequency = 1/51 * hmclk frequency
20529 * 0b00110011..mclk frequency = 1/52 * hmclk frequency
20530 * 0b00110100..mclk frequency = 1/53 * hmclk frequency
20531 * 0b00110101..mclk frequency = 1/54 * hmclk frequency
20532 * 0b00110110..mclk frequency = 1/55 * hmclk frequency
20533 * 0b00110111..mclk frequency = 1/56 * hmclk frequency
20534 * 0b00111000..mclk frequency = 1/57 * hmclk frequency
20535 * 0b00111001..mclk frequency = 1/58 * hmclk frequency
20536 * 0b00111010..mclk frequency = 1/59 * hmclk frequency
20537 * 0b00111011..mclk frequency = 1/60 * hmclk frequency
20538 * 0b00111100..mclk frequency = 1/61 * hmclk frequency
20539 * 0b00111101..mclk frequency = 1/62 * hmclk frequency
20540 * 0b00111110..mclk frequency = 1/63 * hmclk frequency
20541 * 0b00111111..mclk frequency = 1/64 * hmclk frequency
20542 * 0b01000000..mclk frequency = 1/65 * hmclk frequency
20543 * 0b01000001..mclk frequency = 1/66 * hmclk frequency
20544 * 0b01000010..mclk frequency = 1/67 * hmclk frequency
20545 * 0b01000011..mclk frequency = 1/68 * hmclk frequency
20546 * 0b01000100..mclk frequency = 1/69 * hmclk frequency
20547 * 0b01000101..mclk frequency = 1/70 * hmclk frequency
20548 * 0b01000110..mclk frequency = 1/71 * hmclk frequency
20549 * 0b01000111..mclk frequency = 1/72 * hmclk frequency
20550 * 0b01001000..mclk frequency = 1/73 * hmclk frequency
20551 * 0b01001001..mclk frequency = 1/74 * hmclk frequency
20552 * 0b01001010..mclk frequency = 1/75 * hmclk frequency
20553 * 0b01001011..mclk frequency = 1/76 * hmclk frequency
20554 * 0b01001100..mclk frequency = 1/77 * hmclk frequency
20555 * 0b01001101..mclk frequency = 1/78 * hmclk frequency
20556 * 0b01001110..mclk frequency = 1/79 * hmclk frequency
20557 * 0b01001111..mclk frequency = 1/80 * hmclk frequency
20558 * 0b01010000..mclk frequency = 1/81 * hmclk frequency
20559 * 0b01010001..mclk frequency = 1/82 * hmclk frequency
20560 * 0b01010010..mclk frequency = 1/83 * hmclk frequency
20561 * 0b01010011..mclk frequency = 1/84 * hmclk frequency
20562 * 0b01010100..mclk frequency = 1/85 * hmclk frequency
20563 * 0b01010101..mclk frequency = 1/86 * hmclk frequency
20564 * 0b01010110..mclk frequency = 1/87 * hmclk frequency
20565 * 0b01010111..mclk frequency = 1/88 * hmclk frequency
20566 * 0b01011000..mclk frequency = 1/89 * hmclk frequency
20567 * 0b01011001..mclk frequency = 1/90 * hmclk frequency
20568 * 0b01011010..mclk frequency = 1/91 * hmclk frequency
20569 * 0b01011011..mclk frequency = 1/92 * hmclk frequency
20570 * 0b01011100..mclk frequency = 1/93 * hmclk frequency
20571 * 0b01011101..mclk frequency = 1/94 * hmclk frequency
20572 * 0b01011110..mclk frequency = 1/95 * hmclk frequency
20573 * 0b01011111..mclk frequency = 1/96 * hmclk frequency
20574 * 0b01100000..mclk frequency = 1/97 * hmclk frequency
20575 * 0b01100001..mclk frequency = 1/98 * hmclk frequency
20576 * 0b01100010..mclk frequency = 1/99 * hmclk frequency
20577 * 0b01100011..mclk frequency = 1/100 * hmclk frequency
20578 * 0b01100100..mclk frequency = 1/101 * hmclk frequency
20579 * 0b01100101..mclk frequency = 1/102 * hmclk frequency
20580 * 0b01100110..mclk frequency = 1/103 * hmclk frequency
20581 * 0b01100111..mclk frequency = 1/104 * hmclk frequency
20582 * 0b01101000..mclk frequency = 1/105 * hmclk frequency
20583 * 0b01101001..mclk frequency = 1/106 * hmclk frequency
20584 * 0b01101010..mclk frequency = 1/107 * hmclk frequency
20585 * 0b01101011..mclk frequency = 1/108 * hmclk frequency
20586 * 0b01101100..mclk frequency = 1/109 * hmclk frequency
20587 * 0b01101101..mclk frequency = 1/110 * hmclk frequency
20588 * 0b01101110..mclk frequency = 1/111 * hmclk frequency
20589 * 0b01101111..mclk frequency = 1/112 * hmclk frequency
20590 * 0b01110000..mclk frequency = 1/113 * hmclk frequency
20591 * 0b01110001..mclk frequency = 1/114 * hmclk frequency
20592 * 0b01110010..mclk frequency = 1/115 * hmclk frequency
20593 * 0b01110011..mclk frequency = 1/116 * hmclk frequency
20594 * 0b01110100..mclk frequency = 1/117 * hmclk frequency
20595 * 0b01110101..mclk frequency = 1/118 * hmclk frequency
20596 * 0b01110110..mclk frequency = 1/119 * hmclk frequency
20597 * 0b01110111..mclk frequency = 1/120 * hmclk frequency
20598 * 0b01111000..mclk frequency = 1/121 * hmclk frequency
20599 * 0b01111001..mclk frequency = 1/122 * hmclk frequency
20600 * 0b01111010..mclk frequency = 1/123 * hmclk frequency
20601 * 0b01111011..mclk frequency = 1/124 * hmclk frequency
20602 * 0b01111100..mclk frequency = 1/125 * hmclk frequency
20603 * 0b01111101..mclk frequency = 1/126 * hmclk frequency
20604 * 0b01111110..mclk frequency = 1/127 * hmclk frequency
20605 * 0b01111111..mclk frequency = 1/128 * hmclk frequency
20606 * 0b10000000..mclk frequency = 1/129 * hmclk frequency
20607 * 0b10000001..mclk frequency = 1/130 * hmclk frequency
20608 * 0b10000010..mclk frequency = 1/131 * hmclk frequency
20609 * 0b10000011..mclk frequency = 1/132 * hmclk frequency
20610 * 0b10000100..mclk frequency = 1/133 * hmclk frequency
20611 * 0b10000101..mclk frequency = 1/134 * hmclk frequency
20612 * 0b10000110..mclk frequency = 1/135 * hmclk frequency
20613 * 0b10000111..mclk frequency = 1/136 * hmclk frequency
20614 * 0b10001000..mclk frequency = 1/137 * hmclk frequency
20615 * 0b10001001..mclk frequency = 1/138 * hmclk frequency
20616 * 0b10001010..mclk frequency = 1/139 * hmclk frequency
20617 * 0b10001011..mclk frequency = 1/140 * hmclk frequency
20618 * 0b10001100..mclk frequency = 1/141 * hmclk frequency
20619 * 0b10001101..mclk frequency = 1/142 * hmclk frequency
20620 * 0b10001110..mclk frequency = 1/143 * hmclk frequency
20621 * 0b10001111..mclk frequency = 1/144 * hmclk frequency
20622 * 0b10010000..mclk frequency = 1/145 * hmclk frequency
20623 * 0b10010001..mclk frequency = 1/146 * hmclk frequency
20624 * 0b10010010..mclk frequency = 1/147 * hmclk frequency
20625 * 0b10010011..mclk frequency = 1/148 * hmclk frequency
20626 * 0b10010100..mclk frequency = 1/149 * hmclk frequency
20627 * 0b10010101..mclk frequency = 1/150 * hmclk frequency
20628 * 0b10010110..mclk frequency = 1/151 * hmclk frequency
20629 * 0b10010111..mclk frequency = 1/152 * hmclk frequency
20630 * 0b10011000..mclk frequency = 1/153 * hmclk frequency
20631 * 0b10011001..mclk frequency = 1/154 * hmclk frequency
20632 * 0b10011010..mclk frequency = 1/155 * hmclk frequency
20633 * 0b10011011..mclk frequency = 1/156 * hmclk frequency
20634 * 0b10011100..mclk frequency = 1/157 * hmclk frequency
20635 * 0b10011101..mclk frequency = 1/158 * hmclk frequency
20636 * 0b10011110..mclk frequency = 1/159 * hmclk frequency
20637 * 0b10011111..mclk frequency = 1/160 * hmclk frequency
20638 * 0b10100000..mclk frequency = 1/161 * hmclk frequency
20639 * 0b10100001..mclk frequency = 1/162 * hmclk frequency
20640 * 0b10100010..mclk frequency = 1/163 * hmclk frequency
20641 * 0b10100011..mclk frequency = 1/164 * hmclk frequency
20642 * 0b10100100..mclk frequency = 1/165 * hmclk frequency
20643 * 0b10100101..mclk frequency = 1/166 * hmclk frequency
20644 * 0b10100110..mclk frequency = 1/167 * hmclk frequency
20645 * 0b10100111..mclk frequency = 1/168 * hmclk frequency
20646 * 0b10101000..mclk frequency = 1/169 * hmclk frequency
20647 * 0b10101001..mclk frequency = 1/170 * hmclk frequency
20648 * 0b10101010..mclk frequency = 1/171 * hmclk frequency
20649 * 0b10101011..mclk frequency = 1/172 * hmclk frequency
20650 * 0b10101100..mclk frequency = 1/173 * hmclk frequency
20651 * 0b10101101..mclk frequency = 1/174 * hmclk frequency
20652 * 0b10101110..mclk frequency = 1/175 * hmclk frequency
20653 * 0b10101111..mclk frequency = 1/176 * hmclk frequency
20654 * 0b10110000..mclk frequency = 1/177 * hmclk frequency
20655 * 0b10110001..mclk frequency = 1/178 * hmclk frequency
20656 * 0b10110010..mclk frequency = 1/179 * hmclk frequency
20657 * 0b10110011..mclk frequency = 1/180 * hmclk frequency
20658 * 0b10110100..mclk frequency = 1/181 * hmclk frequency
20659 * 0b10110101..mclk frequency = 1/182 * hmclk frequency
20660 * 0b10110110..mclk frequency = 1/183 * hmclk frequency
20661 * 0b10110111..mclk frequency = 1/184 * hmclk frequency
20662 * 0b10111000..mclk frequency = 1/185 * hmclk frequency
20663 * 0b10111001..mclk frequency = 1/186 * hmclk frequency
20664 * 0b10111010..mclk frequency = 1/187 * hmclk frequency
20665 * 0b10111011..mclk frequency = 1/188 * hmclk frequency
20666 * 0b10111100..mclk frequency = 1/189 * hmclk frequency
20667 * 0b10111101..mclk frequency = 1/190 * hmclk frequency
20668 * 0b10111110..mclk frequency = 1/191 * hmclk frequency
20669 * 0b10111111..mclk frequency = 1/192 * hmclk frequency
20670 * 0b11000000..mclk frequency = 1/193 * hmclk frequency
20671 * 0b11000001..mclk frequency = 1/194 * hmclk frequency
20672 * 0b11000010..mclk frequency = 1/195 * hmclk frequency
20673 * 0b11000011..mclk frequency = 1/196 * hmclk frequency
20674 * 0b11000100..mclk frequency = 1/197 * hmclk frequency
20675 * 0b11000101..mclk frequency = 1/198 * hmclk frequency
20676 * 0b11000110..mclk frequency = 1/199 * hmclk frequency
20677 * 0b11000111..mclk frequency = 1/200 * hmclk frequency
20678 * 0b11001000..mclk frequency = 1/201 * hmclk frequency
20679 * 0b11001001..mclk frequency = 1/202 * hmclk frequency
20680 * 0b11001010..mclk frequency = 1/203 * hmclk frequency
20681 * 0b11001011..mclk frequency = 1/204 * hmclk frequency
20682 * 0b11001100..mclk frequency = 1/205 * hmclk frequency
20683 * 0b11001101..mclk frequency = 1/206 * hmclk frequency
20684 * 0b11001110..mclk frequency = 1/207 * hmclk frequency
20685 * 0b11001111..mclk frequency = 1/208 * hmclk frequency
20686 * 0b11010000..mclk frequency = 1/209 * hmclk frequency
20687 * 0b11010001..mclk frequency = 1/210 * hmclk frequency
20688 * 0b11010010..mclk frequency = 1/211 * hmclk frequency
20689 * 0b11010011..mclk frequency = 1/212 * hmclk frequency
20690 * 0b11010100..mclk frequency = 1/213 * hmclk frequency
20691 * 0b11010101..mclk frequency = 1/214 * hmclk frequency
20692 * 0b11010110..mclk frequency = 1/215 * hmclk frequency
20693 * 0b11010111..mclk frequency = 1/216 * hmclk frequency
20694 * 0b11011000..mclk frequency = 1/217 * hmclk frequency
20695 * 0b11011001..mclk frequency = 1/218 * hmclk frequency
20696 * 0b11011010..mclk frequency = 1/219 * hmclk frequency
20697 * 0b11011011..mclk frequency = 1/220 * hmclk frequency
20698 * 0b11011100..mclk frequency = 1/221 * hmclk frequency
20699 * 0b11011101..mclk frequency = 1/222 * hmclk frequency
20700 * 0b11011110..mclk frequency = 1/223 * hmclk frequency
20701 * 0b11011111..mclk frequency = 1/224 * hmclk frequency
20702 * 0b11100000..mclk frequency = 1/225 * hmclk frequency
20703 * 0b11100001..mclk frequency = 1/226 * hmclk frequency
20704 * 0b11100010..mclk frequency = 1/227 * hmclk frequency
20705 * 0b11100011..mclk frequency = 1/228 * hmclk frequency
20706 * 0b11100100..mclk frequency = 1/229 * hmclk frequency
20707 * 0b11100101..mclk frequency = 1/230 * hmclk frequency
20708 * 0b11100110..mclk frequency = 1/231 * hmclk frequency
20709 * 0b11100111..mclk frequency = 1/232 * hmclk frequency
20710 * 0b11101000..mclk frequency = 1/233 * hmclk frequency
20711 * 0b11101001..mclk frequency = 1/234 * hmclk frequency
20712 * 0b11101010..mclk frequency = 1/235 * hmclk frequency
20713 * 0b11101011..mclk frequency = 1/236 * hmclk frequency
20714 * 0b11101100..mclk frequency = 1/237 * hmclk frequency
20715 * 0b11101101..mclk frequency = 1/238 * hmclk frequency
20716 * 0b11101110..mclk frequency = 1/239 * hmclk frequency
20717 * 0b11101111..mclk frequency = 1/240 * hmclk frequency
20718 * 0b11110000..mclk frequency = 1/241 * hmclk frequency
20719 * 0b11110001..mclk frequency = 1/242 * hmclk frequency
20720 * 0b11110010..mclk frequency = 1/243 * hmclk frequency
20721 * 0b11110011..mclk frequency = 1/244 * hmclk frequency
20722 * 0b11110100..mclk frequency = 1/245 * hmclk frequency
20723 * 0b11110101..mclk frequency = 1/246 * hmclk frequency
20724 * 0b11110110..mclk frequency = 1/247 * hmclk frequency
20725 * 0b11110111..mclk frequency = 1/248 * hmclk frequency
20726 * 0b11111000..mclk frequency = 1/249 * hmclk frequency
20727 * 0b11111001..mclk frequency = 1/250 * hmclk frequency
20728 * 0b11111010..mclk frequency = 1/251 * hmclk frequency
20729 * 0b11111011..mclk frequency = 1/252 * hmclk frequency
20730 * 0b11111100..mclk frequency = 1/253 * hmclk frequency
20731 * 0b11111101..mclk frequency = 1/254 * hmclk frequency
20732 * 0b11111110..mclk frequency = 1/255 * hmclk frequency
20733 * 0b11111111..mclk frequency = 1/256 * hmclk frequency
20734 */
20735#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK)
20736#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U)
20737#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U)
20738/* MQS_SW_RST
20739 * 0b0..Exit software reset for MQS
20740 * 0b1..Enable software reset for MQS
20741 */
20742#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK)
20743#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U)
20744#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U)
20745/* MQS_EN
20746 * 0b0..Disable MQS
20747 * 0b1..Enable MQS
20748 */
20749#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK)
20750#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U)
20751#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U)
20752/* MQS_OVERSAMPLE
20753 * 0b0..32
20754 * 0b1..64
20755 */
20756#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK)
20757#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U)
20758#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U)
20759/* QTIMER1_TMR_CNTS_FREEZE
20760 * 0b0..timer counter work normally
20761 * 0b1..reset counter and ouput flags
20762 */
20763#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK)
20764#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U)
20765#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U)
20766/* QTIMER2_TMR_CNTS_FREEZE
20767 * 0b0..timer counter work normally
20768 * 0b1..reset counter and ouput flags
20769 */
20770#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK)
20771#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U)
20772#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U)
20773/* QTIMER3_TMR_CNTS_FREEZE
20774 * 0b0..timer counter work normally
20775 * 0b1..reset counter and ouput flags
20776 */
20777#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK)
20778#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U)
20779#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U)
20780/* QTIMER4_TMR_CNTS_FREEZE
20781 * 0b0..timer counter work normally
20782 * 0b1..reset counter and ouput flags
20783 */
20784#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK)
20785/* @} */
20786
20787/* @name GPR3 - GPR3 General Purpose Register */
20788/* @{ */
20789#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU)
20790#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U)
20791#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK)
20792#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U)
20793#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U)
20794/* DCP_KEY_SEL
20795 * 0b0..Select [127:0] from snvs/ocotp key as dcp key
20796 * 0b1..Select [255:128] from snvs/ocotp key as dcp key
20797 */
20798#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK)
20799#define IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK (0xF00U)
20800#define IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT (8U)
20801#define IOMUXC_GPR_GPR3_OCRAM2_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK)
20802#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK (0x8000U)
20803#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT (15U)
20804/* AXBS_L_HALT_REQ
20805 * 0b0..axbs_l normal run
20806 * 0b1..request to halt axbs_l
20807 */
20808#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK)
20809#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U)
20810#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U)
20811#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK)
20812#define IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK (0xF000000U)
20813#define IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT (24U)
20814#define IOMUXC_GPR_GPR3_OCRAM2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK)
20815#define IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK (0x80000000U)
20816#define IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT (31U)
20817/* AXBS_L_HALTED
20818 * 0b0..axbs_l is not halted
20819 * 0b1..axbs_l is in halted status
20820 */
20821#define IOMUXC_GPR_GPR3_AXBS_L_HALTED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK)
20822/* @} */
20823
20824/* @name GPR4 - GPR4 General Purpose Register */
20825/* @{ */
20826#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U)
20827#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U)
20828/* EDMA_STOP_REQ
20829 * 0b0..stop request off
20830 * 0b1..stop request on
20831 */
20832#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK)
20833#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U)
20834#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U)
20835/* CAN1_STOP_REQ
20836 * 0b0..stop request off
20837 * 0b1..stop request on
20838 */
20839#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK)
20840#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U)
20841#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U)
20842/* CAN2_STOP_REQ
20843 * 0b0..stop request off
20844 * 0b1..stop request on
20845 */
20846#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK)
20847#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U)
20848#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U)
20849/* TRNG_STOP_REQ
20850 * 0b0..stop request off
20851 * 0b1..stop request on
20852 */
20853#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK)
20854#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U)
20855#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U)
20856/* ENET_STOP_REQ
20857 * 0b0..stop request off
20858 * 0b1..stop request on
20859 */
20860#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK)
20861#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U)
20862#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U)
20863/* SAI1_STOP_REQ
20864 * 0b0..stop request off
20865 * 0b1..stop request on
20866 */
20867#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK)
20868#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U)
20869#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U)
20870/* SAI2_STOP_REQ
20871 * 0b0..stop request off
20872 * 0b1..stop request on
20873 */
20874#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK)
20875#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U)
20876#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U)
20877/* SAI3_STOP_REQ
20878 * 0b0..stop request off
20879 * 0b1..stop request on
20880 */
20881#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK)
20882#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x100U)
20883#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (8U)
20884/* ENET2_STOP_REQ
20885 * 0b0..stop request off
20886 * 0b1..stop request on
20887 */
20888#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK)
20889#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U)
20890#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U)
20891/* SEMC_STOP_REQ
20892 * 0b0..stop request off
20893 * 0b1..stop request on
20894 */
20895#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK)
20896#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U)
20897#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U)
20898/* PIT_STOP_REQ
20899 * 0b0..stop request off
20900 * 0b1..stop request on
20901 */
20902#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK)
20903#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U)
20904#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U)
20905/* FLEXSPI_STOP_REQ
20906 * 0b0..stop request off
20907 * 0b1..stop request on
20908 */
20909#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK)
20910#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U)
20911#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U)
20912/* FLEXIO1_STOP_REQ
20913 * 0b0..stop request off
20914 * 0b1..stop request on
20915 */
20916#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK)
20917#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U)
20918#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U)
20919/* FLEXIO2_STOP_REQ
20920 * 0b0..stop request off
20921 * 0b1..stop request on
20922 */
20923#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
20924#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK (0x4000U)
20925#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT (14U)
20926/* FLEXIO3_STOP_REQ
20927 * 0b0..stop request off
20928 * 0b1..stop request on
20929 */
20930#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK)
20931#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK (0x8000U)
20932#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT (15U)
20933/* FLEXSPI2_STOP_REQ
20934 * 0b0..stop request off
20935 * 0b1..stop request on
20936 */
20937#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK)
20938#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U)
20939#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U)
20940/* EDMA_STOP_ACK
20941 * 0b0..EDMA stop acknowledge is not asserted
20942 * 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode).
20943 */
20944#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK)
20945#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U)
20946#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U)
20947/* CAN1_STOP_ACK
20948 * 0b0..CAN1 stop acknowledge is not asserted
20949 * 0b1..CAN1 stop acknowledge is asserted
20950 */
20951#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK)
20952#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U)
20953#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U)
20954/* CAN2_STOP_ACK
20955 * 0b0..CAN2 stop acknowledge is not asserted
20956 * 0b1..CAN2 stop acknowledge is asserted
20957 */
20958#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK)
20959#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U)
20960#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U)
20961/* TRNG_STOP_ACK
20962 * 0b0..TRNG stop acknowledge is not asserted
20963 * 0b1..TRNG stop acknowledge is asserted
20964 */
20965#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK)
20966#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U)
20967#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U)
20968/* ENET_STOP_ACK
20969 * 0b0..ENET1 stop acknowledge is not asserted
20970 * 0b1..ENET1 stop acknowledge is asserted
20971 */
20972#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
20973#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U)
20974#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U)
20975/* SAI1_STOP_ACK
20976 * 0b0..SAI1 stop acknowledge is not asserted
20977 * 0b1..SAI1 stop acknowledge is asserted
20978 */
20979#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK)
20980#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U)
20981#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U)
20982/* SAI2_STOP_ACK
20983 * 0b0..SAI2 stop acknowledge is not asserted
20984 * 0b1..SAI2 stop acknowledge is asserted
20985 */
20986#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK)
20987#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U)
20988#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U)
20989/* SAI3_STOP_ACK
20990 * 0b0..SAI3 stop acknowledge is not asserted
20991 * 0b1..SAI3 stop acknowledge is asserted
20992 */
20993#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK)
20994#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x1000000U)
20995#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (24U)
20996/* ENET2_STOP_ACK
20997 * 0b0..ENET2 stop acknowledge is not asserted
20998 * 0b1..ENET2 stop acknowledge is asserted
20999 */
21000#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK)
21001#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U)
21002#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U)
21003/* SEMC_STOP_ACK
21004 * 0b0..SEMC stop acknowledge is not asserted
21005 * 0b1..SEMC stop acknowledge is asserted
21006 */
21007#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK)
21008#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U)
21009#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U)
21010/* PIT_STOP_ACK
21011 * 0b0..PIT stop acknowledge is not asserted
21012 * 0b1..PIT stop acknowledge is asserted
21013 */
21014#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK)
21015#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U)
21016#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U)
21017/* FLEXSPI_STOP_ACK
21018 * 0b0..FLEXSPI stop acknowledge is not asserted
21019 * 0b1..FLEXSPI stop acknowledge is asserted
21020 */
21021#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK)
21022#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U)
21023#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U)
21024/* FLEXIO1_STOP_ACK
21025 * 0b0..FLEXIO1 stop acknowledge is not asserted
21026 * 0b1..FLEXIO1 stop acknowledge is asserted
21027 */
21028#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK)
21029#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U)
21030#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U)
21031/* FLEXIO2_STOP_ACK
21032 * 0b0..FLEXIO2 stop acknowledge is not asserted
21033 * 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode)
21034 */
21035#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
21036#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK (0x40000000U)
21037#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT (30U)
21038/* FLEXIO3_STOP_ACK
21039 * 0b0..FLEXIO3 stop acknowledge is not asserted
21040 * 0b1..FLEXIO3 stop acknowledge is asserted
21041 */
21042#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK)
21043#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK (0x80000000U)
21044#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT (31U)
21045/* FLEXSPI2_STOP_ACK
21046 * 0b0..FLEXSPI2 stop acknowledge is not asserted
21047 * 0b1..FLEXSPI2 stop acknowledge is asserted
21048 */
21049#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK)
21050/* @} */
21051
21052/* @name GPR5 - GPR5 General Purpose Register */
21053/* @{ */
21054#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U)
21055#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U)
21056/* WDOG1_MASK
21057 * 0b0..WDOG1 Timeout behaves normally
21058 * 0b1..WDOG1 Timeout is masked
21059 */
21060#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK)
21061#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U)
21062#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U)
21063/* WDOG2_MASK
21064 * 0b0..WDOG2 Timeout behaves normally
21065 * 0b1..WDOG2 Timeout is masked
21066 */
21067#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK)
21068#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U)
21069#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U)
21070/* GPT2_CAPIN1_SEL
21071 * 0b0..source from GPT2_CAPTURE1
21072 * 0b1..source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)
21073 */
21074#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK)
21075#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U)
21076#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U)
21077/* GPT2_CAPIN2_SEL
21078 * 0b0..source from GPT2_CAPTURE2
21079 * 0b1..source from ENET2_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer)
21080 */
21081#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK)
21082#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U)
21083#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U)
21084/* ENET_EVENT3IN_SEL
21085 * 0b0..event3 source input from ENET_1588_EVENT3_IN
21086 * 0b1..event3 source input from GPT2.GPT_COMPARE1
21087 */
21088#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK)
21089#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U)
21090#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U)
21091/* ENET2_EVENT3IN_SEL
21092 * 0b0..event3 source input from ENET2_1588_EVENT3_IN
21093 * 0b1..event3 source input from GPT2.GPT_COMPARE2
21094 */
21095#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK)
21096#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U)
21097#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U)
21098/* VREF_1M_CLK_GPT1
21099 * 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK
21100 * 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock
21101 */
21102#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK)
21103#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U)
21104#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U)
21105/* VREF_1M_CLK_GPT2
21106 * 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK
21107 * 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock
21108 */
21109#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK)
21110/* @} */
21111
21112/* @name GPR6 - GPR6 General Purpose Register */
21113/* @{ */
21114#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U)
21115#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U)
21116/* QTIMER1_TRM0_INPUT_SEL
21117 * 0b0..input from IOMUX
21118 * 0b1..input from XBAR
21119 */
21120#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK)
21121#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U)
21122#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U)
21123/* QTIMER1_TRM1_INPUT_SEL
21124 * 0b0..input from IOMUX
21125 * 0b1..input from XBAR
21126 */
21127#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK)
21128#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U)
21129#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U)
21130/* QTIMER1_TRM2_INPUT_SEL
21131 * 0b0..input from IOMUX
21132 * 0b1..input from XBAR
21133 */
21134#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK)
21135#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U)
21136#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U)
21137/* QTIMER1_TRM3_INPUT_SEL
21138 * 0b0..input from IOMUX
21139 * 0b1..input from XBAR
21140 */
21141#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK)
21142#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U)
21143#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U)
21144/* QTIMER2_TRM0_INPUT_SEL
21145 * 0b0..input from IOMUX
21146 * 0b1..input from XBAR
21147 */
21148#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK)
21149#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U)
21150#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U)
21151/* QTIMER2_TRM1_INPUT_SEL
21152 * 0b0..input from IOMUX
21153 * 0b1..input from XBAR
21154 */
21155#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK)
21156#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U)
21157#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U)
21158/* QTIMER2_TRM2_INPUT_SEL
21159 * 0b0..input from IOMUX
21160 * 0b1..input from XBAR
21161 */
21162#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK)
21163#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U)
21164#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U)
21165/* QTIMER2_TRM3_INPUT_SEL
21166 * 0b0..input from IOMUX
21167 * 0b1..input from XBAR
21168 */
21169#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK)
21170#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
21171#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
21172/* QTIMER3_TRM0_INPUT_SEL
21173 * 0b0..input from IOMUX
21174 * 0b1..input from XBAR
21175 */
21176#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK)
21177#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
21178#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
21179/* QTIMER3_TRM1_INPUT_SEL
21180 * 0b0..input from IOMUX
21181 * 0b1..input from XBAR
21182 */
21183#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK)
21184#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
21185#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
21186/* QTIMER3_TRM2_INPUT_SEL
21187 * 0b0..input from IOMUX
21188 * 0b1..input from XBAR
21189 */
21190#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK)
21191#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
21192#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
21193/* QTIMER3_TRM3_INPUT_SEL
21194 * 0b0..input from IOMUX
21195 * 0b1..input from XBAR
21196 */
21197#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK)
21198#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U)
21199#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U)
21200/* QTIMER4_TRM0_INPUT_SEL
21201 * 0b0..input from IOMUX
21202 * 0b1..input from XBAR
21203 */
21204#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK)
21205#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U)
21206#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U)
21207/* QTIMER4_TRM1_INPUT_SEL
21208 * 0b0..input from IOMUX
21209 * 0b1..input from XBAR
21210 */
21211#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK)
21212#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U)
21213#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U)
21214/* QTIMER4_TRM2_INPUT_SEL
21215 * 0b0..input from IOMUX
21216 * 0b1..input from XBAR
21217 */
21218#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK)
21219#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U)
21220#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U)
21221/* QTIMER4_TRM3_INPUT_SEL
21222 * 0b0..input from IOMUX
21223 * 0b1..input from XBAR
21224 */
21225#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK)
21226#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U)
21227#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U)
21228/* IOMUXC_XBAR_DIR_SEL_4
21229 * 0b0..XBAR_INOUT as input
21230 * 0b1..XBAR_INOUT as output
21231 */
21232#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK)
21233#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U)
21234#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U)
21235/* IOMUXC_XBAR_DIR_SEL_5
21236 * 0b0..XBAR_INOUT as input
21237 * 0b1..XBAR_INOUT as output
21238 */
21239#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK)
21240#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U)
21241#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U)
21242/* IOMUXC_XBAR_DIR_SEL_6
21243 * 0b0..XBAR_INOUT as input
21244 * 0b1..XBAR_INOUT as output
21245 */
21246#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK)
21247#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U)
21248#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U)
21249/* IOMUXC_XBAR_DIR_SEL_7
21250 * 0b0..XBAR_INOUT as input
21251 * 0b1..XBAR_INOUT as output
21252 */
21253#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK)
21254#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U)
21255#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U)
21256/* IOMUXC_XBAR_DIR_SEL_8
21257 * 0b0..XBAR_INOUT as input
21258 * 0b1..XBAR_INOUT as output
21259 */
21260#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK)
21261#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U)
21262#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U)
21263/* IOMUXC_XBAR_DIR_SEL_9
21264 * 0b0..XBAR_INOUT as input
21265 * 0b1..XBAR_INOUT as output
21266 */
21267#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK)
21268#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U)
21269#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U)
21270/* IOMUXC_XBAR_DIR_SEL_10
21271 * 0b0..XBAR_INOUT as input
21272 * 0b1..XBAR_INOUT as output
21273 */
21274#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK)
21275#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U)
21276#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U)
21277/* IOMUXC_XBAR_DIR_SEL_11
21278 * 0b0..XBAR_INOUT as input
21279 * 0b1..XBAR_INOUT as output
21280 */
21281#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK)
21282#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U)
21283#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U)
21284/* IOMUXC_XBAR_DIR_SEL_12
21285 * 0b0..XBAR_INOUT as input
21286 * 0b1..XBAR_INOUT as output
21287 */
21288#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK)
21289#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U)
21290#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U)
21291/* IOMUXC_XBAR_DIR_SEL_13
21292 * 0b0..XBAR_INOUT as input
21293 * 0b1..XBAR_INOUT as output
21294 */
21295#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK)
21296#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U)
21297#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U)
21298/* IOMUXC_XBAR_DIR_SEL_14
21299 * 0b0..XBAR_INOUT as input
21300 * 0b1..XBAR_INOUT as output
21301 */
21302#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK)
21303#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U)
21304#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U)
21305/* IOMUXC_XBAR_DIR_SEL_15
21306 * 0b0..XBAR_INOUT as input
21307 * 0b1..XBAR_INOUT as output
21308 */
21309#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK)
21310#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U)
21311#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U)
21312/* IOMUXC_XBAR_DIR_SEL_16
21313 * 0b0..XBAR_INOUT as input
21314 * 0b1..XBAR_INOUT as output
21315 */
21316#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK)
21317#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U)
21318#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U)
21319/* IOMUXC_XBAR_DIR_SEL_17
21320 * 0b0..XBAR_INOUT as input
21321 * 0b1..XBAR_INOUT as output
21322 */
21323#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK)
21324#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U)
21325#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U)
21326/* IOMUXC_XBAR_DIR_SEL_18
21327 * 0b0..XBAR_INOUT as input
21328 * 0b1..XBAR_INOUT as output
21329 */
21330#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK)
21331#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U)
21332#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U)
21333/* IOMUXC_XBAR_DIR_SEL_19
21334 * 0b0..XBAR_INOUT as input
21335 * 0b1..XBAR_INOUT as output
21336 */
21337#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK)
21338/* @} */
21339
21340/* @name GPR7 - GPR7 General Purpose Register */
21341/* @{ */
21342#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U)
21343#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U)
21344/* LPI2C1_STOP_REQ
21345 * 0b0..stop request off
21346 * 0b1..stop request on
21347 */
21348#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK)
21349#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U)
21350#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U)
21351/* LPI2C2_STOP_REQ
21352 * 0b0..stop request off
21353 * 0b1..stop request on
21354 */
21355#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK)
21356#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U)
21357#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U)
21358/* LPI2C3_STOP_REQ
21359 * 0b0..stop request off
21360 * 0b1..stop request on
21361 */
21362#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK)
21363#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U)
21364#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U)
21365/* LPI2C4_STOP_REQ
21366 * 0b0..stop request off
21367 * 0b1..stop request on
21368 */
21369#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK)
21370#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U)
21371#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U)
21372/* LPSPI1_STOP_REQ
21373 * 0b0..stop request off
21374 * 0b1..stop request on
21375 */
21376#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK)
21377#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U)
21378#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U)
21379/* LPSPI2_STOP_REQ
21380 * 0b0..stop request off
21381 * 0b1..stop request on
21382 */
21383#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK)
21384#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U)
21385#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U)
21386/* LPSPI3_STOP_REQ
21387 * 0b0..stop request off
21388 * 0b1..stop request on
21389 */
21390#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK)
21391#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U)
21392#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U)
21393/* LPSPI4_STOP_REQ
21394 * 0b0..stop request off
21395 * 0b1..stop request on
21396 */
21397#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK)
21398#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U)
21399#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U)
21400/* LPUART1_STOP_REQ
21401 * 0b0..stop request off
21402 * 0b1..stop request on
21403 */
21404#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK)
21405#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U)
21406#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U)
21407/* LPUART2_STOP_REQ
21408 * 0b0..stop request off
21409 * 0b1..stop request on
21410 */
21411#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK)
21412#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U)
21413#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U)
21414/* LPUART3_STOP_REQ
21415 * 0b0..stop request off
21416 * 0b1..stop request on
21417 */
21418#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK)
21419#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U)
21420#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U)
21421/* LPUART4_STOP_REQ
21422 * 0b0..stop request off
21423 * 0b1..stop request on
21424 */
21425#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK)
21426#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U)
21427#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U)
21428/* LPUART5_STOP_REQ
21429 * 0b0..stop request off
21430 * 0b1..stop request on
21431 */
21432#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK)
21433#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U)
21434#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U)
21435/* LPUART6_STOP_REQ
21436 * 0b0..stop request off
21437 * 0b1..stop request on
21438 */
21439#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK)
21440#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U)
21441#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U)
21442/* LPUART7_STOP_REQ
21443 * 0b0..stop request off
21444 * 0b1..stop request on
21445 */
21446#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK)
21447#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U)
21448#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U)
21449/* LPUART8_STOP_REQ
21450 * 0b0..stop request off
21451 * 0b1..stop request on
21452 */
21453#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
21454#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U)
21455#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U)
21456/* LPI2C1_STOP_ACK
21457 * 0b0..stop acknowledge is not asserted
21458 * 0b1..stop acknowledge is asserted (the module is in Stop mode)
21459 */
21460#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK)
21461#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U)
21462#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U)
21463/* LPI2C2_STOP_ACK
21464 * 0b0..stop acknowledge is not asserted
21465 * 0b1..stop acknowledge is asserted
21466 */
21467#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK)
21468#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U)
21469#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U)
21470/* LPI2C3_STOP_ACK
21471 * 0b0..stop acknowledge is not asserted
21472 * 0b1..stop acknowledge is asserted
21473 */
21474#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK)
21475#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U)
21476#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U)
21477/* LPI2C4_STOP_ACK
21478 * 0b0..stop acknowledge is not asserted
21479 * 0b1..stop acknowledge is asserted
21480 */
21481#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK)
21482#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U)
21483#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U)
21484/* LPSPI1_STOP_ACK
21485 * 0b0..stop acknowledge is not asserted
21486 * 0b1..stop acknowledge is asserted
21487 */
21488#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK)
21489#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U)
21490#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U)
21491/* LPSPI2_STOP_ACK
21492 * 0b0..stop acknowledge is not asserted
21493 * 0b1..stop acknowledge is asserted
21494 */
21495#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK)
21496#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U)
21497#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U)
21498/* LPSPI3_STOP_ACK
21499 * 0b0..stop acknowledge is not asserted
21500 * 0b1..stop acknowledge is asserted
21501 */
21502#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK)
21503#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U)
21504#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U)
21505/* LPSPI4_STOP_ACK
21506 * 0b0..stop acknowledge is not asserted
21507 * 0b1..stop acknowledge is asserted
21508 */
21509#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK)
21510#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U)
21511#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U)
21512/* LPUART1_STOP_ACK
21513 * 0b0..stop acknowledge is not asserted
21514 * 0b1..stop acknowledge is asserted
21515 */
21516#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK)
21517#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U)
21518#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U)
21519/* LPUART2_STOP_ACK
21520 * 0b0..stop acknowledge is not asserted
21521 * 0b1..stop acknowledge is asserted
21522 */
21523#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK)
21524#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U)
21525#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U)
21526/* LPUART3_STOP_ACK
21527 * 0b0..stop acknowledge is not asserted
21528 * 0b1..stop acknowledge is asserted
21529 */
21530#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK)
21531#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U)
21532#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U)
21533/* LPUART4_STOP_ACK
21534 * 0b0..stop acknowledge is not asserted
21535 * 0b1..stop acknowledge is asserted
21536 */
21537#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK)
21538#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U)
21539#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U)
21540/* LPUART5_STOP_ACK
21541 * 0b0..stop acknowledge is not asserted
21542 * 0b1..stop acknowledge is asserted
21543 */
21544#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK)
21545#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U)
21546#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U)
21547/* LPUART6_STOP_ACK
21548 * 0b0..stop acknowledge is not asserted
21549 * 0b1..stop acknowledge is asserted
21550 */
21551#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK)
21552#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U)
21553#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U)
21554/* LPUART7_STOP_ACK
21555 * 0b0..stop acknowledge is not asserted
21556 * 0b1..stop acknowledge is asserted
21557 */
21558#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK)
21559#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U)
21560#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U)
21561/* LPUART8_STOP_ACK
21562 * 0b0..stop acknowledge is not asserted
21563 * 0b1..stop acknowledge is asserted (the module is in Stop mode)
21564 */
21565#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
21566/* @} */
21567
21568/* @name GPR8 - GPR8 General Purpose Register */
21569/* @{ */
21570#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U)
21571#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U)
21572/* LPI2C1_IPG_STOP_MODE
21573 * 0b0..the module is functional in Stop mode
21574 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21575 */
21576#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK)
21577#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U)
21578#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U)
21579/* LPI2C1_IPG_DOZE
21580 * 0b0..not in doze mode
21581 * 0b1..in doze mode
21582 */
21583#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK)
21584#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U)
21585#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U)
21586/* LPI2C2_IPG_STOP_MODE
21587 * 0b0..the module is functional in Stop mode
21588 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21589 */
21590#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK)
21591#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U)
21592#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U)
21593/* LPI2C2_IPG_DOZE
21594 * 0b0..not in doze mode
21595 * 0b1..in doze mode
21596 */
21597#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK)
21598#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U)
21599#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U)
21600/* LPI2C3_IPG_STOP_MODE
21601 * 0b0..the module is functional in Stop mode
21602 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21603 */
21604#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK)
21605#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U)
21606#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U)
21607/* LPI2C3_IPG_DOZE
21608 * 0b0..not in doze mode
21609 * 0b1..in doze mode
21610 */
21611#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK)
21612#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U)
21613#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U)
21614/* LPI2C4_IPG_STOP_MODE
21615 * 0b0..the module is functional in Stop mode
21616 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21617 */
21618#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK)
21619#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U)
21620#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U)
21621/* LPI2C4_IPG_DOZE
21622 * 0b0..not in doze mode
21623 * 0b1..in doze mode
21624 */
21625#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK)
21626#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U)
21627#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U)
21628/* LPSPI1_IPG_STOP_MODE
21629 * 0b0..the module is functional in Stop mode
21630 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21631 */
21632#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK)
21633#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U)
21634#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U)
21635/* LPSPI1_IPG_DOZE
21636 * 0b0..not in doze mode
21637 * 0b1..in doze mode
21638 */
21639#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK)
21640#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U)
21641#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U)
21642/* LPSPI2_IPG_STOP_MODE
21643 * 0b0..the module is functional in Stop mode
21644 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21645 */
21646#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK)
21647#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U)
21648#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U)
21649/* LPSPI2_IPG_DOZE
21650 * 0b0..not in doze mode
21651 * 0b1..in doze mode
21652 */
21653#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK)
21654#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U)
21655#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U)
21656/* LPSPI3_IPG_STOP_MODE
21657 * 0b0..the module is functional in Stop mode
21658 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21659 */
21660#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK)
21661#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U)
21662#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U)
21663/* LPSPI3_IPG_DOZE
21664 * 0b0..not in doze mode
21665 * 0b1..in doze mode
21666 */
21667#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK)
21668#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U)
21669#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U)
21670/* LPSPI4_IPG_STOP_MODE
21671 * 0b0..the module is functional in Stop mode
21672 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21673 */
21674#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK)
21675#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U)
21676#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U)
21677/* LPSPI4_IPG_DOZE
21678 * 0b0..not in doze mode
21679 * 0b1..in doze mode
21680 */
21681#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK)
21682#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U)
21683#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U)
21684/* LPUART1_IPG_STOP_MODE
21685 * 0b0..the module is functional in Stop mode
21686 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21687 */
21688#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK)
21689#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U)
21690#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U)
21691/* LPUART1_IPG_DOZE
21692 * 0b0..not in doze mode
21693 * 0b1..in doze mode
21694 */
21695#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK)
21696#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U)
21697#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U)
21698/* LPUART2_IPG_STOP_MODE
21699 * 0b0..the module is functional in Stop mode
21700 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21701 */
21702#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK)
21703#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U)
21704#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U)
21705/* LPUART2_IPG_DOZE
21706 * 0b0..not in doze mode
21707 * 0b1..in doze mode
21708 */
21709#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK)
21710#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U)
21711#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U)
21712/* LPUART3_IPG_STOP_MODE
21713 * 0b0..the module is functional in Stop mode
21714 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21715 */
21716#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK)
21717#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U)
21718#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U)
21719/* LPUART3_IPG_DOZE
21720 * 0b0..not in doze mode
21721 * 0b1..in doze mode
21722 */
21723#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK)
21724#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U)
21725#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U)
21726/* LPUART4_IPG_STOP_MODE
21727 * 0b0..the module is functional in Stop mode
21728 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21729 */
21730#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK)
21731#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U)
21732#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U)
21733/* LPUART4_IPG_DOZE
21734 * 0b0..not in doze mode
21735 * 0b1..in doze mode
21736 */
21737#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK)
21738#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U)
21739#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U)
21740/* LPUART5_IPG_STOP_MODE
21741 * 0b0..the module is functional in Stop mode
21742 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21743 */
21744#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK)
21745#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U)
21746#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U)
21747/* LPUART5_IPG_DOZE
21748 * 0b0..not in doze mode
21749 * 0b1..in doze mode
21750 */
21751#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK)
21752#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U)
21753#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U)
21754/* LPUART6_IPG_STOP_MODE
21755 * 0b0..the module is functional in Stop mode
21756 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21757 */
21758#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK)
21759#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U)
21760#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U)
21761/* LPUART6_IPG_DOZE
21762 * 0b0..not in doze mode
21763 * 0b1..in doze mode
21764 */
21765#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK)
21766#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U)
21767#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U)
21768/* LPUART7_IPG_STOP_MODE
21769 * 0b0..the module is functional in Stop mode
21770 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21771 */
21772#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK)
21773#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U)
21774#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U)
21775/* LPUART7_IPG_DOZE
21776 * 0b0..not in doze mode
21777 * 0b1..in doze mode
21778 */
21779#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK)
21780#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U)
21781#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U)
21782/* LPUART8_IPG_STOP_MODE
21783 * 0b0..the module is functional in Stop mode
21784 * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted
21785 */
21786#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
21787#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U)
21788#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U)
21789/* LPUART8_IPG_DOZE
21790 * 0b0..not in doze mode
21791 * 0b1..in doze mode
21792 */
21793#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
21794/* @} */
21795
21796/* @name GPR10 - GPR10 General Purpose Register */
21797/* @{ */
21798#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U)
21799#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U)
21800/* NIDEN
21801 * 0b0..Debug turned off.
21802 * 0b1..Debug enabled (default).
21803 */
21804#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK)
21805#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U)
21806#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U)
21807/* DBG_EN
21808 * 0b0..Debug turned off.
21809 * 0b1..Debug enabled (default).
21810 */
21811#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK)
21812#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U)
21813#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U)
21814/* SEC_ERR_RESP
21815 * 0b0..OKEY response
21816 * 0b1..SLVError (default)
21817 */
21818#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK)
21819#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U)
21820#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U)
21821/* DCPKEY_OCOTP_OR_KEYMUX
21822 * 0b0..Select key from Key MUX (SNVS/OTPMK).
21823 * 0b1..Select key from OCOTP (SW_GP2).
21824 */
21825#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK)
21826#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U)
21827#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U)
21828/* OCRAM_TZ_EN
21829 * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor).
21830 * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows
21831 * the execution mode access policy described in CSU chapter.
21832 */
21833#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK)
21834#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U)
21835#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U)
21836#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK)
21837#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U)
21838#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U)
21839/* LOCK_NIDEN
21840 * 0b0..Field is not locked
21841 * 0b1..Field is locked (read access only)
21842 */
21843#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK)
21844#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U)
21845#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U)
21846/* LOCK_DBG_EN
21847 * 0b0..Field is not locked
21848 * 0b1..Field is locked (read access only)
21849 */
21850#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK)
21851#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U)
21852#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U)
21853/* LOCK_SEC_ERR_RESP
21854 * 0b0..Field is not locked
21855 * 0b1..Field is locked (read access only)
21856 */
21857#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK)
21858#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U)
21859#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U)
21860/* LOCK_DCPKEY_OCOTP_OR_KEYMUX
21861 * 0b0..Field is not locked
21862 * 0b1..Field is locked (read access only)
21863 */
21864#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK)
21865#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U)
21866#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U)
21867/* LOCK_OCRAM_TZ_EN
21868 * 0b0..Field is not locked
21869 * 0b1..Field is locked (read access only)
21870 */
21871#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK)
21872#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U)
21873#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U)
21874/* LOCK_OCRAM_TZ_ADDR
21875 * 0b0000000..Field is not locked
21876 * 0b0000001..Field is locked (read access only)
21877 */
21878#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK)
21879/* @} */
21880
21881/* @name GPR11 - GPR11 General Purpose Register */
21882/* @{ */
21883#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U)
21884#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U)
21885/* M7_APC_AC_R0_CTRL
21886 * 0b00..No access protection
21887 * 0b01..M7 debug protection enabled
21888 * 0b10..FlexSPI access protection
21889 * 0b11..Both M7 debug and FlexSPI access are protected
21890 */
21891#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK)
21892#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU)
21893#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U)
21894/* M7_APC_AC_R1_CTRL
21895 * 0b00..No access protection
21896 * 0b01..M7 debug protection enabled
21897 * 0b10..FlexSPI access protection
21898 * 0b11..Both M7 debug and FlexSPI access are protected
21899 */
21900#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK)
21901#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U)
21902#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U)
21903/* M7_APC_AC_R2_CTRL
21904 * 0b00..No access protection
21905 * 0b01..M7 debug protection enabled
21906 * 0b10..FlexSPI access protection
21907 * 0b11..Both M7 debug and FlexSPI access are protected
21908 */
21909#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK)
21910#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U)
21911#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U)
21912/* M7_APC_AC_R3_CTRL
21913 * 0b00..No access protection
21914 * 0b01..M7 debug protection enabled
21915 * 0b10..FlexSPI access protection
21916 * 0b11..Both M7 debug and FlexSPI access are protected
21917 */
21918#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK)
21919#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U)
21920#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U)
21921#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK)
21922/* @} */
21923
21924/* @name GPR12 - GPR12 General Purpose Register */
21925/* @{ */
21926#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U)
21927#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U)
21928/* FLEXIO1_IPG_STOP_MODE
21929 * 0b0..FlexIO1 is functional in Stop mode.
21930 * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode.
21931 */
21932#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK)
21933#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U)
21934#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U)
21935/* FLEXIO1_IPG_DOZE
21936 * 0b0..FLEXIO1 is not in doze mode
21937 * 0b1..FLEXIO1 is in doze mode
21938 */
21939#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK)
21940#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U)
21941#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U)
21942/* FLEXIO2_IPG_STOP_MODE
21943 * 0b0..FlexIO2 is functional in Stop mode.
21944 * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode.
21945 */
21946#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
21947#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U)
21948#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U)
21949/* FLEXIO2_IPG_DOZE
21950 * 0b0..FLEXIO2 is not in doze mode
21951 * 0b1..FLEXIO2 is in doze mode
21952 */
21953#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
21954#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U)
21955#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U)
21956/* ACMP_IPG_STOP_MODE
21957 * 0b0..ACMP is functional in Stop mode.
21958 * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode.
21959 */
21960#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK)
21961#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK (0x20U)
21962#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT (5U)
21963/* FLEXIO3_IPG_STOP_MODE
21964 * 0b0..FlexIO3 is functional in Stop mode.
21965 * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO3 is not functional in Stop mode.
21966 */
21967#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK)
21968#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK (0x40U)
21969#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT (6U)
21970/* FLEXIO3_IPG_DOZE
21971 * 0b0..FLEXIO3 is not in doze mode
21972 * 0b1..FLEXIO3 is in doze mode
21973 */
21974#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK)
21975/* @} */
21976
21977/* @name GPR13 - GPR13 General Purpose Register */
21978/* @{ */
21979#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U)
21980#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U)
21981/* ARCACHE_USDHC
21982 * 0b0..Cacheable attribute is off for read transactions.
21983 * 0b1..Cacheable attribute is on for read transactions.
21984 */
21985#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK)
21986#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U)
21987#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U)
21988/* AWCACHE_USDHC
21989 * 0b0..Cacheable attribute is off for write transactions.
21990 * 0b1..Cacheable attribute is on for write transactions.
21991 */
21992#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK)
21993#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK (0x10U)
21994#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT (4U)
21995/* CANFD_STOP_REQ
21996 * 0b0..stop request off
21997 * 0b1..stop request on
21998 */
21999#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK)
22000#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U)
22001#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U)
22002/* CACHE_ENET
22003 * 0b0..Cacheable attribute is off for read/write transactions.
22004 * 0b1..Cacheable attribute is on for read/write transactions.
22005 */
22006#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK)
22007#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U)
22008#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U)
22009/* CACHE_USB
22010 * 0b0..Cacheable attribute is off for read/write transactions.
22011 * 0b1..Cacheable attribute is on for read/write transactions.
22012 */
22013#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK)
22014#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK (0x100000U)
22015#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT (20U)
22016/* CANFD_STOP_ACK
22017 * 0b0..CANFD stop acknowledge is not asserted
22018 * 0b1..CANFD stop acknowledge is asserted
22019 */
22020#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK)
22021/* @} */
22022
22023/* @name GPR14 - GPR14 General Purpose Register */
22024/* @{ */
22025#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U)
22026#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U)
22027/* ACMP1_CMP_IGEN_TRIM_DN
22028 * 0b0..no reduce
22029 * 0b1..reduces
22030 */
22031#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK)
22032#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U)
22033#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U)
22034/* ACMP2_CMP_IGEN_TRIM_DN
22035 * 0b0..no reduce
22036 * 0b1..reduces
22037 */
22038#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK)
22039#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U)
22040#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U)
22041/* ACMP3_CMP_IGEN_TRIM_DN
22042 * 0b0..no reduce
22043 * 0b1..reduces
22044 */
22045#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK)
22046#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U)
22047#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U)
22048/* ACMP4_CMP_IGEN_TRIM_DN
22049 * 0b0..no reduce
22050 * 0b1..reduces
22051 */
22052#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK)
22053#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U)
22054#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U)
22055/* ACMP1_CMP_IGEN_TRIM_UP
22056 * 0b0..no increase
22057 * 0b1..increases
22058 */
22059#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK)
22060#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U)
22061#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U)
22062/* ACMP2_CMP_IGEN_TRIM_UP
22063 * 0b0..no increase
22064 * 0b1..increases
22065 */
22066#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK)
22067#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U)
22068#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U)
22069/* ACMP3_CMP_IGEN_TRIM_UP
22070 * 0b0..no increase
22071 * 0b1..increases
22072 */
22073#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK)
22074#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U)
22075#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U)
22076/* ACMP4_CMP_IGEN_TRIM_UP
22077 * 0b0..no increase
22078 * 0b1..increases
22079 */
22080#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK)
22081#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U)
22082#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U)
22083/* ACMP1_SAMPLE_SYNC_EN
22084 * 0b0..select XBAR output
22085 * 0b1..select synced sample_lv
22086 */
22087#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK)
22088#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U)
22089#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U)
22090/* ACMP2_SAMPLE_SYNC_EN
22091 * 0b0..select XBAR output
22092 * 0b1..select synced sample_lv
22093 */
22094#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK)
22095#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U)
22096#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U)
22097/* ACMP3_SAMPLE_SYNC_EN
22098 * 0b0..select XBAR output
22099 * 0b1..select synced sample_lv
22100 */
22101#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK)
22102#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U)
22103#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U)
22104/* ACMP4_SAMPLE_SYNC_EN
22105 * 0b0..select XBAR output
22106 * 0b1..select synced sample_lv
22107 */
22108#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK)
22109#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U)
22110#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U)
22111/* CM7_CFGITCMSZ
22112 * 0b0000..0 KB (No ITCM)
22113 * 0b0011..4 KB
22114 * 0b0100..8 KB
22115 * 0b0101..16 KB
22116 * 0b0110..32 KB
22117 * 0b0111..64 KB
22118 * 0b1000..128 KB
22119 * 0b1001..256 KB
22120 * 0b1010..512 KB
22121 */
22122#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK)
22123#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U)
22124#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U)
22125/* CM7_CFGDTCMSZ
22126 * 0b0000..0 KB (No DTCM)
22127 * 0b0011..4 KB
22128 * 0b0100..8 KB
22129 * 0b0101..16 KB
22130 * 0b0110..32 KB
22131 * 0b0111..64 KB
22132 * 0b1000..128 KB
22133 * 0b1001..256 KB
22134 * 0b1010..512 KB
22135 */
22136#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK)
22137/* @} */
22138
22139/* @name GPR16 - GPR16 General Purpose Register */
22140/* @{ */
22141#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U)
22142#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U)
22143/* INIT_ITCM_EN
22144 * 0b0..ITCM is disabled
22145 * 0b1..ITCM is enabled
22146 */
22147#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK)
22148#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U)
22149#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U)
22150/* INIT_DTCM_EN
22151 * 0b0..DTCM is disabled
22152 * 0b1..DTCM is enabled
22153 */
22154#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK)
22155#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
22156#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
22157/* FLEXRAM_BANK_CFG_SEL
22158 * 0b0..use fuse value to config
22159 * 0b1..use FLEXRAM_BANK_CFG to config
22160 */
22161#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
22162/* @} */
22163
22164/* @name GPR17 - GPR17 General Purpose Register */
22165/* @{ */
22166#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU)
22167#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U)
22168#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK)
22169/* @} */
22170
22171/* @name GPR18 - GPR18 General Purpose Register */
22172/* @{ */
22173#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U)
22174#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U)
22175/* LOCK_M7_APC_AC_R0_BOT
22176 * 0b0..Register field [31:1] is not locked
22177 * 0b1..Register field [31:1] is locked (read access only)
22178 */
22179#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK)
22180#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
22181#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U)
22182#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK)
22183/* @} */
22184
22185/* @name GPR19 - GPR19 General Purpose Register */
22186/* @{ */
22187#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U)
22188#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U)
22189/* LOCK_M7_APC_AC_R0_TOP
22190 * 0b0..Register field [31:1] is not locked
22191 * 0b1..Register field [31:1] is locked (read access only)
22192 */
22193#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK)
22194#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
22195#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U)
22196#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK)
22197/* @} */
22198
22199/* @name GPR20 - GPR20 General Purpose Register */
22200/* @{ */
22201#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U)
22202#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U)
22203/* LOCK_M7_APC_AC_R1_BOT
22204 * 0b0..Register field [31:1] is not locked
22205 * 0b1..Register field [31:1] is locked (read access only)
22206 */
22207#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK)
22208#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
22209#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U)
22210#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK)
22211/* @} */
22212
22213/* @name GPR21 - GPR21 General Purpose Register */
22214/* @{ */
22215#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U)
22216#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U)
22217/* LOCK_M7_APC_AC_R1_TOP
22218 * 0b0..Register field [31:1] is not locked
22219 * 0b1..Register field [31:1] is locked (read access only)
22220 */
22221#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK)
22222#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
22223#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U)
22224#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK)
22225/* @} */
22226
22227/* @name GPR22 - GPR22 General Purpose Register */
22228/* @{ */
22229#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U)
22230#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U)
22231/* LOCK_M7_APC_AC_R2_BOT
22232 * 0b0..Register field [31:1] is not locked
22233 * 0b1..Register field [31:1] is locked (read access only)
22234 */
22235#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK)
22236#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
22237#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U)
22238#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK)
22239/* @} */
22240
22241/* @name GPR23 - GPR23 General Purpose Register */
22242/* @{ */
22243#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U)
22244#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U)
22245/* LOCK_M7_APC_AC_R2_TOP
22246 * 0b0..Register field [31:1] is not locked
22247 * 0b1..Register field [31:1] is locked (read access only)
22248 */
22249#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK)
22250#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
22251#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U)
22252#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK)
22253/* @} */
22254
22255/* @name GPR24 - GPR24 General Purpose Register */
22256/* @{ */
22257#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U)
22258#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U)
22259/* LOCK_M7_APC_AC_R3_BOT
22260 * 0b0..Register field [31:1] is not locked
22261 * 0b1..Register field [31:1] is locked (read access only)
22262 */
22263#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK)
22264#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
22265#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U)
22266#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK)
22267/* @} */
22268
22269/* @name GPR25 - GPR25 General Purpose Register */
22270/* @{ */
22271#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U)
22272#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U)
22273/* LOCK_M7_APC_AC_R3_TOP
22274 * 0b0..Register field [31:1] is not locked
22275 * 0b1..Register field [31:1] is locked (read access only)
22276 */
22277#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK)
22278#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
22279#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U)
22280#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK)
22281/* @} */
22282
22283/* @name GPR26 - GPR26 General Purpose Register */
22284/* @{ */
22285#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK (0xFFFFFFFFU)
22286#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT (0U)
22287#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)
22288/* @} */
22289
22290/* @name GPR27 - GPR27 General Purpose Register */
22291/* @{ */
22292#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK (0xFFFFFFFFU)
22293#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT (0U)
22294#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)
22295/* @} */
22296
22297/* @name GPR28 - GPR28 General Purpose Register */
22298/* @{ */
22299#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK (0xFFFFFFFFU)
22300#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT (0U)
22301#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK)
22302/* @} */
22303
22304/* @name GPR29 - GPR29 General Purpose Register */
22305/* @{ */
22306#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK (0xFFFFFFFFU)
22307#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT (0U)
22308#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK)
22309/* @} */
22310
22311/* @name GPR30 - GPR30 General Purpose Register */
22312/* @{ */
22313#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK (0xFFFFF000U)
22314#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT (12U)
22315#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT)) & IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK)
22316/* @} */
22317
22318/* @name GPR31 - GPR31 General Purpose Register */
22319/* @{ */
22320#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK (0xFFFFF000U)
22321#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT (12U)
22322#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT)) & IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK)
22323/* @} */
22324
22325/* @name GPR32 - GPR32 General Purpose Register */
22326/* @{ */
22327#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK (0xFFFFF000U)
22328#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT (12U)
22329#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT)) & IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK)
22330/* @} */
22331
22332/* @name GPR33 - GPR33 General Purpose Register */
22333/* @{ */
22334#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK (0x1U)
22335#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT (0U)
22336/* OCRAM2_TZ_EN
22337 * 0b0..The TrustZone feature is disabled. Entire OCRAM2 space is available for all access types (secure/non-secure/user/supervisor).
22338 * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows
22339 * the execution mode access policy described in CSU chapter.
22340 */
22341#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK)
22342#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK (0xFEU)
22343#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT (1U)
22344#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK)
22345#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK (0x10000U)
22346#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT (16U)
22347/* LOCK_OCRAM2_TZ_EN
22348 * 0b0..Field is not locked
22349 * 0b1..Field is locked (read access only)
22350 */
22351#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK)
22352#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK (0xFE0000U)
22353#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT (17U)
22354/* LOCK_OCRAM2_TZ_ADDR
22355 * 0b0000000..Field is not locked
22356 * 0b0000001..Field is locked (read access only)
22357 */
22358#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK)
22359/* @} */
22360
22361/* @name GPR34 - GPR34 General Purpose Register */
22362/* @{ */
22363#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK (0xFFU)
22364#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT (0U)
22365#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK)
22366#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK (0x100U)
22367#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT (8U)
22368/* SIP_TEST_MUX_QSPI_SIP_EN
22369 * 0b0..SIP_TEST_MUX is disabled
22370 * 0b1..SIP_TEST_MUX is enabled
22371 */
22372#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK)
22373/* @} */
22374
22375
22376/*
22377 * @}
22378 */ /* end of group IOMUXC_GPR_Register_Masks */
22379
22380
22381/* IOMUXC_GPR - Peripheral instance base addresses */
22382/* Peripheral IOMUXC_GPR base address */
22383#define IOMUXC_GPR_BASE (0x400AC000u)
22384/* Peripheral IOMUXC_GPR base pointer */
22385#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
22386/* Array initializer of IOMUXC_GPR peripheral base addresses */
22387#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
22388/* Array initializer of IOMUXC_GPR peripheral base pointers */
22389#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
22390
22391/*
22392 * @}
22393 */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
22394
22395
22396/* ----------------------------------------------------------------------------
22397 -- IOMUXC_SNVS Peripheral Access Layer
22398 ---------------------------------------------------------------------------- */
22399
22400/*
22401 * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer
22402 * @{
22403 */
22404
22405/* IOMUXC_SNVS - Register Layout Typedef */
22406typedef struct {
22407 union {
22408 __IO uint32_t SW_MUX_CTL_PAD[1];
22409 __IO uint32_t SW_MUX_CTL_PAD_WAKEUP;
22410 };
22411 __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ;
22412 __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ;
22413 __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE;
22414 __IO uint32_t SW_PAD_CTL_PAD_POR_B;
22415 __IO uint32_t SW_PAD_CTL_PAD_ONOFF;
22416 union {
22417 __IO uint32_t SW_PAD_CTL_PAD[1];
22418 __IO uint32_t SW_PAD_CTL_PAD_WAKEUP;
22419 };
22420 __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ;
22421 __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ;
22422} IOMUXC_SNVS_Type;
22423
22424/* ----------------------------------------------------------------------------
22425 -- IOMUXC_SNVS Register Masks
22426 ---------------------------------------------------------------------------- */
22427
22428/*
22429 * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks
22430 * @{
22431 */
22432
22433/* @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */
22434/* @{ */
22435#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U)
22436#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U)
22437/* MUX_MODE - MUX Mode Select Field.
22438 * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5
22439 * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue
22440 */
22441#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK)
22442#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U)
22443#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U)
22444/* SION - Software Input On Field.
22445 * 0b1..Force input path of pad WAKEUP
22446 * 0b0..Input Path is determined by functionality
22447 */
22448#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK)
22449/* @} */
22450
22451/* @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */
22452/* @{ */
22453#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U)
22454#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U)
22455/* MUX_MODE - MUX Mode Select Field.
22456 * 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp
22457 * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5
22458 */
22459#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK)
22460#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U)
22461#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U)
22462/* SION - Software Input On Field.
22463 * 0b1..Force input path of pad PMIC_ON_REQ
22464 * 0b0..Input Path is determined by functionality
22465 */
22466#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK)
22467/* @} */
22468
22469/* @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */
22470/* @{ */
22471#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U)
22472#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U)
22473/* MUX_MODE - MUX Mode Select Field.
22474 * 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm
22475 * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5
22476 */
22477#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK)
22478#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U)
22479#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U)
22480/* SION - Software Input On Field.
22481 * 0b1..Force input path of pad PMIC_STBY_REQ
22482 * 0b0..Input Path is determined by functionality
22483 */
22484#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK)
22485/* @} */
22486
22487/* @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */
22488/* @{ */
22489#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U)
22490#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U)
22491/* SRE - Slew Rate Field
22492 * 0b0..Slow Slew Rate
22493 * 0b1..Fast Slew Rate
22494 */
22495#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK)
22496#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U)
22497#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U)
22498/* DSE - Drive Strength Field
22499 * 0b000..output driver disabled;
22500 * 0b001..R0(260 Ohm @ 3.3V, 150 [email protected], 240 Ohm for DDR)
22501 * 0b010..R0/2
22502 * 0b011..R0/3
22503 * 0b100..R0/4
22504 * 0b101..R0/5
22505 * 0b110..R0/6
22506 * 0b111..R0/7
22507 */
22508#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK)
22509#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U)
22510#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U)
22511/* SPEED - Speed Field
22512 * 0b10..medium(100MHz)
22513 */
22514#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK)
22515#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U)
22516#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U)
22517/* ODE - Open Drain Enable Field
22518 * 0b0..Open Drain Disabled
22519 * 0b1..Open Drain Enabled
22520 */
22521#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK)
22522#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U)
22523#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U)
22524/* PKE - Pull / Keep Enable Field
22525 * 0b0..Pull/Keeper Disabled
22526 * 0b1..Pull/Keeper Enabled
22527 */
22528#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK)
22529#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U)
22530#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U)
22531/* PUE - Pull / Keep Select Field
22532 * 0b0..Keeper
22533 * 0b1..Pull
22534 */
22535#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK)
22536#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U)
22537#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U)
22538/* PUS - Pull Up / Down Config. Field
22539 * 0b00..100K Ohm Pull Down
22540 * 0b01..47K Ohm Pull Up
22541 * 0b10..100K Ohm Pull Up
22542 * 0b11..22K Ohm Pull Up
22543 */
22544#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK)
22545#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U)
22546#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U)
22547/* HYS - Hyst. Enable Field
22548 * 0b0..Hysteresis Disabled
22549 * 0b1..Hysteresis Enabled
22550 */
22551#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK)
22552/* @} */
22553
22554/* @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */
22555/* @{ */
22556#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U)
22557#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U)
22558/* SRE - Slew Rate Field
22559 * 0b0..Slow Slew Rate
22560 * 0b1..Fast Slew Rate
22561 */
22562#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK)
22563#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U)
22564#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U)
22565/* DSE - Drive Strength Field
22566 * 0b000..output driver disabled;
22567 * 0b001..R0(260 Ohm @ 3.3V, 150 [email protected], 240 Ohm for DDR)
22568 * 0b010..R0/2
22569 * 0b011..R0/3
22570 * 0b100..R0/4
22571 * 0b101..R0/5
22572 * 0b110..R0/6
22573 * 0b111..R0/7
22574 */
22575#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK)
22576#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U)
22577#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U)
22578/* SPEED - Speed Field
22579 * 0b10..medium(100MHz)
22580 */
22581#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK)
22582#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U)
22583#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U)
22584/* ODE - Open Drain Enable Field
22585 * 0b0..Open Drain Disabled
22586 * 0b1..Open Drain Enabled
22587 */
22588#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK)
22589#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U)
22590#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U)
22591/* PKE - Pull / Keep Enable Field
22592 * 0b0..Pull/Keeper Disabled
22593 * 0b1..Pull/Keeper Enabled
22594 */
22595#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK)
22596#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U)
22597#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U)
22598/* PUE - Pull / Keep Select Field
22599 * 0b0..Keeper
22600 * 0b1..Pull
22601 */
22602#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK)
22603#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U)
22604#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U)
22605/* PUS - Pull Up / Down Config. Field
22606 * 0b00..100K Ohm Pull Down
22607 * 0b01..47K Ohm Pull Up
22608 * 0b10..100K Ohm Pull Up
22609 * 0b11..22K Ohm Pull Up
22610 */
22611#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK)
22612#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U)
22613#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U)
22614/* HYS - Hyst. Enable Field
22615 * 0b0..Hysteresis Disabled
22616 * 0b1..Hysteresis Enabled
22617 */
22618#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK)
22619/* @} */
22620
22621/* @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */
22622/* @{ */
22623#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U)
22624#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U)
22625/* SRE - Slew Rate Field
22626 * 0b0..Slow Slew Rate
22627 * 0b1..Fast Slew Rate
22628 */
22629#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK)
22630#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U)
22631#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U)
22632/* DSE - Drive Strength Field
22633 * 0b000..output driver disabled;
22634 * 0b001..R0(260 Ohm @ 3.3V, 150 [email protected], 240 Ohm for DDR)
22635 * 0b010..R0/2
22636 * 0b011..R0/3
22637 * 0b100..R0/4
22638 * 0b101..R0/5
22639 * 0b110..R0/6
22640 * 0b111..R0/7
22641 */
22642#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK)
22643#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U)
22644#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U)
22645/* SPEED - Speed Field
22646 * 0b10..medium(100MHz)
22647 */
22648#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK)
22649#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U)
22650#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U)
22651/* ODE - Open Drain Enable Field
22652 * 0b0..Open Drain Disabled
22653 * 0b1..Open Drain Enabled
22654 */
22655#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK)
22656#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U)
22657#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U)
22658/* PKE - Pull / Keep Enable Field
22659 * 0b0..Pull/Keeper Disabled
22660 * 0b1..Pull/Keeper Enabled
22661 */
22662#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK)
22663#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U)
22664#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U)
22665/* PUE - Pull / Keep Select Field
22666 * 0b0..Keeper
22667 * 0b1..Pull
22668 */
22669#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK)
22670#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U)
22671#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U)
22672/* PUS - Pull Up / Down Config. Field
22673 * 0b00..100K Ohm Pull Down
22674 * 0b01..47K Ohm Pull Up
22675 * 0b10..100K Ohm Pull Up
22676 * 0b11..22K Ohm Pull Up
22677 */
22678#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK)
22679#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U)
22680#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U)
22681/* HYS - Hyst. Enable Field
22682 * 0b0..Hysteresis Disabled
22683 * 0b1..Hysteresis Enabled
22684 */
22685#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK)
22686/* @} */
22687
22688/* @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */
22689/* @{ */
22690#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U)
22691#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U)
22692/* SRE - Slew Rate Field
22693 * 0b0..Slow Slew Rate
22694 * 0b1..Fast Slew Rate
22695 */
22696#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK)
22697#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U)
22698#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U)
22699/* DSE - Drive Strength Field
22700 * 0b000..output driver disabled;
22701 * 0b001..R0(260 Ohm @ 3.3V, 150 [email protected], 240 Ohm for DDR)
22702 * 0b010..R0/2
22703 * 0b011..R0/3
22704 * 0b100..R0/4
22705 * 0b101..R0/5
22706 * 0b110..R0/6
22707 * 0b111..R0/7
22708 */
22709#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK)
22710#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U)
22711#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U)
22712/* SPEED - Speed Field
22713 * 0b10..medium(100MHz)
22714 */
22715#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK)
22716#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U)
22717#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U)
22718/* ODE - Open Drain Enable Field
22719 * 0b0..Open Drain Disabled
22720 * 0b1..Open Drain Enabled
22721 */
22722#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK)
22723#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U)
22724#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U)
22725/* PKE - Pull / Keep Enable Field
22726 * 0b0..Pull/Keeper Disabled
22727 * 0b1..Pull/Keeper Enabled
22728 */
22729#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK)
22730#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U)
22731#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U)
22732/* PUE - Pull / Keep Select Field
22733 * 0b0..Keeper
22734 * 0b1..Pull
22735 */
22736#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK)
22737#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U)
22738#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U)
22739/* PUS - Pull Up / Down Config. Field
22740 * 0b00..100K Ohm Pull Down
22741 * 0b01..47K Ohm Pull Up
22742 * 0b10..100K Ohm Pull Up
22743 * 0b11..22K Ohm Pull Up
22744 */
22745#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK)
22746#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U)
22747#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U)
22748/* HYS - Hyst. Enable Field
22749 * 0b0..Hysteresis Disabled
22750 * 0b1..Hysteresis Enabled
22751 */
22752#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK)
22753/* @} */
22754
22755/* @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */
22756/* @{ */
22757#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U)
22758#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U)
22759/* SRE - Slew Rate Field
22760 * 0b0..Slow Slew Rate
22761 * 0b1..Fast Slew Rate
22762 */
22763#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK)
22764#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U)
22765#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U)
22766/* DSE - Drive Strength Field
22767 * 0b000..output driver disabled;
22768 * 0b001..R0(260 Ohm @ 3.3V, 150 [email protected], 240 Ohm for DDR)
22769 * 0b010..R0/2
22770 * 0b011..R0/3
22771 * 0b100..R0/4
22772 * 0b101..R0/5
22773 * 0b110..R0/6
22774 * 0b111..R0/7
22775 */
22776#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK)
22777#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U)
22778#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U)
22779/* SPEED - Speed Field
22780 * 0b10..medium(100MHz)
22781 */
22782#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK)
22783#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U)
22784#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U)
22785/* ODE - Open Drain Enable Field
22786 * 0b0..Open Drain Disabled
22787 * 0b1..Open Drain Enabled
22788 */
22789#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK)
22790#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U)
22791#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U)
22792/* PKE - Pull / Keep Enable Field
22793 * 0b0..Pull/Keeper Disabled
22794 * 0b1..Pull/Keeper Enabled
22795 */
22796#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK)
22797#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U)
22798#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U)
22799/* PUE - Pull / Keep Select Field
22800 * 0b0..Keeper
22801 * 0b1..Pull
22802 */
22803#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK)
22804#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U)
22805#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U)
22806/* PUS - Pull Up / Down Config. Field
22807 * 0b00..100K Ohm Pull Down
22808 * 0b01..47K Ohm Pull Up
22809 * 0b10..100K Ohm Pull Up
22810 * 0b11..22K Ohm Pull Up
22811 */
22812#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK)
22813#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U)
22814#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U)
22815/* HYS - Hyst. Enable Field
22816 * 0b0..Hysteresis Disabled
22817 * 0b1..Hysteresis Enabled
22818 */
22819#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK)
22820/* @} */
22821
22822/* @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */
22823/* @{ */
22824#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U)
22825#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U)
22826/* SRE - Slew Rate Field
22827 * 0b0..Slow Slew Rate
22828 * 0b1..Fast Slew Rate
22829 */
22830#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK)
22831#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U)
22832#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U)
22833/* DSE - Drive Strength Field
22834 * 0b000..output driver disabled;
22835 * 0b001..R0(260 Ohm @ 3.3V, 150 [email protected], 240 Ohm for DDR)
22836 * 0b010..R0/2
22837 * 0b011..R0/3
22838 * 0b100..R0/4
22839 * 0b101..R0/5
22840 * 0b110..R0/6
22841 * 0b111..R0/7
22842 */
22843#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK)
22844#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U)
22845#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U)
22846/* SPEED - Speed Field
22847 * 0b10..medium(100MHz)
22848 */
22849#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK)
22850#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U)
22851#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U)
22852/* ODE - Open Drain Enable Field
22853 * 0b0..Open Drain Disabled
22854 * 0b1..Open Drain Enabled
22855 */
22856#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK)
22857#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U)
22858#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U)
22859/* PKE - Pull / Keep Enable Field
22860 * 0b0..Pull/Keeper Disabled
22861 * 0b1..Pull/Keeper Enabled
22862 */
22863#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK)
22864#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U)
22865#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U)
22866/* PUE - Pull / Keep Select Field
22867 * 0b0..Keeper
22868 * 0b1..Pull
22869 */
22870#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK)
22871#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U)
22872#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U)
22873/* PUS - Pull Up / Down Config. Field
22874 * 0b00..100K Ohm Pull Down
22875 * 0b01..47K Ohm Pull Up
22876 * 0b10..100K Ohm Pull Up
22877 * 0b11..22K Ohm Pull Up
22878 */
22879#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK)
22880#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U)
22881#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U)
22882/* HYS - Hyst. Enable Field
22883 * 0b0..Hysteresis Disabled
22884 * 0b1..Hysteresis Enabled
22885 */
22886#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK)
22887/* @} */
22888
22889
22890/*
22891 * @}
22892 */ /* end of group IOMUXC_SNVS_Register_Masks */
22893
22894
22895/* IOMUXC_SNVS - Peripheral instance base addresses */
22896/* Peripheral IOMUXC_SNVS base address */
22897#define IOMUXC_SNVS_BASE (0x400A8000u)
22898/* Peripheral IOMUXC_SNVS base pointer */
22899#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
22900/* Array initializer of IOMUXC_SNVS peripheral base addresses */
22901#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
22902/* Array initializer of IOMUXC_SNVS peripheral base pointers */
22903#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
22904
22905/*
22906 * @}
22907 */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
22908
22909
22910/* ----------------------------------------------------------------------------
22911 -- IOMUXC_SNVS_GPR Peripheral Access Layer
22912 ---------------------------------------------------------------------------- */
22913
22914/*
22915 * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer
22916 * @{
22917 */
22918
22919/* IOMUXC_SNVS_GPR - Register Layout Typedef */
22920typedef struct {
22921 uint32_t GPR0;
22922 uint32_t GPR1;
22923 uint32_t GPR2;
22924 __IO uint32_t GPR3;
22925} IOMUXC_SNVS_GPR_Type;
22926
22927/* ----------------------------------------------------------------------------
22928 -- IOMUXC_SNVS_GPR Register Masks
22929 ---------------------------------------------------------------------------- */
22930
22931/*
22932 * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks
22933 * @{
22934 */
22935
22936/* @name GPR3 - GPR3 General Purpose Register */
22937/* @{ */
22938#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U)
22939#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U)
22940#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK)
22941#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
22942#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
22943#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK)
22944#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU)
22945#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U)
22946#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK)
22947#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U)
22948#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U)
22949#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK)
22950#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U)
22951#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U)
22952#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK)
22953#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U)
22954#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U)
22955#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK)
22956#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U)
22957#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U)
22958#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK)
22959/* @} */
22960
22961
22962/*
22963 * @}
22964 */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */
22965
22966
22967/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
22968/* Peripheral IOMUXC_SNVS_GPR base address */
22969#define IOMUXC_SNVS_GPR_BASE (0x400A4000u)
22970/* Peripheral IOMUXC_SNVS_GPR base pointer */
22971#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
22972/* Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */
22973#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
22974/* Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */
22975#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
22976
22977/*
22978 * @}
22979 */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
22980
22981
22982/* ----------------------------------------------------------------------------
22983 -- KPP Peripheral Access Layer
22984 ---------------------------------------------------------------------------- */
22985
22986/*
22987 * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
22988 * @{
22989 */
22990
22991/* KPP - Register Layout Typedef */
22992typedef struct {
22993 __IO uint16_t KPCR;
22994 __IO uint16_t KPSR;
22995 __IO uint16_t KDDR;
22996 __IO uint16_t KPDR;
22997} KPP_Type;
22998
22999/* ----------------------------------------------------------------------------
23000 -- KPP Register Masks
23001 ---------------------------------------------------------------------------- */
23002
23003/*
23004 * @addtogroup KPP_Register_Masks KPP Register Masks
23005 * @{
23006 */
23007
23008/* @name KPCR - Keypad Control Register */
23009/* @{ */
23010#define KPP_KPCR_KRE_MASK (0xFFU)
23011#define KPP_KPCR_KRE_SHIFT (0U)
23012/* KRE
23013 * 0b00000000..Row is not included in the keypad key press detect.
23014 * 0b00000001..Row is included in the keypad key press detect.
23015 */
23016#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
23017#define KPP_KPCR_KCO_MASK (0xFF00U)
23018#define KPP_KPCR_KCO_SHIFT (8U)
23019/* KCO
23020 * 0b00000000..Column strobe output is totem pole drive.
23021 * 0b00000001..Column strobe output is open drain.
23022 */
23023#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
23024/* @} */
23025
23026/* @name KPSR - Keypad Status Register */
23027/* @{ */
23028#define KPP_KPSR_KPKD_MASK (0x1U)
23029#define KPP_KPSR_KPKD_SHIFT (0U)
23030/* KPKD
23031 * 0b0..No key presses detected
23032 * 0b1..A key has been depressed
23033 */
23034#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
23035#define KPP_KPSR_KPKR_MASK (0x2U)
23036#define KPP_KPSR_KPKR_SHIFT (1U)
23037/* KPKR
23038 * 0b0..No key release detected
23039 * 0b1..All keys have been released
23040 */
23041#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
23042#define KPP_KPSR_KDSC_MASK (0x4U)
23043#define KPP_KPSR_KDSC_SHIFT (2U)
23044/* KDSC
23045 * 0b0..No effect
23046 * 0b1..Set bits that clear the keypad depress synchronizer chain
23047 */
23048#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
23049#define KPP_KPSR_KRSS_MASK (0x8U)
23050#define KPP_KPSR_KRSS_SHIFT (3U)
23051/* KRSS
23052 * 0b0..No effect
23053 * 0b1..Set bits which sets keypad release synchronizer chain
23054 */
23055#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
23056#define KPP_KPSR_KDIE_MASK (0x100U)
23057#define KPP_KPSR_KDIE_SHIFT (8U)
23058/* KDIE
23059 * 0b0..No interrupt request is generated when KPKD is set.
23060 * 0b1..An interrupt request is generated when KPKD is set.
23061 */
23062#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
23063#define KPP_KPSR_KRIE_MASK (0x200U)
23064#define KPP_KPSR_KRIE_SHIFT (9U)
23065/* KRIE
23066 * 0b0..No interrupt request is generated when KPKR is set.
23067 * 0b1..An interrupt request is generated when KPKR is set.
23068 */
23069#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
23070/* @} */
23071
23072/* @name KDDR - Keypad Data Direction Register */
23073/* @{ */
23074#define KPP_KDDR_KRDD_MASK (0xFFU)
23075#define KPP_KDDR_KRDD_SHIFT (0U)
23076/* KRDD
23077 * 0b00000000..ROWn pin configured as an input.
23078 * 0b00000001..ROWn pin configured as an output.
23079 */
23080#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
23081#define KPP_KDDR_KCDD_MASK (0xFF00U)
23082#define KPP_KDDR_KCDD_SHIFT (8U)
23083/* KCDD
23084 * 0b00000000..COLn pin is configured as an input.
23085 * 0b00000001..COLn pin is configured as an output.
23086 */
23087#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
23088/* @} */
23089
23090/* @name KPDR - Keypad Data Register */
23091/* @{ */
23092#define KPP_KPDR_KRD_MASK (0xFFU)
23093#define KPP_KPDR_KRD_SHIFT (0U)
23094#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
23095#define KPP_KPDR_KCD_MASK (0xFF00U)
23096#define KPP_KPDR_KCD_SHIFT (8U)
23097#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
23098/* @} */
23099
23100
23101/*
23102 * @}
23103 */ /* end of group KPP_Register_Masks */
23104
23105
23106/* KPP - Peripheral instance base addresses */
23107/* Peripheral KPP base address */
23108#define KPP_BASE (0x401FC000u)
23109/* Peripheral KPP base pointer */
23110#define KPP ((KPP_Type *)KPP_BASE)
23111/* Array initializer of KPP peripheral base addresses */
23112#define KPP_BASE_ADDRS { KPP_BASE }
23113/* Array initializer of KPP peripheral base pointers */
23114#define KPP_BASE_PTRS { KPP }
23115/* Interrupt vectors for the KPP peripheral type */
23116#define KPP_IRQS { KPP_IRQn }
23117
23118/*
23119 * @}
23120 */ /* end of group KPP_Peripheral_Access_Layer */
23121
23122
23123/* ----------------------------------------------------------------------------
23124 -- LPI2C Peripheral Access Layer
23125 ---------------------------------------------------------------------------- */
23126
23127/*
23128 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
23129 * @{
23130 */
23131
23132/* LPI2C - Register Layout Typedef */
23133typedef struct {
23134 __I uint32_t VERID;
23135 __I uint32_t PARAM;
23136 uint8_t RESERVED_0[8];
23137 __IO uint32_t MCR;
23138 __IO uint32_t MSR;
23139 __IO uint32_t MIER;
23140 __IO uint32_t MDER;
23141 __IO uint32_t MCFGR0;
23142 __IO uint32_t MCFGR1;
23143 __IO uint32_t MCFGR2;
23144 __IO uint32_t MCFGR3;
23145 uint8_t RESERVED_1[16];
23146 __IO uint32_t MDMR;
23147 uint8_t RESERVED_2[4];
23148 __IO uint32_t MCCR0;
23149 uint8_t RESERVED_3[4];
23150 __IO uint32_t MCCR1;
23151 uint8_t RESERVED_4[4];
23152 __IO uint32_t MFCR;
23153 __I uint32_t MFSR;
23154 __O uint32_t MTDR;
23155 uint8_t RESERVED_5[12];
23156 __I uint32_t MRDR;
23157 uint8_t RESERVED_6[156];
23158 __IO uint32_t SCR;
23159 __IO uint32_t SSR;
23160 __IO uint32_t SIER;
23161 __IO uint32_t SDER;
23162 uint8_t RESERVED_7[4];
23163 __IO uint32_t SCFGR1;
23164 __IO uint32_t SCFGR2;
23165 uint8_t RESERVED_8[20];
23166 __IO uint32_t SAMR;
23167 uint8_t RESERVED_9[12];
23168 __I uint32_t SASR;
23169 __IO uint32_t STAR;
23170 uint8_t RESERVED_10[8];
23171 __O uint32_t STDR;
23172 uint8_t RESERVED_11[12];
23173 __I uint32_t SRDR;
23174} LPI2C_Type;
23175
23176/* ----------------------------------------------------------------------------
23177 -- LPI2C Register Masks
23178 ---------------------------------------------------------------------------- */
23179
23180/*
23181 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
23182 * @{
23183 */
23184
23185/* @name VERID - Version ID Register */
23186/* @{ */
23187#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
23188#define LPI2C_VERID_FEATURE_SHIFT (0U)
23189/* FEATURE - Feature Specification Number
23190 * 0b0000000000000010..Master only, with standard feature set
23191 * 0b0000000000000011..Master and slave, with standard feature set
23192 */
23193#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
23194#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
23195#define LPI2C_VERID_MINOR_SHIFT (16U)
23196#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
23197#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
23198#define LPI2C_VERID_MAJOR_SHIFT (24U)
23199#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
23200/* @} */
23201
23202/* @name PARAM - Parameter Register */
23203/* @{ */
23204#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
23205#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
23206#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
23207#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
23208#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
23209#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
23210/* @} */
23211
23212/* @name MCR - Master Control Register */
23213/* @{ */
23214#define LPI2C_MCR_MEN_MASK (0x1U)
23215#define LPI2C_MCR_MEN_SHIFT (0U)
23216/* MEN - Master Enable
23217 * 0b0..Master logic is disabled
23218 * 0b1..Master logic is enabled
23219 */
23220#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
23221#define LPI2C_MCR_RST_MASK (0x2U)
23222#define LPI2C_MCR_RST_SHIFT (1U)
23223/* RST - Software Reset
23224 * 0b0..Master logic is not reset
23225 * 0b1..Master logic is reset
23226 */
23227#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
23228#define LPI2C_MCR_DOZEN_MASK (0x4U)
23229#define LPI2C_MCR_DOZEN_SHIFT (2U)
23230/* DOZEN - Doze mode enable
23231 * 0b0..Master is enabled in Doze mode
23232 * 0b1..Master is disabled in Doze mode
23233 */
23234#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
23235#define LPI2C_MCR_DBGEN_MASK (0x8U)
23236#define LPI2C_MCR_DBGEN_SHIFT (3U)
23237/* DBGEN - Debug Enable
23238 * 0b0..Master is disabled in debug mode
23239 * 0b1..Master is enabled in debug mode
23240 */
23241#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
23242#define LPI2C_MCR_RTF_MASK (0x100U)
23243#define LPI2C_MCR_RTF_SHIFT (8U)
23244/* RTF - Reset Transmit FIFO
23245 * 0b0..No effect
23246 * 0b1..Transmit FIFO is reset
23247 */
23248#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
23249#define LPI2C_MCR_RRF_MASK (0x200U)
23250#define LPI2C_MCR_RRF_SHIFT (9U)
23251/* RRF - Reset Receive FIFO
23252 * 0b0..No effect
23253 * 0b1..Receive FIFO is reset
23254 */
23255#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
23256/* @} */
23257
23258/* @name MSR - Master Status Register */
23259/* @{ */
23260#define LPI2C_MSR_TDF_MASK (0x1U)
23261#define LPI2C_MSR_TDF_SHIFT (0U)
23262/* TDF - Transmit Data Flag
23263 * 0b0..Transmit data is not requested
23264 * 0b1..Transmit data is requested
23265 */
23266#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
23267#define LPI2C_MSR_RDF_MASK (0x2U)
23268#define LPI2C_MSR_RDF_SHIFT (1U)
23269/* RDF - Receive Data Flag
23270 * 0b0..Receive Data is not ready
23271 * 0b1..Receive data is ready
23272 */
23273#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
23274#define LPI2C_MSR_EPF_MASK (0x100U)
23275#define LPI2C_MSR_EPF_SHIFT (8U)
23276/* EPF - End Packet Flag
23277 * 0b0..Master has not generated a STOP or Repeated START condition
23278 * 0b1..Master has generated a STOP or Repeated START condition
23279 */
23280#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
23281#define LPI2C_MSR_SDF_MASK (0x200U)
23282#define LPI2C_MSR_SDF_SHIFT (9U)
23283/* SDF - STOP Detect Flag
23284 * 0b0..Master has not generated a STOP condition
23285 * 0b1..Master has generated a STOP condition
23286 */
23287#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
23288#define LPI2C_MSR_NDF_MASK (0x400U)
23289#define LPI2C_MSR_NDF_SHIFT (10U)
23290/* NDF - NACK Detect Flag
23291 * 0b0..Unexpected NACK was not detected
23292 * 0b1..Unexpected NACK was detected
23293 */
23294#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
23295#define LPI2C_MSR_ALF_MASK (0x800U)
23296#define LPI2C_MSR_ALF_SHIFT (11U)
23297/* ALF - Arbitration Lost Flag
23298 * 0b0..Master has not lost arbitration
23299 * 0b1..Master has lost arbitration
23300 */
23301#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
23302#define LPI2C_MSR_FEF_MASK (0x1000U)
23303#define LPI2C_MSR_FEF_SHIFT (12U)
23304/* FEF - FIFO Error Flag
23305 * 0b0..No error
23306 * 0b1..Master sending or receiving data without a START condition
23307 */
23308#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
23309#define LPI2C_MSR_PLTF_MASK (0x2000U)
23310#define LPI2C_MSR_PLTF_SHIFT (13U)
23311/* PLTF - Pin Low Timeout Flag
23312 * 0b0..Pin low timeout has not occurred or is disabled
23313 * 0b1..Pin low timeout has occurred
23314 */
23315#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
23316#define LPI2C_MSR_DMF_MASK (0x4000U)
23317#define LPI2C_MSR_DMF_SHIFT (14U)
23318/* DMF - Data Match Flag
23319 * 0b0..Have not received matching data
23320 * 0b1..Have received matching data
23321 */
23322#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
23323#define LPI2C_MSR_MBF_MASK (0x1000000U)
23324#define LPI2C_MSR_MBF_SHIFT (24U)
23325/* MBF - Master Busy Flag
23326 * 0b0..I2C Master is idle
23327 * 0b1..I2C Master is busy
23328 */
23329#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
23330#define LPI2C_MSR_BBF_MASK (0x2000000U)
23331#define LPI2C_MSR_BBF_SHIFT (25U)
23332/* BBF - Bus Busy Flag
23333 * 0b0..I2C Bus is idle
23334 * 0b1..I2C Bus is busy
23335 */
23336#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
23337/* @} */
23338
23339/* @name MIER - Master Interrupt Enable Register */
23340/* @{ */
23341#define LPI2C_MIER_TDIE_MASK (0x1U)
23342#define LPI2C_MIER_TDIE_SHIFT (0U)
23343/* TDIE - Transmit Data Interrupt Enable
23344 * 0b0..Disabled
23345 * 0b1..Enabled
23346 */
23347#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
23348#define LPI2C_MIER_RDIE_MASK (0x2U)
23349#define LPI2C_MIER_RDIE_SHIFT (1U)
23350/* RDIE - Receive Data Interrupt Enable
23351 * 0b0..Disabled
23352 * 0b1..Enabled
23353 */
23354#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
23355#define LPI2C_MIER_EPIE_MASK (0x100U)
23356#define LPI2C_MIER_EPIE_SHIFT (8U)
23357/* EPIE - End Packet Interrupt Enable
23358 * 0b0..Disabled
23359 * 0b1..Enabled
23360 */
23361#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
23362#define LPI2C_MIER_SDIE_MASK (0x200U)
23363#define LPI2C_MIER_SDIE_SHIFT (9U)
23364/* SDIE - STOP Detect Interrupt Enable
23365 * 0b0..Disabled
23366 * 0b1..Enabled
23367 */
23368#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
23369#define LPI2C_MIER_NDIE_MASK (0x400U)
23370#define LPI2C_MIER_NDIE_SHIFT (10U)
23371/* NDIE - NACK Detect Interrupt Enable
23372 * 0b0..Disabled
23373 * 0b1..Enabled
23374 */
23375#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
23376#define LPI2C_MIER_ALIE_MASK (0x800U)
23377#define LPI2C_MIER_ALIE_SHIFT (11U)
23378/* ALIE - Arbitration Lost Interrupt Enable
23379 * 0b0..Disabled
23380 * 0b1..Enabled
23381 */
23382#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
23383#define LPI2C_MIER_FEIE_MASK (0x1000U)
23384#define LPI2C_MIER_FEIE_SHIFT (12U)
23385/* FEIE - FIFO Error Interrupt Enable
23386 * 0b0..Enabled
23387 * 0b1..Disabled
23388 */
23389#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
23390#define LPI2C_MIER_PLTIE_MASK (0x2000U)
23391#define LPI2C_MIER_PLTIE_SHIFT (13U)
23392/* PLTIE - Pin Low Timeout Interrupt Enable
23393 * 0b0..Disabled
23394 * 0b1..Enabled
23395 */
23396#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
23397#define LPI2C_MIER_DMIE_MASK (0x4000U)
23398#define LPI2C_MIER_DMIE_SHIFT (14U)
23399/* DMIE - Data Match Interrupt Enable
23400 * 0b0..Disabled
23401 * 0b1..Enabled
23402 */
23403#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
23404/* @} */
23405
23406/* @name MDER - Master DMA Enable Register */
23407/* @{ */
23408#define LPI2C_MDER_TDDE_MASK (0x1U)
23409#define LPI2C_MDER_TDDE_SHIFT (0U)
23410/* TDDE - Transmit Data DMA Enable
23411 * 0b0..DMA request is disabled
23412 * 0b1..DMA request is enabled
23413 */
23414#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
23415#define LPI2C_MDER_RDDE_MASK (0x2U)
23416#define LPI2C_MDER_RDDE_SHIFT (1U)
23417/* RDDE - Receive Data DMA Enable
23418 * 0b0..DMA request is disabled
23419 * 0b1..DMA request is enabled
23420 */
23421#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
23422/* @} */
23423
23424/* @name MCFGR0 - Master Configuration Register 0 */
23425/* @{ */
23426#define LPI2C_MCFGR0_HREN_MASK (0x1U)
23427#define LPI2C_MCFGR0_HREN_SHIFT (0U)
23428/* HREN - Host Request Enable
23429 * 0b0..Host request input is disabled
23430 * 0b1..Host request input is enabled
23431 */
23432#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
23433#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
23434#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
23435/* HRPOL - Host Request Polarity
23436 * 0b0..Active low
23437 * 0b1..Active high
23438 */
23439#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
23440#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
23441#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
23442/* HRSEL - Host Request Select
23443 * 0b0..Host request input is pin HREQ
23444 * 0b1..Host request input is input trigger
23445 */
23446#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
23447#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
23448#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
23449/* CIRFIFO - Circular FIFO Enable
23450 * 0b0..Circular FIFO is disabled
23451 * 0b1..Circular FIFO is enabled
23452 */
23453#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
23454#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
23455#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
23456/* RDMO - Receive Data Match Only
23457 * 0b0..Received data is stored in the receive FIFO
23458 * 0b1..Received data is discarded unless the Data Match Flag (MSR[DMF]) is set
23459 */
23460#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
23461/* @} */
23462
23463/* @name MCFGR1 - Master Configuration Register 1 */
23464/* @{ */
23465#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
23466#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
23467/* PRESCALE - Prescaler
23468 * 0b000..Divide by 1
23469 * 0b001..Divide by 2
23470 * 0b010..Divide by 4
23471 * 0b011..Divide by 8
23472 * 0b100..Divide by 16
23473 * 0b101..Divide by 32
23474 * 0b110..Divide by 64
23475 * 0b111..Divide by 128
23476 */
23477#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
23478#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
23479#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
23480/* AUTOSTOP - Automatic STOP Generation
23481 * 0b0..No effect
23482 * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
23483 */
23484#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
23485#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
23486#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
23487/* IGNACK - IGNACK
23488 * 0b0..LPI2C Master will receive ACK and NACK normally
23489 * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK
23490 */
23491#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
23492#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
23493#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
23494/* TIMECFG - Timeout Configuration
23495 * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout
23496 * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout
23497 */
23498#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
23499#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
23500#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
23501/* MATCFG - Match Configuration
23502 * 0b000..Match is disabled
23503 * 0b001..Reserved
23504 * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1)
23505 * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1)
23506 * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1)
23507 * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1)
23508 * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)
23509 * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1)
23510 */
23511#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
23512#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
23513#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
23514/* PINCFG - Pin Configuration
23515 * 0b000..2-pin open drain mode
23516 * 0b001..2-pin output only mode (ultra-fast mode)
23517 * 0b010..2-pin push-pull mode
23518 * 0b011..4-pin push-pull mode
23519 * 0b100..2-pin open drain mode with separate LPI2C slave
23520 * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
23521 * 0b110..2-pin push-pull mode with separate LPI2C slave
23522 * 0b111..4-pin push-pull mode (inverted outputs)
23523 */
23524#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
23525/* @} */
23526
23527/* @name MCFGR2 - Master Configuration Register 2 */
23528/* @{ */
23529#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
23530#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
23531#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
23532#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
23533#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
23534#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
23535#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
23536#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
23537#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
23538/* @} */
23539
23540/* @name MCFGR3 - Master Configuration Register 3 */
23541/* @{ */
23542#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
23543#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
23544#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
23545/* @} */
23546
23547/* @name MDMR - Master Data Match Register */
23548/* @{ */
23549#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
23550#define LPI2C_MDMR_MATCH0_SHIFT (0U)
23551#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
23552#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
23553#define LPI2C_MDMR_MATCH1_SHIFT (16U)
23554#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
23555/* @} */
23556
23557/* @name MCCR0 - Master Clock Configuration Register 0 */
23558/* @{ */
23559#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
23560#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
23561#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
23562#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
23563#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
23564#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
23565#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
23566#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
23567#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
23568#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
23569#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
23570#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
23571/* @} */
23572
23573/* @name MCCR1 - Master Clock Configuration Register 1 */
23574/* @{ */
23575#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
23576#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
23577#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
23578#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
23579#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
23580#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
23581#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
23582#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
23583#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
23584#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
23585#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
23586#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
23587/* @} */
23588
23589/* @name MFCR - Master FIFO Control Register */
23590/* @{ */
23591#define LPI2C_MFCR_TXWATER_MASK (0x3U)
23592#define LPI2C_MFCR_TXWATER_SHIFT (0U)
23593#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
23594#define LPI2C_MFCR_RXWATER_MASK (0x30000U)
23595#define LPI2C_MFCR_RXWATER_SHIFT (16U)
23596#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
23597/* @} */
23598
23599/* @name MFSR - Master FIFO Status Register */
23600/* @{ */
23601#define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
23602#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
23603#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
23604#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
23605#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
23606#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
23607/* @} */
23608
23609/* @name MTDR - Master Transmit Data Register */
23610/* @{ */
23611#define LPI2C_MTDR_DATA_MASK (0xFFU)
23612#define LPI2C_MTDR_DATA_SHIFT (0U)
23613#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
23614#define LPI2C_MTDR_CMD_MASK (0x700U)
23615#define LPI2C_MTDR_CMD_SHIFT (8U)
23616/* CMD - Command Data
23617 * 0b000..Transmit DATA[7:0]
23618 * 0b001..Receive (DATA[7:0] + 1) bytes
23619 * 0b010..Generate STOP condition
23620 * 0b011..Receive and discard (DATA[7:0] + 1) bytes
23621 * 0b100..Generate (repeated) START and transmit address in DATA[7:0]
23622 * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
23623 * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
23624 * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
23625 */
23626#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
23627/* @} */
23628
23629/* @name MRDR - Master Receive Data Register */
23630/* @{ */
23631#define LPI2C_MRDR_DATA_MASK (0xFFU)
23632#define LPI2C_MRDR_DATA_SHIFT (0U)
23633#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
23634#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
23635#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
23636/* RXEMPTY - RX Empty
23637 * 0b0..Receive FIFO is not empty
23638 * 0b1..Receive FIFO is empty
23639 */
23640#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
23641/* @} */
23642
23643/* @name SCR - Slave Control Register */
23644/* @{ */
23645#define LPI2C_SCR_SEN_MASK (0x1U)
23646#define LPI2C_SCR_SEN_SHIFT (0U)
23647/* SEN - Slave Enable
23648 * 0b0..I2C Slave mode is disabled
23649 * 0b1..I2C Slave mode is enabled
23650 */
23651#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
23652#define LPI2C_SCR_RST_MASK (0x2U)
23653#define LPI2C_SCR_RST_SHIFT (1U)
23654/* RST - Software Reset
23655 * 0b0..Slave mode logic is not reset
23656 * 0b1..Slave mode logic is reset
23657 */
23658#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
23659#define LPI2C_SCR_FILTEN_MASK (0x10U)
23660#define LPI2C_SCR_FILTEN_SHIFT (4U)
23661/* FILTEN - Filter Enable
23662 * 0b0..Disable digital filter and output delay counter for slave mode
23663 * 0b1..Enable digital filter and output delay counter for slave mode
23664 */
23665#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
23666#define LPI2C_SCR_FILTDZ_MASK (0x20U)
23667#define LPI2C_SCR_FILTDZ_SHIFT (5U)
23668/* FILTDZ - Filter Doze Enable
23669 * 0b0..Filter remains enabled in Doze mode
23670 * 0b1..Filter is disabled in Doze mode
23671 */
23672#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
23673#define LPI2C_SCR_RTF_MASK (0x100U)
23674#define LPI2C_SCR_RTF_SHIFT (8U)
23675/* RTF - Reset Transmit FIFO
23676 * 0b0..No effect
23677 * 0b1..Transmit Data Register is now empty
23678 */
23679#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
23680#define LPI2C_SCR_RRF_MASK (0x200U)
23681#define LPI2C_SCR_RRF_SHIFT (9U)
23682/* RRF - Reset Receive FIFO
23683 * 0b0..No effect
23684 * 0b1..Receive Data Register is now empty
23685 */
23686#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
23687/* @} */
23688
23689/* @name SSR - Slave Status Register */
23690/* @{ */
23691#define LPI2C_SSR_TDF_MASK (0x1U)
23692#define LPI2C_SSR_TDF_SHIFT (0U)
23693/* TDF - Transmit Data Flag
23694 * 0b0..Transmit data not requested
23695 * 0b1..Transmit data is requested
23696 */
23697#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
23698#define LPI2C_SSR_RDF_MASK (0x2U)
23699#define LPI2C_SSR_RDF_SHIFT (1U)
23700/* RDF - Receive Data Flag
23701 * 0b0..Receive data is not ready
23702 * 0b1..Receive data is ready
23703 */
23704#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
23705#define LPI2C_SSR_AVF_MASK (0x4U)
23706#define LPI2C_SSR_AVF_SHIFT (2U)
23707/* AVF - Address Valid Flag
23708 * 0b0..Address Status Register is not valid
23709 * 0b1..Address Status Register is valid
23710 */
23711#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
23712#define LPI2C_SSR_TAF_MASK (0x8U)
23713#define LPI2C_SSR_TAF_SHIFT (3U)
23714/* TAF - Transmit ACK Flag
23715 * 0b0..Transmit ACK/NACK is not required
23716 * 0b1..Transmit ACK/NACK is required
23717 */
23718#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
23719#define LPI2C_SSR_RSF_MASK (0x100U)
23720#define LPI2C_SSR_RSF_SHIFT (8U)
23721/* RSF - Repeated Start Flag
23722 * 0b0..Slave has not detected a Repeated START condition
23723 * 0b1..Slave has detected a Repeated START condition
23724 */
23725#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
23726#define LPI2C_SSR_SDF_MASK (0x200U)
23727#define LPI2C_SSR_SDF_SHIFT (9U)
23728/* SDF - STOP Detect Flag
23729 * 0b0..Slave has not detected a STOP condition
23730 * 0b1..Slave has detected a STOP condition
23731 */
23732#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
23733#define LPI2C_SSR_BEF_MASK (0x400U)
23734#define LPI2C_SSR_BEF_SHIFT (10U)
23735/* BEF - Bit Error Flag
23736 * 0b0..Slave has not detected a bit error
23737 * 0b1..Slave has detected a bit error
23738 */
23739#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
23740#define LPI2C_SSR_FEF_MASK (0x800U)
23741#define LPI2C_SSR_FEF_SHIFT (11U)
23742/* FEF - FIFO Error Flag
23743 * 0b0..FIFO underflow or overflow was not detected
23744 * 0b1..FIFO underflow or overflow was detected
23745 */
23746#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
23747#define LPI2C_SSR_AM0F_MASK (0x1000U)
23748#define LPI2C_SSR_AM0F_SHIFT (12U)
23749/* AM0F - Address Match 0 Flag
23750 * 0b0..Have not received an ADDR0 matching address
23751 * 0b1..Have received an ADDR0 matching address
23752 */
23753#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
23754#define LPI2C_SSR_AM1F_MASK (0x2000U)
23755#define LPI2C_SSR_AM1F_SHIFT (13U)
23756/* AM1F - Address Match 1 Flag
23757 * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
23758 * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
23759 */
23760#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
23761#define LPI2C_SSR_GCF_MASK (0x4000U)
23762#define LPI2C_SSR_GCF_SHIFT (14U)
23763/* GCF - General Call Flag
23764 * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled
23765 * 0b1..Slave has detected the General Call Address
23766 */
23767#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
23768#define LPI2C_SSR_SARF_MASK (0x8000U)
23769#define LPI2C_SSR_SARF_SHIFT (15U)
23770/* SARF - SMBus Alert Response Flag
23771 * 0b0..SMBus Alert Response is disabled or not detected
23772 * 0b1..SMBus Alert Response is enabled and detected
23773 */
23774#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
23775#define LPI2C_SSR_SBF_MASK (0x1000000U)
23776#define LPI2C_SSR_SBF_SHIFT (24U)
23777/* SBF - Slave Busy Flag
23778 * 0b0..I2C Slave is idle
23779 * 0b1..I2C Slave is busy
23780 */
23781#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
23782#define LPI2C_SSR_BBF_MASK (0x2000000U)
23783#define LPI2C_SSR_BBF_SHIFT (25U)
23784/* BBF - Bus Busy Flag
23785 * 0b0..I2C Bus is idle
23786 * 0b1..I2C Bus is busy
23787 */
23788#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
23789/* @} */
23790
23791/* @name SIER - Slave Interrupt Enable Register */
23792/* @{ */
23793#define LPI2C_SIER_TDIE_MASK (0x1U)
23794#define LPI2C_SIER_TDIE_SHIFT (0U)
23795/* TDIE - Transmit Data Interrupt Enable
23796 * 0b0..Disabled
23797 * 0b1..Enabled
23798 */
23799#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
23800#define LPI2C_SIER_RDIE_MASK (0x2U)
23801#define LPI2C_SIER_RDIE_SHIFT (1U)
23802/* RDIE - Receive Data Interrupt Enable
23803 * 0b0..Disabled
23804 * 0b1..Enabled
23805 */
23806#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
23807#define LPI2C_SIER_AVIE_MASK (0x4U)
23808#define LPI2C_SIER_AVIE_SHIFT (2U)
23809/* AVIE - Address Valid Interrupt Enable
23810 * 0b0..Disabled
23811 * 0b1..Enabled
23812 */
23813#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
23814#define LPI2C_SIER_TAIE_MASK (0x8U)
23815#define LPI2C_SIER_TAIE_SHIFT (3U)
23816/* TAIE - Transmit ACK Interrupt Enable
23817 * 0b0..Disabled
23818 * 0b1..Enabled
23819 */
23820#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
23821#define LPI2C_SIER_RSIE_MASK (0x100U)
23822#define LPI2C_SIER_RSIE_SHIFT (8U)
23823/* RSIE - Repeated Start Interrupt Enable
23824 * 0b0..Disabled
23825 * 0b1..Enabled
23826 */
23827#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
23828#define LPI2C_SIER_SDIE_MASK (0x200U)
23829#define LPI2C_SIER_SDIE_SHIFT (9U)
23830/* SDIE - STOP Detect Interrupt Enable
23831 * 0b0..Disabled
23832 * 0b1..Enabled
23833 */
23834#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
23835#define LPI2C_SIER_BEIE_MASK (0x400U)
23836#define LPI2C_SIER_BEIE_SHIFT (10U)
23837/* BEIE - Bit Error Interrupt Enable
23838 * 0b0..Disabled
23839 * 0b1..Enabled
23840 */
23841#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
23842#define LPI2C_SIER_FEIE_MASK (0x800U)
23843#define LPI2C_SIER_FEIE_SHIFT (11U)
23844/* FEIE - FIFO Error Interrupt Enable
23845 * 0b0..Disabled
23846 * 0b1..Enabled
23847 */
23848#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
23849#define LPI2C_SIER_AM0IE_MASK (0x1000U)
23850#define LPI2C_SIER_AM0IE_SHIFT (12U)
23851/* AM0IE - Address Match 0 Interrupt Enable
23852 * 0b0..Enabled
23853 * 0b1..Disabled
23854 */
23855#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
23856#define LPI2C_SIER_AM1F_MASK (0x2000U)
23857#define LPI2C_SIER_AM1F_SHIFT (13U)
23858/* AM1F - Address Match 1 Interrupt Enable
23859 * 0b0..Disabled
23860 * 0b1..Enabled
23861 */
23862#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
23863#define LPI2C_SIER_GCIE_MASK (0x4000U)
23864#define LPI2C_SIER_GCIE_SHIFT (14U)
23865/* GCIE - General Call Interrupt Enable
23866 * 0b0..Disabled
23867 * 0b1..Enabled
23868 */
23869#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
23870#define LPI2C_SIER_SARIE_MASK (0x8000U)
23871#define LPI2C_SIER_SARIE_SHIFT (15U)
23872/* SARIE - SMBus Alert Response Interrupt Enable
23873 * 0b0..Disabled
23874 * 0b1..Enabled
23875 */
23876#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
23877/* @} */
23878
23879/* @name SDER - Slave DMA Enable Register */
23880/* @{ */
23881#define LPI2C_SDER_TDDE_MASK (0x1U)
23882#define LPI2C_SDER_TDDE_SHIFT (0U)
23883/* TDDE - Transmit Data DMA Enable
23884 * 0b0..DMA request is disabled
23885 * 0b1..DMA request is enabled
23886 */
23887#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
23888#define LPI2C_SDER_RDDE_MASK (0x2U)
23889#define LPI2C_SDER_RDDE_SHIFT (1U)
23890/* RDDE - Receive Data DMA Enable
23891 * 0b0..DMA request is disabled
23892 * 0b1..DMA request is enabled
23893 */
23894#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
23895#define LPI2C_SDER_AVDE_MASK (0x4U)
23896#define LPI2C_SDER_AVDE_SHIFT (2U)
23897/* AVDE - Address Valid DMA Enable
23898 * 0b0..DMA request is disabled
23899 * 0b1..DMA request is enabled
23900 */
23901#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
23902/* @} */
23903
23904/* @name SCFGR1 - Slave Configuration Register 1 */
23905/* @{ */
23906#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
23907#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
23908/* ADRSTALL - Address SCL Stall
23909 * 0b0..Clock stretching is disabled
23910 * 0b1..Clock stretching is enabled
23911 */
23912#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
23913#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
23914#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
23915/* RXSTALL - RX SCL Stall
23916 * 0b0..Clock stretching is disabled
23917 * 0b1..Clock stretching is enabled
23918 */
23919#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
23920#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
23921#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
23922/* TXDSTALL - TX Data SCL Stall
23923 * 0b0..Clock stretching is disabled
23924 * 0b1..Clock stretching is enabled
23925 */
23926#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
23927#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
23928#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
23929/* ACKSTALL - ACK SCL Stall
23930 * 0b0..Clock stretching is disabled
23931 * 0b1..Clock stretching is enabled
23932 */
23933#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
23934#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
23935#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
23936/* GCEN - General Call Enable
23937 * 0b0..General Call address is disabled
23938 * 0b1..General Call address is enabled
23939 */
23940#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
23941#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
23942#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
23943/* SAEN - SMBus Alert Enable
23944 * 0b0..Disables match on SMBus Alert
23945 * 0b1..Enables match on SMBus Alert
23946 */
23947#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
23948#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
23949#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
23950/* TXCFG - Transmit Flag Configuration
23951 * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty
23952 * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty
23953 */
23954#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
23955#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
23956#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
23957/* RXCFG - Receive Data Configuration
23958 * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]).
23959 * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address
23960 * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid
23961 * flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]).
23962 */
23963#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
23964#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
23965#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
23966/* IGNACK - Ignore NACK
23967 * 0b0..Slave will end transfer when NACK is detected
23968 * 0b1..Slave will not end transfer when NACK detected
23969 */
23970#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
23971#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
23972#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
23973/* HSMEN - High Speed Mode Enable
23974 * 0b0..Disables detection of HS-mode master code
23975 * 0b1..Enables detection of HS-mode master code
23976 */
23977#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
23978#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
23979#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
23980/* ADDRCFG - Address Configuration
23981 * 0b000..Address match 0 (7-bit)
23982 * 0b001..Address match 0 (10-bit)
23983 * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
23984 * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
23985 * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
23986 * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
23987 * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
23988 * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
23989 */
23990#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
23991/* @} */
23992
23993/* @name SCFGR2 - Slave Configuration Register 2 */
23994/* @{ */
23995#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
23996#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
23997#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
23998#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
23999#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
24000#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
24001#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
24002#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
24003#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
24004#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
24005#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
24006#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
24007/* @} */
24008
24009/* @name SAMR - Slave Address Match Register */
24010/* @{ */
24011#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
24012#define LPI2C_SAMR_ADDR0_SHIFT (1U)
24013#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
24014#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
24015#define LPI2C_SAMR_ADDR1_SHIFT (17U)
24016#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
24017/* @} */
24018
24019/* @name SASR - Slave Address Status Register */
24020/* @{ */
24021#define LPI2C_SASR_RADDR_MASK (0x7FFU)
24022#define LPI2C_SASR_RADDR_SHIFT (0U)
24023#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
24024#define LPI2C_SASR_ANV_MASK (0x4000U)
24025#define LPI2C_SASR_ANV_SHIFT (14U)
24026/* ANV - Address Not Valid
24027 * 0b0..Received Address (RADDR) is valid
24028 * 0b1..Received Address (RADDR) is not valid
24029 */
24030#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
24031/* @} */
24032
24033/* @name STAR - Slave Transmit ACK Register */
24034/* @{ */
24035#define LPI2C_STAR_TXNACK_MASK (0x1U)
24036#define LPI2C_STAR_TXNACK_SHIFT (0U)
24037/* TXNACK - Transmit NACK
24038 * 0b0..Write a Transmit ACK for each received word
24039 * 0b1..Write a Transmit NACK for each received word
24040 */
24041#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
24042/* @} */
24043
24044/* @name STDR - Slave Transmit Data Register */
24045/* @{ */
24046#define LPI2C_STDR_DATA_MASK (0xFFU)
24047#define LPI2C_STDR_DATA_SHIFT (0U)
24048#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
24049/* @} */
24050
24051/* @name SRDR - Slave Receive Data Register */
24052/* @{ */
24053#define LPI2C_SRDR_DATA_MASK (0xFFU)
24054#define LPI2C_SRDR_DATA_SHIFT (0U)
24055#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
24056#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
24057#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
24058/* RXEMPTY - RX Empty
24059 * 0b0..The Receive Data Register is not empty
24060 * 0b1..The Receive Data Register is empty
24061 */
24062#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
24063#define LPI2C_SRDR_SOF_MASK (0x8000U)
24064#define LPI2C_SRDR_SOF_SHIFT (15U)
24065/* SOF - Start Of Frame
24066 * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
24067 * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition
24068 */
24069#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
24070/* @} */
24071
24072
24073/*
24074 * @}
24075 */ /* end of group LPI2C_Register_Masks */
24076
24077
24078/* LPI2C - Peripheral instance base addresses */
24079/* Peripheral LPI2C1 base address */
24080#define LPI2C1_BASE (0x403F0000u)
24081/* Peripheral LPI2C1 base pointer */
24082#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
24083/* Peripheral LPI2C2 base address */
24084#define LPI2C2_BASE (0x403F4000u)
24085/* Peripheral LPI2C2 base pointer */
24086#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
24087/* Peripheral LPI2C3 base address */
24088#define LPI2C3_BASE (0x403F8000u)
24089/* Peripheral LPI2C3 base pointer */
24090#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
24091/* Peripheral LPI2C4 base address */
24092#define LPI2C4_BASE (0x403FC000u)
24093/* Peripheral LPI2C4 base pointer */
24094#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
24095/* Array initializer of LPI2C peripheral base addresses */
24096#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE }
24097/* Array initializer of LPI2C peripheral base pointers */
24098#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 }
24099/* Interrupt vectors for the LPI2C peripheral type */
24100#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn }
24101
24102/*
24103 * @}
24104 */ /* end of group LPI2C_Peripheral_Access_Layer */
24105
24106
24107/* ----------------------------------------------------------------------------
24108 -- LPSPI Peripheral Access Layer
24109 ---------------------------------------------------------------------------- */
24110
24111/*
24112 * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
24113 * @{
24114 */
24115
24116/* LPSPI - Register Layout Typedef */
24117typedef struct {
24118 __I uint32_t VERID;
24119 __I uint32_t PARAM;
24120 uint8_t RESERVED_0[8];
24121 __IO uint32_t CR;
24122 __IO uint32_t SR;
24123 __IO uint32_t IER;
24124 __IO uint32_t DER;
24125 __IO uint32_t CFGR0;
24126 __IO uint32_t CFGR1;
24127 uint8_t RESERVED_1[8];
24128 __IO uint32_t DMR0;
24129 __IO uint32_t DMR1;
24130 uint8_t RESERVED_2[8];
24131 __IO uint32_t CCR;
24132 uint8_t RESERVED_3[20];
24133 __IO uint32_t FCR;
24134 __I uint32_t FSR;
24135 __IO uint32_t TCR;
24136 __O uint32_t TDR;
24137 uint8_t RESERVED_4[8];
24138 __I uint32_t RSR;
24139 __I uint32_t RDR;
24140} LPSPI_Type;
24141
24142/* ----------------------------------------------------------------------------
24143 -- LPSPI Register Masks
24144 ---------------------------------------------------------------------------- */
24145
24146/*
24147 * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
24148 * @{
24149 */
24150
24151/* @name VERID - Version ID Register */
24152/* @{ */
24153#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
24154#define LPSPI_VERID_FEATURE_SHIFT (0U)
24155/* FEATURE - Module Identification Number
24156 * 0b0000000000000100..Standard feature set supporting a 32-bit shift register.
24157 */
24158#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
24159#define LPSPI_VERID_MINOR_MASK (0xFF0000U)
24160#define LPSPI_VERID_MINOR_SHIFT (16U)
24161#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
24162#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
24163#define LPSPI_VERID_MAJOR_SHIFT (24U)
24164#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
24165/* @} */
24166
24167/* @name PARAM - Parameter Register */
24168/* @{ */
24169#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
24170#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
24171#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
24172#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
24173#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
24174#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
24175#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
24176#define LPSPI_PARAM_PCSNUM_SHIFT (16U)
24177#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
24178/* @} */
24179
24180/* @name CR - Control Register */
24181/* @{ */
24182#define LPSPI_CR_MEN_MASK (0x1U)
24183#define LPSPI_CR_MEN_SHIFT (0U)
24184/* MEN - Module Enable
24185 * 0b0..Module is disabled
24186 * 0b1..Module is enabled
24187 */
24188#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
24189#define LPSPI_CR_RST_MASK (0x2U)
24190#define LPSPI_CR_RST_SHIFT (1U)
24191/* RST - Software Reset
24192 * 0b0..Module is not reset
24193 * 0b1..Module is reset
24194 */
24195#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
24196#define LPSPI_CR_DOZEN_MASK (0x4U)
24197#define LPSPI_CR_DOZEN_SHIFT (2U)
24198/* DOZEN - Doze mode enable
24199 * 0b0..Module is enabled in Doze mode
24200 * 0b1..Module is disabled in Doze mode
24201 */
24202#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
24203#define LPSPI_CR_DBGEN_MASK (0x8U)
24204#define LPSPI_CR_DBGEN_SHIFT (3U)
24205/* DBGEN - Debug Enable
24206 * 0b0..Module is disabled in debug mode
24207 * 0b1..Module is enabled in debug mode
24208 */
24209#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
24210#define LPSPI_CR_RTF_MASK (0x100U)
24211#define LPSPI_CR_RTF_SHIFT (8U)
24212/* RTF - Reset Transmit FIFO
24213 * 0b0..No effect
24214 * 0b1..Transmit FIFO is reset
24215 */
24216#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
24217#define LPSPI_CR_RRF_MASK (0x200U)
24218#define LPSPI_CR_RRF_SHIFT (9U)
24219/* RRF - Reset Receive FIFO
24220 * 0b0..No effect
24221 * 0b1..Receive FIFO is reset
24222 */
24223#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
24224/* @} */
24225
24226/* @name SR - Status Register */
24227/* @{ */
24228#define LPSPI_SR_TDF_MASK (0x1U)
24229#define LPSPI_SR_TDF_SHIFT (0U)
24230/* TDF - Transmit Data Flag
24231 * 0b0..Transmit data not requested
24232 * 0b1..Transmit data is requested
24233 */
24234#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
24235#define LPSPI_SR_RDF_MASK (0x2U)
24236#define LPSPI_SR_RDF_SHIFT (1U)
24237/* RDF - Receive Data Flag
24238 * 0b0..Receive Data is not ready
24239 * 0b1..Receive data is ready
24240 */
24241#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
24242#define LPSPI_SR_WCF_MASK (0x100U)
24243#define LPSPI_SR_WCF_SHIFT (8U)
24244/* WCF - Word Complete Flag
24245 * 0b0..Transfer of a received word has not yet completed
24246 * 0b1..Transfer of a received word has completed
24247 */
24248#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
24249#define LPSPI_SR_FCF_MASK (0x200U)
24250#define LPSPI_SR_FCF_SHIFT (9U)
24251/* FCF - Frame Complete Flag
24252 * 0b0..Frame transfer has not completed
24253 * 0b1..Frame transfer has completed
24254 */
24255#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
24256#define LPSPI_SR_TCF_MASK (0x400U)
24257#define LPSPI_SR_TCF_SHIFT (10U)
24258/* TCF - Transfer Complete Flag
24259 * 0b0..All transfers have not completed
24260 * 0b1..All transfers have completed
24261 */
24262#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
24263#define LPSPI_SR_TEF_MASK (0x800U)
24264#define LPSPI_SR_TEF_SHIFT (11U)
24265/* TEF - Transmit Error Flag
24266 * 0b0..Transmit FIFO underrun has not occurred
24267 * 0b1..Transmit FIFO underrun has occurred
24268 */
24269#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
24270#define LPSPI_SR_REF_MASK (0x1000U)
24271#define LPSPI_SR_REF_SHIFT (12U)
24272/* REF - Receive Error Flag
24273 * 0b0..Receive FIFO has not overflowed
24274 * 0b1..Receive FIFO has overflowed
24275 */
24276#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
24277#define LPSPI_SR_DMF_MASK (0x2000U)
24278#define LPSPI_SR_DMF_SHIFT (13U)
24279/* DMF - Data Match Flag
24280 * 0b0..Have not received matching data
24281 * 0b1..Have received matching data
24282 */
24283#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
24284#define LPSPI_SR_MBF_MASK (0x1000000U)
24285#define LPSPI_SR_MBF_SHIFT (24U)
24286/* MBF - Module Busy Flag
24287 * 0b0..LPSPI is idle
24288 * 0b1..LPSPI is busy
24289 */
24290#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
24291/* @} */
24292
24293/* @name IER - Interrupt Enable Register */
24294/* @{ */
24295#define LPSPI_IER_TDIE_MASK (0x1U)
24296#define LPSPI_IER_TDIE_SHIFT (0U)
24297/* TDIE - Transmit Data Interrupt Enable
24298 * 0b0..Disabled
24299 * 0b1..Enabled
24300 */
24301#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
24302#define LPSPI_IER_RDIE_MASK (0x2U)
24303#define LPSPI_IER_RDIE_SHIFT (1U)
24304/* RDIE - Receive Data Interrupt Enable
24305 * 0b0..Disabled
24306 * 0b1..Enabled
24307 */
24308#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
24309#define LPSPI_IER_WCIE_MASK (0x100U)
24310#define LPSPI_IER_WCIE_SHIFT (8U)
24311/* WCIE - Word Complete Interrupt Enable
24312 * 0b0..Disabled
24313 * 0b1..Enabled
24314 */
24315#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
24316#define LPSPI_IER_FCIE_MASK (0x200U)
24317#define LPSPI_IER_FCIE_SHIFT (9U)
24318/* FCIE - Frame Complete Interrupt Enable
24319 * 0b0..Disabled
24320 * 0b1..Enabled
24321 */
24322#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
24323#define LPSPI_IER_TCIE_MASK (0x400U)
24324#define LPSPI_IER_TCIE_SHIFT (10U)
24325/* TCIE - Transfer Complete Interrupt Enable
24326 * 0b0..Disabled
24327 * 0b1..Enabled
24328 */
24329#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
24330#define LPSPI_IER_TEIE_MASK (0x800U)
24331#define LPSPI_IER_TEIE_SHIFT (11U)
24332/* TEIE - Transmit Error Interrupt Enable
24333 * 0b0..Disabled
24334 * 0b1..Enabled
24335 */
24336#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
24337#define LPSPI_IER_REIE_MASK (0x1000U)
24338#define LPSPI_IER_REIE_SHIFT (12U)
24339/* REIE - Receive Error Interrupt Enable
24340 * 0b0..Disabled
24341 * 0b1..Enabled
24342 */
24343#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
24344#define LPSPI_IER_DMIE_MASK (0x2000U)
24345#define LPSPI_IER_DMIE_SHIFT (13U)
24346/* DMIE - Data Match Interrupt Enable
24347 * 0b0..Disabled
24348 * 0b1..Enabled
24349 */
24350#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
24351/* @} */
24352
24353/* @name DER - DMA Enable Register */
24354/* @{ */
24355#define LPSPI_DER_TDDE_MASK (0x1U)
24356#define LPSPI_DER_TDDE_SHIFT (0U)
24357/* TDDE - Transmit Data DMA Enable
24358 * 0b0..DMA request is disabled
24359 * 0b1..DMA request is enabled
24360 */
24361#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
24362#define LPSPI_DER_RDDE_MASK (0x2U)
24363#define LPSPI_DER_RDDE_SHIFT (1U)
24364/* RDDE - Receive Data DMA Enable
24365 * 0b0..DMA request is disabled
24366 * 0b1..DMA request is enabled
24367 */
24368#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
24369/* @} */
24370
24371/* @name CFGR0 - Configuration Register 0 */
24372/* @{ */
24373#define LPSPI_CFGR0_HREN_MASK (0x1U)
24374#define LPSPI_CFGR0_HREN_SHIFT (0U)
24375/* HREN - Host Request Enable
24376 * 0b0..Host request is disabled
24377 * 0b1..Host request is enabled
24378 */
24379#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
24380#define LPSPI_CFGR0_HRPOL_MASK (0x2U)
24381#define LPSPI_CFGR0_HRPOL_SHIFT (1U)
24382/* HRPOL - Host Request Polarity
24383 * 0b0..Active low
24384 * 0b1..Active high
24385 */
24386#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
24387#define LPSPI_CFGR0_HRSEL_MASK (0x4U)
24388#define LPSPI_CFGR0_HRSEL_SHIFT (2U)
24389/* HRSEL - Host Request Select
24390 * 0b0..Host request input is the LPSPI_HREQ pin
24391 * 0b1..Host request input is the input trigger
24392 */
24393#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
24394#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
24395#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
24396/* CIRFIFO - Circular FIFO Enable
24397 * 0b0..Circular FIFO is disabled
24398 * 0b1..Circular FIFO is enabled
24399 */
24400#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
24401#define LPSPI_CFGR0_RDMO_MASK (0x200U)
24402#define LPSPI_CFGR0_RDMO_SHIFT (9U)
24403/* RDMO - Receive Data Match Only
24404 * 0b0..Received data is stored in the receive FIFO as in normal operations
24405 * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set
24406 */
24407#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
24408/* @} */
24409
24410/* @name CFGR1 - Configuration Register 1 */
24411/* @{ */
24412#define LPSPI_CFGR1_MASTER_MASK (0x1U)
24413#define LPSPI_CFGR1_MASTER_SHIFT (0U)
24414/* MASTER - Master Mode
24415 * 0b0..Slave mode
24416 * 0b1..Master mode
24417 */
24418#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
24419#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
24420#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
24421/* SAMPLE - Sample Point
24422 * 0b0..Input data is sampled on SCK edge
24423 * 0b1..Input data is sampled on delayed SCK edge
24424 */
24425#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
24426#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
24427#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
24428/* AUTOPCS - Automatic PCS
24429 * 0b0..Automatic PCS generation is disabled
24430 * 0b1..Automatic PCS generation is enabled
24431 */
24432#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
24433#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
24434#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
24435/* NOSTALL - No Stall
24436 * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
24437 * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
24438 */
24439#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
24440#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
24441#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
24442/* PCSPOL - Peripheral Chip Select Polarity
24443 * 0b0000..The Peripheral Chip Select pin PCSx is active low
24444 * 0b0001..The Peripheral Chip Select pin PCSx is active high
24445 */
24446#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
24447#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
24448#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
24449/* MATCFG - Match Configuration
24450 * 0b000..Match is disabled
24451 * 0b001..Reserved
24452 * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
24453 * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
24454 * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st
24455 * data word = MATCH0) * (2nd data word = MATCH1)]
24456 * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e.,
24457 * [(any data word = MATCH0) * (next data word = MATCH1)]
24458 * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]
24459 * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
24460 */
24461#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
24462#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
24463#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
24464/* PINCFG - Pin Configuration
24465 * 0b00..SIN is used for input data and SOUT is used for output data
24466 * 0b01..SIN is used for both input and output data
24467 * 0b10..SOUT is used for both input and output data
24468 * 0b11..SOUT is used for input data and SIN is used for output data
24469 */
24470#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
24471#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
24472#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
24473/* OUTCFG - Output Config
24474 * 0b0..Output data retains last value when chip select is negated
24475 * 0b1..Output data is tristated when chip select is negated
24476 */
24477#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
24478#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
24479#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
24480/* PCSCFG - Peripheral Chip Select Configuration
24481 * 0b0..PCS[3:2] are enabled
24482 * 0b1..PCS[3:2] are disabled
24483 */
24484#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
24485/* @} */
24486
24487/* @name DMR0 - Data Match Register 0 */
24488/* @{ */
24489#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
24490#define LPSPI_DMR0_MATCH0_SHIFT (0U)
24491#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
24492/* @} */
24493
24494/* @name DMR1 - Data Match Register 1 */
24495/* @{ */
24496#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
24497#define LPSPI_DMR1_MATCH1_SHIFT (0U)
24498#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
24499/* @} */
24500
24501/* @name CCR - Clock Configuration Register */
24502/* @{ */
24503#define LPSPI_CCR_SCKDIV_MASK (0xFFU)
24504#define LPSPI_CCR_SCKDIV_SHIFT (0U)
24505#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
24506#define LPSPI_CCR_DBT_MASK (0xFF00U)
24507#define LPSPI_CCR_DBT_SHIFT (8U)
24508#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
24509#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
24510#define LPSPI_CCR_PCSSCK_SHIFT (16U)
24511#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
24512#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
24513#define LPSPI_CCR_SCKPCS_SHIFT (24U)
24514#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
24515/* @} */
24516
24517/* @name FCR - FIFO Control Register */
24518/* @{ */
24519#define LPSPI_FCR_TXWATER_MASK (0xFU)
24520#define LPSPI_FCR_TXWATER_SHIFT (0U)
24521#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
24522#define LPSPI_FCR_RXWATER_MASK (0xF0000U)
24523#define LPSPI_FCR_RXWATER_SHIFT (16U)
24524#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
24525/* @} */
24526
24527/* @name FSR - FIFO Status Register */
24528/* @{ */
24529#define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
24530#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
24531#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
24532#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
24533#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
24534#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
24535/* @} */
24536
24537/* @name TCR - Transmit Command Register */
24538/* @{ */
24539#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
24540#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
24541#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
24542#define LPSPI_TCR_WIDTH_MASK (0x30000U)
24543#define LPSPI_TCR_WIDTH_SHIFT (16U)
24544/* WIDTH - Transfer Width
24545 * 0b00..1 bit transfer
24546 * 0b01..2 bit transfer
24547 * 0b10..4 bit transfer
24548 * 0b11..Reserved
24549 */
24550#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
24551#define LPSPI_TCR_TXMSK_MASK (0x40000U)
24552#define LPSPI_TCR_TXMSK_SHIFT (18U)
24553/* TXMSK - Transmit Data Mask
24554 * 0b0..Normal transfer
24555 * 0b1..Mask transmit data
24556 */
24557#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
24558#define LPSPI_TCR_RXMSK_MASK (0x80000U)
24559#define LPSPI_TCR_RXMSK_SHIFT (19U)
24560/* RXMSK - Receive Data Mask
24561 * 0b0..Normal transfer
24562 * 0b1..Receive data is masked
24563 */
24564#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
24565#define LPSPI_TCR_CONTC_MASK (0x100000U)
24566#define LPSPI_TCR_CONTC_SHIFT (20U)
24567/* CONTC - Continuing Command
24568 * 0b0..Command word for start of new transfer
24569 * 0b1..Command word for continuing transfer
24570 */
24571#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
24572#define LPSPI_TCR_CONT_MASK (0x200000U)
24573#define LPSPI_TCR_CONT_SHIFT (21U)
24574/* CONT - Continuous Transfer
24575 * 0b0..Continuous transfer is disabled
24576 * 0b1..Continuous transfer is enabled
24577 */
24578#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
24579#define LPSPI_TCR_BYSW_MASK (0x400000U)
24580#define LPSPI_TCR_BYSW_SHIFT (22U)
24581/* BYSW - Byte Swap
24582 * 0b0..Byte swap is disabled
24583 * 0b1..Byte swap is enabled
24584 */
24585#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
24586#define LPSPI_TCR_LSBF_MASK (0x800000U)
24587#define LPSPI_TCR_LSBF_SHIFT (23U)
24588/* LSBF - LSB First
24589 * 0b0..Data is transferred MSB first
24590 * 0b1..Data is transferred LSB first
24591 */
24592#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
24593#define LPSPI_TCR_PCS_MASK (0x3000000U)
24594#define LPSPI_TCR_PCS_SHIFT (24U)
24595/* PCS - Peripheral Chip Select
24596 * 0b00..Transfer using LPSPI_PCS[0]
24597 * 0b01..Transfer using LPSPI_PCS[1]
24598 * 0b10..Transfer using LPSPI_PCS[2]
24599 * 0b11..Transfer using LPSPI_PCS[3]
24600 */
24601#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
24602#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
24603#define LPSPI_TCR_PRESCALE_SHIFT (27U)
24604/* PRESCALE - Prescaler Value
24605 * 0b000..Divide by 1
24606 * 0b001..Divide by 2
24607 * 0b010..Divide by 4
24608 * 0b011..Divide by 8
24609 * 0b100..Divide by 16
24610 * 0b101..Divide by 32
24611 * 0b110..Divide by 64
24612 * 0b111..Divide by 128
24613 */
24614#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
24615#define LPSPI_TCR_CPHA_MASK (0x40000000U)
24616#define LPSPI_TCR_CPHA_SHIFT (30U)
24617/* CPHA - Clock Phase
24618 * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
24619 * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
24620 */
24621#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
24622#define LPSPI_TCR_CPOL_MASK (0x80000000U)
24623#define LPSPI_TCR_CPOL_SHIFT (31U)
24624/* CPOL - Clock Polarity
24625 * 0b0..The inactive state value of SCK is low
24626 * 0b1..The inactive state value of SCK is high
24627 */
24628#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
24629/* @} */
24630
24631/* @name TDR - Transmit Data Register */
24632/* @{ */
24633#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
24634#define LPSPI_TDR_DATA_SHIFT (0U)
24635#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
24636/* @} */
24637
24638/* @name RSR - Receive Status Register */
24639/* @{ */
24640#define LPSPI_RSR_SOF_MASK (0x1U)
24641#define LPSPI_RSR_SOF_SHIFT (0U)
24642/* SOF - Start Of Frame
24643 * 0b0..Subsequent data word received after LPSPI_PCS assertion
24644 * 0b1..First data word received after LPSPI_PCS assertion
24645 */
24646#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
24647#define LPSPI_RSR_RXEMPTY_MASK (0x2U)
24648#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
24649/* RXEMPTY - RX FIFO Empty
24650 * 0b0..RX FIFO is not empty
24651 * 0b1..RX FIFO is empty
24652 */
24653#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
24654/* @} */
24655
24656/* @name RDR - Receive Data Register */
24657/* @{ */
24658#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
24659#define LPSPI_RDR_DATA_SHIFT (0U)
24660#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
24661/* @} */
24662
24663
24664/*
24665 * @}
24666 */ /* end of group LPSPI_Register_Masks */
24667
24668
24669/* LPSPI - Peripheral instance base addresses */
24670/* Peripheral LPSPI1 base address */
24671#define LPSPI1_BASE (0x40394000u)
24672/* Peripheral LPSPI1 base pointer */
24673#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
24674/* Peripheral LPSPI2 base address */
24675#define LPSPI2_BASE (0x40398000u)
24676/* Peripheral LPSPI2 base pointer */
24677#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
24678/* Peripheral LPSPI3 base address */
24679#define LPSPI3_BASE (0x4039C000u)
24680/* Peripheral LPSPI3 base pointer */
24681#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
24682/* Peripheral LPSPI4 base address */
24683#define LPSPI4_BASE (0x403A0000u)
24684/* Peripheral LPSPI4 base pointer */
24685#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
24686/* Array initializer of LPSPI peripheral base addresses */
24687#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE }
24688/* Array initializer of LPSPI peripheral base pointers */
24689#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 }
24690/* Interrupt vectors for the LPSPI peripheral type */
24691#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn }
24692
24693/*
24694 * @}
24695 */ /* end of group LPSPI_Peripheral_Access_Layer */
24696
24697
24698/* ----------------------------------------------------------------------------
24699 -- LPUART Peripheral Access Layer
24700 ---------------------------------------------------------------------------- */
24701
24702/*
24703 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
24704 * @{
24705 */
24706
24707/* LPUART - Register Layout Typedef */
24708typedef struct {
24709 __I uint32_t VERID;
24710 __I uint32_t PARAM;
24711 __IO uint32_t GLOBAL;
24712 __IO uint32_t PINCFG;
24713 __IO uint32_t BAUD;
24714 __IO uint32_t STAT;
24715 __IO uint32_t CTRL;
24716 __IO uint32_t DATA;
24717 __IO uint32_t MATCH;
24718 __IO uint32_t MODIR;
24719 __IO uint32_t FIFO;
24720 __IO uint32_t WATER;
24721} LPUART_Type;
24722
24723/* ----------------------------------------------------------------------------
24724 -- LPUART Register Masks
24725 ---------------------------------------------------------------------------- */
24726
24727/*
24728 * @addtogroup LPUART_Register_Masks LPUART Register Masks
24729 * @{
24730 */
24731
24732/* @name VERID - Version ID Register */
24733/* @{ */
24734#define LPUART_VERID_FEATURE_MASK (0xFFFFU)
24735#define LPUART_VERID_FEATURE_SHIFT (0U)
24736/* FEATURE - Feature Identification Number
24737 * 0b0000000000000001..Standard feature set.
24738 * 0b0000000000000011..Standard feature set with MODEM/IrDA support.
24739 */
24740#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
24741#define LPUART_VERID_MINOR_MASK (0xFF0000U)
24742#define LPUART_VERID_MINOR_SHIFT (16U)
24743#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
24744#define LPUART_VERID_MAJOR_MASK (0xFF000000U)
24745#define LPUART_VERID_MAJOR_SHIFT (24U)
24746#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
24747/* @} */
24748
24749/* @name PARAM - Parameter Register */
24750/* @{ */
24751#define LPUART_PARAM_TXFIFO_MASK (0xFFU)
24752#define LPUART_PARAM_TXFIFO_SHIFT (0U)
24753#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
24754#define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
24755#define LPUART_PARAM_RXFIFO_SHIFT (8U)
24756#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
24757/* @} */
24758
24759/* @name GLOBAL - LPUART Global Register */
24760/* @{ */
24761#define LPUART_GLOBAL_RST_MASK (0x2U)
24762#define LPUART_GLOBAL_RST_SHIFT (1U)
24763/* RST - Software Reset
24764 * 0b0..Module is not reset.
24765 * 0b1..Module is reset.
24766 */
24767#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
24768/* @} */
24769
24770/* @name PINCFG - LPUART Pin Configuration Register */
24771/* @{ */
24772#define LPUART_PINCFG_TRGSEL_MASK (0x3U)
24773#define LPUART_PINCFG_TRGSEL_SHIFT (0U)
24774/* TRGSEL - Trigger Select
24775 * 0b00..Input trigger is disabled.
24776 * 0b01..Input trigger is used instead of RXD pin input.
24777 * 0b10..Input trigger is used instead of CTS_B pin input.
24778 * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.
24779 */
24780#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
24781/* @} */
24782
24783/* @name BAUD - LPUART Baud Rate Register */
24784/* @{ */
24785#define LPUART_BAUD_SBR_MASK (0x1FFFU)
24786#define LPUART_BAUD_SBR_SHIFT (0U)
24787#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
24788#define LPUART_BAUD_SBNS_MASK (0x2000U)
24789#define LPUART_BAUD_SBNS_SHIFT (13U)
24790/* SBNS - Stop Bit Number Select
24791 * 0b0..One stop bit.
24792 * 0b1..Two stop bits.
24793 */
24794#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
24795#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
24796#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
24797/* RXEDGIE - RX Input Active Edge Interrupt Enable
24798 * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
24799 * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
24800 */
24801#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
24802#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
24803#define LPUART_BAUD_LBKDIE_SHIFT (15U)
24804/* LBKDIE - LIN Break Detect Interrupt Enable
24805 * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
24806 * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1.
24807 */
24808#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
24809#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
24810#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
24811/* RESYNCDIS - Resynchronization Disable
24812 * 0b0..Resynchronization during received data word is supported
24813 * 0b1..Resynchronization during received data word is disabled
24814 */
24815#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
24816#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
24817#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
24818/* BOTHEDGE - Both Edge Sampling
24819 * 0b0..Receiver samples input data using the rising edge of the baud rate clock.
24820 * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
24821 */
24822#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
24823#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
24824#define LPUART_BAUD_MATCFG_SHIFT (18U)
24825/* MATCFG - Match Configuration
24826 * 0b00..Address Match Wakeup
24827 * 0b01..Idle Match Wakeup
24828 * 0b10..Match On and Match Off
24829 * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
24830 */
24831#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
24832#define LPUART_BAUD_RIDMAE_MASK (0x100000U)
24833#define LPUART_BAUD_RIDMAE_SHIFT (20U)
24834/* RIDMAE - Receiver Idle DMA Enable
24835 * 0b0..DMA request disabled.
24836 * 0b1..DMA request enabled.
24837 */
24838#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)
24839#define LPUART_BAUD_RDMAE_MASK (0x200000U)
24840#define LPUART_BAUD_RDMAE_SHIFT (21U)
24841/* RDMAE - Receiver Full DMA Enable
24842 * 0b0..DMA request disabled.
24843 * 0b1..DMA request enabled.
24844 */
24845#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
24846#define LPUART_BAUD_TDMAE_MASK (0x800000U)
24847#define LPUART_BAUD_TDMAE_SHIFT (23U)
24848/* TDMAE - Transmitter DMA Enable
24849 * 0b0..DMA request disabled.
24850 * 0b1..DMA request enabled.
24851 */
24852#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
24853#define LPUART_BAUD_OSR_MASK (0x1F000000U)
24854#define LPUART_BAUD_OSR_SHIFT (24U)
24855/* OSR - Oversampling Ratio
24856 * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16
24857 * 0b00001..Reserved
24858 * 0b00010..Reserved
24859 * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
24860 * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
24861 * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
24862 * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
24863 * 0b00111..Oversampling ratio of 8.
24864 * 0b01000..Oversampling ratio of 9.
24865 * 0b01001..Oversampling ratio of 10.
24866 * 0b01010..Oversampling ratio of 11.
24867 * 0b01011..Oversampling ratio of 12.
24868 * 0b01100..Oversampling ratio of 13.
24869 * 0b01101..Oversampling ratio of 14.
24870 * 0b01110..Oversampling ratio of 15.
24871 * 0b01111..Oversampling ratio of 16.
24872 * 0b10000..Oversampling ratio of 17.
24873 * 0b10001..Oversampling ratio of 18.
24874 * 0b10010..Oversampling ratio of 19.
24875 * 0b10011..Oversampling ratio of 20.
24876 * 0b10100..Oversampling ratio of 21.
24877 * 0b10101..Oversampling ratio of 22.
24878 * 0b10110..Oversampling ratio of 23.
24879 * 0b10111..Oversampling ratio of 24.
24880 * 0b11000..Oversampling ratio of 25.
24881 * 0b11001..Oversampling ratio of 26.
24882 * 0b11010..Oversampling ratio of 27.
24883 * 0b11011..Oversampling ratio of 28.
24884 * 0b11100..Oversampling ratio of 29.
24885 * 0b11101..Oversampling ratio of 30.
24886 * 0b11110..Oversampling ratio of 31.
24887 * 0b11111..Oversampling ratio of 32.
24888 */
24889#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
24890#define LPUART_BAUD_M10_MASK (0x20000000U)
24891#define LPUART_BAUD_M10_SHIFT (29U)
24892/* M10 - 10-bit Mode select
24893 * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
24894 * 0b1..Receiver and transmitter use 10-bit data characters.
24895 */
24896#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
24897#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
24898#define LPUART_BAUD_MAEN2_SHIFT (30U)
24899/* MAEN2 - Match Address Mode Enable 2
24900 * 0b0..Normal operation.
24901 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
24902 */
24903#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
24904#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
24905#define LPUART_BAUD_MAEN1_SHIFT (31U)
24906/* MAEN1 - Match Address Mode Enable 1
24907 * 0b0..Normal operation.
24908 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
24909 */
24910#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
24911/* @} */
24912
24913/* @name STAT - LPUART Status Register */
24914/* @{ */
24915#define LPUART_STAT_MA2F_MASK (0x4000U)
24916#define LPUART_STAT_MA2F_SHIFT (14U)
24917/* MA2F - Match 2 Flag
24918 * 0b0..Received data is not equal to MA2
24919 * 0b1..Received data is equal to MA2
24920 */
24921#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
24922#define LPUART_STAT_MA1F_MASK (0x8000U)
24923#define LPUART_STAT_MA1F_SHIFT (15U)
24924/* MA1F - Match 1 Flag
24925 * 0b0..Received data is not equal to MA1
24926 * 0b1..Received data is equal to MA1
24927 */
24928#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
24929#define LPUART_STAT_PF_MASK (0x10000U)
24930#define LPUART_STAT_PF_SHIFT (16U)
24931/* PF - Parity Error Flag
24932 * 0b0..No parity error.
24933 * 0b1..Parity error.
24934 */
24935#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
24936#define LPUART_STAT_FE_MASK (0x20000U)
24937#define LPUART_STAT_FE_SHIFT (17U)
24938/* FE - Framing Error Flag
24939 * 0b0..No framing error detected. This does not guarantee the framing is correct.
24940 * 0b1..Framing error.
24941 */
24942#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
24943#define LPUART_STAT_NF_MASK (0x40000U)
24944#define LPUART_STAT_NF_SHIFT (18U)
24945/* NF - Noise Flag
24946 * 0b0..No noise detected.
24947 * 0b1..Noise detected in the received character in the DATA register.
24948 */
24949#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
24950#define LPUART_STAT_OR_MASK (0x80000U)
24951#define LPUART_STAT_OR_SHIFT (19U)
24952/* OR - Receiver Overrun Flag
24953 * 0b0..No overrun.
24954 * 0b1..Receive overrun (new LPUART data lost).
24955 */
24956#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
24957#define LPUART_STAT_IDLE_MASK (0x100000U)
24958#define LPUART_STAT_IDLE_SHIFT (20U)
24959/* IDLE - Idle Line Flag
24960 * 0b0..No idle line detected.
24961 * 0b1..Idle line was detected.
24962 */
24963#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
24964#define LPUART_STAT_RDRF_MASK (0x200000U)
24965#define LPUART_STAT_RDRF_SHIFT (21U)
24966/* RDRF - Receive Data Register Full Flag
24967 * 0b0..Receive data buffer empty.
24968 * 0b1..Receive data buffer full.
24969 */
24970#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
24971#define LPUART_STAT_TC_MASK (0x400000U)
24972#define LPUART_STAT_TC_SHIFT (22U)
24973/* TC - Transmission Complete Flag
24974 * 0b0..Transmitter active (sending data, a preamble, or a break).
24975 * 0b1..Transmitter idle (transmission activity complete).
24976 */
24977#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
24978#define LPUART_STAT_TDRE_MASK (0x800000U)
24979#define LPUART_STAT_TDRE_SHIFT (23U)
24980/* TDRE - Transmit Data Register Empty Flag
24981 * 0b0..Transmit data buffer full.
24982 * 0b1..Transmit data buffer empty.
24983 */
24984#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
24985#define LPUART_STAT_RAF_MASK (0x1000000U)
24986#define LPUART_STAT_RAF_SHIFT (24U)
24987/* RAF - Receiver Active Flag
24988 * 0b0..LPUART receiver idle waiting for a start bit.
24989 * 0b1..LPUART receiver active (RXD input not idle).
24990 */
24991#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
24992#define LPUART_STAT_LBKDE_MASK (0x2000000U)
24993#define LPUART_STAT_LBKDE_SHIFT (25U)
24994/* LBKDE - LIN Break Detection Enable
24995 * 0b0..LIN break detect is disabled, normal break character can be detected.
24996 * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
24997 */
24998#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
24999#define LPUART_STAT_BRK13_MASK (0x4000000U)
25000#define LPUART_STAT_BRK13_SHIFT (26U)
25001/* BRK13 - Break Character Generation Length
25002 * 0b0..Break character is transmitted with length of 9 to 13 bit times.
25003 * 0b1..Break character is transmitted with length of 12 to 15 bit times.
25004 */
25005#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
25006#define LPUART_STAT_RWUID_MASK (0x8000000U)
25007#define LPUART_STAT_RWUID_SHIFT (27U)
25008/* RWUID - Receive Wake Up Idle Detect
25009 * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
25010 * character. During address match wakeup, the IDLE bit does not set when an address does not match.
25011 * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
25012 * address match wakeup, the IDLE bit does set when an address does not match.
25013 */
25014#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
25015#define LPUART_STAT_RXINV_MASK (0x10000000U)
25016#define LPUART_STAT_RXINV_SHIFT (28U)
25017/* RXINV - Receive Data Inversion
25018 * 0b0..Receive data not inverted.
25019 * 0b1..Receive data inverted.
25020 */
25021#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
25022#define LPUART_STAT_MSBF_MASK (0x20000000U)
25023#define LPUART_STAT_MSBF_SHIFT (29U)
25024/* MSBF - MSB First
25025 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
25026 * after the start bit is identified as bit0.
25027 * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on
25028 * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is
25029 * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
25030 */
25031#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
25032#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
25033#define LPUART_STAT_RXEDGIF_SHIFT (30U)
25034/* RXEDGIF - RXD Pin Active Edge Interrupt Flag
25035 * 0b0..No active edge on the receive pin has occurred.
25036 * 0b1..An active edge on the receive pin has occurred.
25037 */
25038#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
25039#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
25040#define LPUART_STAT_LBKDIF_SHIFT (31U)
25041/* LBKDIF - LIN Break Detect Interrupt Flag
25042 * 0b0..No LIN break character has been detected.
25043 * 0b1..LIN break character has been detected.
25044 */
25045#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
25046/* @} */
25047
25048/* @name CTRL - LPUART Control Register */
25049/* @{ */
25050#define LPUART_CTRL_PT_MASK (0x1U)
25051#define LPUART_CTRL_PT_SHIFT (0U)
25052/* PT - Parity Type
25053 * 0b0..Even parity.
25054 * 0b1..Odd parity.
25055 */
25056#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
25057#define LPUART_CTRL_PE_MASK (0x2U)
25058#define LPUART_CTRL_PE_SHIFT (1U)
25059/* PE - Parity Enable
25060 * 0b0..No hardware parity generation or checking.
25061 * 0b1..Parity enabled.
25062 */
25063#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
25064#define LPUART_CTRL_ILT_MASK (0x4U)
25065#define LPUART_CTRL_ILT_SHIFT (2U)
25066/* ILT - Idle Line Type Select
25067 * 0b0..Idle character bit count starts after start bit.
25068 * 0b1..Idle character bit count starts after stop bit.
25069 */
25070#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
25071#define LPUART_CTRL_WAKE_MASK (0x8U)
25072#define LPUART_CTRL_WAKE_SHIFT (3U)
25073/* WAKE - Receiver Wakeup Method Select
25074 * 0b0..Configures RWU for idle-line wakeup.
25075 * 0b1..Configures RWU with address-mark wakeup.
25076 */
25077#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
25078#define LPUART_CTRL_M_MASK (0x10U)
25079#define LPUART_CTRL_M_SHIFT (4U)
25080/* M - 9-Bit or 8-Bit Mode Select
25081 * 0b0..Receiver and transmitter use 8-bit data characters.
25082 * 0b1..Receiver and transmitter use 9-bit data characters.
25083 */
25084#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
25085#define LPUART_CTRL_RSRC_MASK (0x20U)
25086#define LPUART_CTRL_RSRC_SHIFT (5U)
25087/* RSRC - Receiver Source Select
25088 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
25089 * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
25090 */
25091#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
25092#define LPUART_CTRL_DOZEEN_MASK (0x40U)
25093#define LPUART_CTRL_DOZEEN_SHIFT (6U)
25094/* DOZEEN - Doze Enable
25095 * 0b0..LPUART is enabled in Doze mode.
25096 * 0b1..LPUART is disabled in Doze mode.
25097 */
25098#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
25099#define LPUART_CTRL_LOOPS_MASK (0x80U)
25100#define LPUART_CTRL_LOOPS_SHIFT (7U)
25101/* LOOPS - Loop Mode Select
25102 * 0b0..Normal operation - RXD and TXD use separate pins.
25103 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
25104 */
25105#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
25106#define LPUART_CTRL_IDLECFG_MASK (0x700U)
25107#define LPUART_CTRL_IDLECFG_SHIFT (8U)
25108/* IDLECFG - Idle Configuration
25109 * 0b000..1 idle character
25110 * 0b001..2 idle characters
25111 * 0b010..4 idle characters
25112 * 0b011..8 idle characters
25113 * 0b100..16 idle characters
25114 * 0b101..32 idle characters
25115 * 0b110..64 idle characters
25116 * 0b111..128 idle characters
25117 */
25118#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
25119#define LPUART_CTRL_M7_MASK (0x800U)
25120#define LPUART_CTRL_M7_SHIFT (11U)
25121/* M7 - 7-Bit Mode Select
25122 * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
25123 * 0b1..Receiver and transmitter use 7-bit data characters.
25124 */
25125#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
25126#define LPUART_CTRL_MA2IE_MASK (0x4000U)
25127#define LPUART_CTRL_MA2IE_SHIFT (14U)
25128/* MA2IE - Match 2 Interrupt Enable
25129 * 0b0..MA2F interrupt disabled
25130 * 0b1..MA2F interrupt enabled
25131 */
25132#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
25133#define LPUART_CTRL_MA1IE_MASK (0x8000U)
25134#define LPUART_CTRL_MA1IE_SHIFT (15U)
25135/* MA1IE - Match 1 Interrupt Enable
25136 * 0b0..MA1F interrupt disabled
25137 * 0b1..MA1F interrupt enabled
25138 */
25139#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
25140#define LPUART_CTRL_SBK_MASK (0x10000U)
25141#define LPUART_CTRL_SBK_SHIFT (16U)
25142/* SBK - Send Break
25143 * 0b0..Normal transmitter operation.
25144 * 0b1..Queue break character(s) to be sent.
25145 */
25146#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
25147#define LPUART_CTRL_RWU_MASK (0x20000U)
25148#define LPUART_CTRL_RWU_SHIFT (17U)
25149/* RWU - Receiver Wakeup Control
25150 * 0b0..Normal receiver operation.
25151 * 0b1..LPUART receiver in standby waiting for wakeup condition.
25152 */
25153#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
25154#define LPUART_CTRL_RE_MASK (0x40000U)
25155#define LPUART_CTRL_RE_SHIFT (18U)
25156/* RE - Receiver Enable
25157 * 0b0..Receiver disabled.
25158 * 0b1..Receiver enabled.
25159 */
25160#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
25161#define LPUART_CTRL_TE_MASK (0x80000U)
25162#define LPUART_CTRL_TE_SHIFT (19U)
25163/* TE - Transmitter Enable
25164 * 0b0..Transmitter disabled.
25165 * 0b1..Transmitter enabled.
25166 */
25167#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
25168#define LPUART_CTRL_ILIE_MASK (0x100000U)
25169#define LPUART_CTRL_ILIE_SHIFT (20U)
25170/* ILIE - Idle Line Interrupt Enable
25171 * 0b0..Hardware interrupts from IDLE disabled; use polling.
25172 * 0b1..Hardware interrupt requested when IDLE flag is 1.
25173 */
25174#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
25175#define LPUART_CTRL_RIE_MASK (0x200000U)
25176#define LPUART_CTRL_RIE_SHIFT (21U)
25177/* RIE - Receiver Interrupt Enable
25178 * 0b0..Hardware interrupts from RDRF disabled; use polling.
25179 * 0b1..Hardware interrupt requested when RDRF flag is 1.
25180 */
25181#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
25182#define LPUART_CTRL_TCIE_MASK (0x400000U)
25183#define LPUART_CTRL_TCIE_SHIFT (22U)
25184/* TCIE - Transmission Complete Interrupt Enable for
25185 * 0b0..Hardware interrupts from TC disabled; use polling.
25186 * 0b1..Hardware interrupt requested when TC flag is 1.
25187 */
25188#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
25189#define LPUART_CTRL_TIE_MASK (0x800000U)
25190#define LPUART_CTRL_TIE_SHIFT (23U)
25191/* TIE - Transmit Interrupt Enable
25192 * 0b0..Hardware interrupts from TDRE disabled; use polling.
25193 * 0b1..Hardware interrupt requested when TDRE flag is 1.
25194 */
25195#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
25196#define LPUART_CTRL_PEIE_MASK (0x1000000U)
25197#define LPUART_CTRL_PEIE_SHIFT (24U)
25198/* PEIE - Parity Error Interrupt Enable
25199 * 0b0..PF interrupts disabled; use polling).
25200 * 0b1..Hardware interrupt requested when PF is set.
25201 */
25202#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
25203#define LPUART_CTRL_FEIE_MASK (0x2000000U)
25204#define LPUART_CTRL_FEIE_SHIFT (25U)
25205/* FEIE - Framing Error Interrupt Enable
25206 * 0b0..FE interrupts disabled; use polling.
25207 * 0b1..Hardware interrupt requested when FE is set.
25208 */
25209#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
25210#define LPUART_CTRL_NEIE_MASK (0x4000000U)
25211#define LPUART_CTRL_NEIE_SHIFT (26U)
25212/* NEIE - Noise Error Interrupt Enable
25213 * 0b0..NF interrupts disabled; use polling.
25214 * 0b1..Hardware interrupt requested when NF is set.
25215 */
25216#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
25217#define LPUART_CTRL_ORIE_MASK (0x8000000U)
25218#define LPUART_CTRL_ORIE_SHIFT (27U)
25219/* ORIE - Overrun Interrupt Enable
25220 * 0b0..OR interrupts disabled; use polling.
25221 * 0b1..Hardware interrupt requested when OR is set.
25222 */
25223#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
25224#define LPUART_CTRL_TXINV_MASK (0x10000000U)
25225#define LPUART_CTRL_TXINV_SHIFT (28U)
25226/* TXINV - Transmit Data Inversion
25227 * 0b0..Transmit data not inverted.
25228 * 0b1..Transmit data inverted.
25229 */
25230#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
25231#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
25232#define LPUART_CTRL_TXDIR_SHIFT (29U)
25233/* TXDIR - TXD Pin Direction in Single-Wire Mode
25234 * 0b0..TXD pin is an input in single-wire mode.
25235 * 0b1..TXD pin is an output in single-wire mode.
25236 */
25237#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
25238#define LPUART_CTRL_R9T8_MASK (0x40000000U)
25239#define LPUART_CTRL_R9T8_SHIFT (30U)
25240#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
25241#define LPUART_CTRL_R8T9_MASK (0x80000000U)
25242#define LPUART_CTRL_R8T9_SHIFT (31U)
25243#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
25244/* @} */
25245
25246/* @name DATA - LPUART Data Register */
25247/* @{ */
25248#define LPUART_DATA_R0T0_MASK (0x1U)
25249#define LPUART_DATA_R0T0_SHIFT (0U)
25250#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
25251#define LPUART_DATA_R1T1_MASK (0x2U)
25252#define LPUART_DATA_R1T1_SHIFT (1U)
25253#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
25254#define LPUART_DATA_R2T2_MASK (0x4U)
25255#define LPUART_DATA_R2T2_SHIFT (2U)
25256#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
25257#define LPUART_DATA_R3T3_MASK (0x8U)
25258#define LPUART_DATA_R3T3_SHIFT (3U)
25259#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
25260#define LPUART_DATA_R4T4_MASK (0x10U)
25261#define LPUART_DATA_R4T4_SHIFT (4U)
25262#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
25263#define LPUART_DATA_R5T5_MASK (0x20U)
25264#define LPUART_DATA_R5T5_SHIFT (5U)
25265#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
25266#define LPUART_DATA_R6T6_MASK (0x40U)
25267#define LPUART_DATA_R6T6_SHIFT (6U)
25268#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
25269#define LPUART_DATA_R7T7_MASK (0x80U)
25270#define LPUART_DATA_R7T7_SHIFT (7U)
25271#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
25272#define LPUART_DATA_R8T8_MASK (0x100U)
25273#define LPUART_DATA_R8T8_SHIFT (8U)
25274#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
25275#define LPUART_DATA_R9T9_MASK (0x200U)
25276#define LPUART_DATA_R9T9_SHIFT (9U)
25277#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
25278#define LPUART_DATA_IDLINE_MASK (0x800U)
25279#define LPUART_DATA_IDLINE_SHIFT (11U)
25280/* IDLINE - Idle Line
25281 * 0b0..Receiver was not idle before receiving this character.
25282 * 0b1..Receiver was idle before receiving this character.
25283 */
25284#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
25285#define LPUART_DATA_RXEMPT_MASK (0x1000U)
25286#define LPUART_DATA_RXEMPT_SHIFT (12U)
25287/* RXEMPT - Receive Buffer Empty
25288 * 0b0..Receive buffer contains valid data.
25289 * 0b1..Receive buffer is empty, data returned on read is not valid.
25290 */
25291#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
25292#define LPUART_DATA_FRETSC_MASK (0x2000U)
25293#define LPUART_DATA_FRETSC_SHIFT (13U)
25294/* FRETSC - Frame Error / Transmit Special Character
25295 * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write.
25296 * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.
25297 */
25298#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
25299#define LPUART_DATA_PARITYE_MASK (0x4000U)
25300#define LPUART_DATA_PARITYE_SHIFT (14U)
25301/* PARITYE - PARITYE
25302 * 0b0..The dataword was received without a parity error.
25303 * 0b1..The dataword was received with a parity error.
25304 */
25305#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
25306#define LPUART_DATA_NOISY_MASK (0x8000U)
25307#define LPUART_DATA_NOISY_SHIFT (15U)
25308/* NOISY - NOISY
25309 * 0b0..The dataword was received without noise.
25310 * 0b1..The data was received with noise.
25311 */
25312#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
25313/* @} */
25314
25315/* @name MATCH - LPUART Match Address Register */
25316/* @{ */
25317#define LPUART_MATCH_MA1_MASK (0x3FFU)
25318#define LPUART_MATCH_MA1_SHIFT (0U)
25319#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
25320#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
25321#define LPUART_MATCH_MA2_SHIFT (16U)
25322#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
25323/* @} */
25324
25325/* @name MODIR - LPUART Modem IrDA Register */
25326/* @{ */
25327#define LPUART_MODIR_TXCTSE_MASK (0x1U)
25328#define LPUART_MODIR_TXCTSE_SHIFT (0U)
25329/* TXCTSE - Transmitter clear-to-send enable
25330 * 0b0..CTS has no effect on the transmitter.
25331 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
25332 * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
25333 * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
25334 * do not affect its transmission.
25335 */
25336#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
25337#define LPUART_MODIR_TXRTSE_MASK (0x2U)
25338#define LPUART_MODIR_TXRTSE_SHIFT (1U)
25339/* TXRTSE - Transmitter request-to-send enable
25340 * 0b0..The transmitter has no effect on RTS.
25341 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the
25342 * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and
25343 * shift register are completely sent, including the last stop bit.
25344 */
25345#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
25346#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
25347#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
25348/* TXRTSPOL - Transmitter request-to-send polarity
25349 * 0b0..Transmitter RTS is active low.
25350 * 0b1..Transmitter RTS is active high.
25351 */
25352#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
25353#define LPUART_MODIR_RXRTSE_MASK (0x8U)
25354#define LPUART_MODIR_RXRTSE_SHIFT (3U)
25355/* RXRTSE - Receiver request-to-send enable
25356 * 0b0..The receiver has no effect on RTS.
25357 * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
25358 * the receiver data register to become full. RTS is asserted if the receiver data register is not full and
25359 * has not detected a start bit that would cause the receiver data register to become full.
25360 */
25361#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
25362#define LPUART_MODIR_TXCTSC_MASK (0x10U)
25363#define LPUART_MODIR_TXCTSC_SHIFT (4U)
25364/* TXCTSC - Transmit CTS Configuration
25365 * 0b0..CTS input is sampled at the start of each character.
25366 * 0b1..CTS input is sampled when the transmitter is idle.
25367 */
25368#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
25369#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
25370#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
25371/* TXCTSSRC - Transmit CTS Source
25372 * 0b0..CTS input is the CTS_B pin.
25373 * 0b1..CTS input is the inverted Receiver Match result.
25374 */
25375#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
25376#define LPUART_MODIR_RTSWATER_MASK (0x300U)
25377#define LPUART_MODIR_RTSWATER_SHIFT (8U)
25378#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
25379#define LPUART_MODIR_TNP_MASK (0x30000U)
25380#define LPUART_MODIR_TNP_SHIFT (16U)
25381/* TNP - Transmitter narrow pulse
25382 * 0b00..1/OSR.
25383 * 0b01..2/OSR.
25384 * 0b10..3/OSR.
25385 * 0b11..4/OSR.
25386 */
25387#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
25388#define LPUART_MODIR_IREN_MASK (0x40000U)
25389#define LPUART_MODIR_IREN_SHIFT (18U)
25390/* IREN - Infrared enable
25391 * 0b0..IR disabled.
25392 * 0b1..IR enabled.
25393 */
25394#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
25395/* @} */
25396
25397/* @name FIFO - LPUART FIFO Register */
25398/* @{ */
25399#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
25400#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
25401/* RXFIFOSIZE - Receive FIFO Buffer Depth
25402 * 0b000..Receive FIFO/Buffer depth = 1 dataword.
25403 * 0b001..Receive FIFO/Buffer depth = 4 datawords.
25404 * 0b010..Receive FIFO/Buffer depth = 8 datawords.
25405 * 0b011..Receive FIFO/Buffer depth = 16 datawords.
25406 * 0b100..Receive FIFO/Buffer depth = 32 datawords.
25407 * 0b101..Receive FIFO/Buffer depth = 64 datawords.
25408 * 0b110..Receive FIFO/Buffer depth = 128 datawords.
25409 * 0b111..Receive FIFO/Buffer depth = 256 datawords.
25410 */
25411#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
25412#define LPUART_FIFO_RXFE_MASK (0x8U)
25413#define LPUART_FIFO_RXFE_SHIFT (3U)
25414/* RXFE - Receive FIFO Enable
25415 * 0b0..Receive FIFO is not enabled. Buffer is depth 1.
25416 * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
25417 */
25418#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
25419#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
25420#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
25421/* TXFIFOSIZE - Transmit FIFO Buffer Depth
25422 * 0b000..Transmit FIFO/Buffer depth = 1 dataword.
25423 * 0b001..Transmit FIFO/Buffer depth = 4 datawords.
25424 * 0b010..Transmit FIFO/Buffer depth = 8 datawords.
25425 * 0b011..Transmit FIFO/Buffer depth = 16 datawords.
25426 * 0b100..Transmit FIFO/Buffer depth = 32 datawords.
25427 * 0b101..Transmit FIFO/Buffer depth = 64 datawords.
25428 * 0b110..Transmit FIFO/Buffer depth = 128 datawords.
25429 * 0b111..Transmit FIFO/Buffer depth = 256 datawords
25430 */
25431#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
25432#define LPUART_FIFO_TXFE_MASK (0x80U)
25433#define LPUART_FIFO_TXFE_SHIFT (7U)
25434/* TXFE - Transmit FIFO Enable
25435 * 0b0..Transmit FIFO is not enabled. Buffer is depth 1.
25436 * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
25437 */
25438#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
25439#define LPUART_FIFO_RXUFE_MASK (0x100U)
25440#define LPUART_FIFO_RXUFE_SHIFT (8U)
25441/* RXUFE - Receive FIFO Underflow Interrupt Enable
25442 * 0b0..RXUF flag does not generate an interrupt to the host.
25443 * 0b1..RXUF flag generates an interrupt to the host.
25444 */
25445#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
25446#define LPUART_FIFO_TXOFE_MASK (0x200U)
25447#define LPUART_FIFO_TXOFE_SHIFT (9U)
25448/* TXOFE - Transmit FIFO Overflow Interrupt Enable
25449 * 0b0..TXOF flag does not generate an interrupt to the host.
25450 * 0b1..TXOF flag generates an interrupt to the host.
25451 */
25452#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
25453#define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
25454#define LPUART_FIFO_RXIDEN_SHIFT (10U)
25455/* RXIDEN - Receiver Idle Empty Enable
25456 * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
25457 * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
25458 * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
25459 * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
25460 * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
25461 * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
25462 * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
25463 * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
25464 */
25465#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
25466#define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
25467#define LPUART_FIFO_RXFLUSH_SHIFT (14U)
25468/* RXFLUSH - Receive FIFO/Buffer Flush
25469 * 0b0..No flush operation occurs.
25470 * 0b1..All data in the receive FIFO/buffer is cleared out.
25471 */
25472#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
25473#define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
25474#define LPUART_FIFO_TXFLUSH_SHIFT (15U)
25475/* TXFLUSH - Transmit FIFO/Buffer Flush
25476 * 0b0..No flush operation occurs.
25477 * 0b1..All data in the transmit FIFO/Buffer is cleared out.
25478 */
25479#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
25480#define LPUART_FIFO_RXUF_MASK (0x10000U)
25481#define LPUART_FIFO_RXUF_SHIFT (16U)
25482/* RXUF - Receiver Buffer Underflow Flag
25483 * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
25484 * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
25485 */
25486#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
25487#define LPUART_FIFO_TXOF_MASK (0x20000U)
25488#define LPUART_FIFO_TXOF_SHIFT (17U)
25489/* TXOF - Transmitter Buffer Overflow Flag
25490 * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
25491 * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
25492 */
25493#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
25494#define LPUART_FIFO_RXEMPT_MASK (0x400000U)
25495#define LPUART_FIFO_RXEMPT_SHIFT (22U)
25496/* RXEMPT - Receive Buffer/FIFO Empty
25497 * 0b0..Receive buffer is not empty.
25498 * 0b1..Receive buffer is empty.
25499 */
25500#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
25501#define LPUART_FIFO_TXEMPT_MASK (0x800000U)
25502#define LPUART_FIFO_TXEMPT_SHIFT (23U)
25503/* TXEMPT - Transmit Buffer/FIFO Empty
25504 * 0b0..Transmit buffer is not empty.
25505 * 0b1..Transmit buffer is empty.
25506 */
25507#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
25508/* @} */
25509
25510/* @name WATER - LPUART Watermark Register */
25511/* @{ */
25512#define LPUART_WATER_TXWATER_MASK (0x3U)
25513#define LPUART_WATER_TXWATER_SHIFT (0U)
25514#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
25515#define LPUART_WATER_TXCOUNT_MASK (0x700U)
25516#define LPUART_WATER_TXCOUNT_SHIFT (8U)
25517#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
25518#define LPUART_WATER_RXWATER_MASK (0x30000U)
25519#define LPUART_WATER_RXWATER_SHIFT (16U)
25520#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
25521#define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
25522#define LPUART_WATER_RXCOUNT_SHIFT (24U)
25523#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
25524/* @} */
25525
25526
25527/*
25528 * @}
25529 */ /* end of group LPUART_Register_Masks */
25530
25531
25532/* LPUART - Peripheral instance base addresses */
25533/* Peripheral LPUART1 base address */
25534#define LPUART1_BASE (0x40184000u)
25535/* Peripheral LPUART1 base pointer */
25536#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
25537/* Peripheral LPUART2 base address */
25538#define LPUART2_BASE (0x40188000u)
25539/* Peripheral LPUART2 base pointer */
25540#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
25541/* Peripheral LPUART3 base address */
25542#define LPUART3_BASE (0x4018C000u)
25543/* Peripheral LPUART3 base pointer */
25544#define LPUART3 ((LPUART_Type *)LPUART3_BASE)
25545/* Peripheral LPUART4 base address */
25546#define LPUART4_BASE (0x40190000u)
25547/* Peripheral LPUART4 base pointer */
25548#define LPUART4 ((LPUART_Type *)LPUART4_BASE)
25549/* Peripheral LPUART5 base address */
25550#define LPUART5_BASE (0x40194000u)
25551/* Peripheral LPUART5 base pointer */
25552#define LPUART5 ((LPUART_Type *)LPUART5_BASE)
25553/* Peripheral LPUART6 base address */
25554#define LPUART6_BASE (0x40198000u)
25555/* Peripheral LPUART6 base pointer */
25556#define LPUART6 ((LPUART_Type *)LPUART6_BASE)
25557/* Peripheral LPUART7 base address */
25558#define LPUART7_BASE (0x4019C000u)
25559/* Peripheral LPUART7 base pointer */
25560#define LPUART7 ((LPUART_Type *)LPUART7_BASE)
25561/* Peripheral LPUART8 base address */
25562#define LPUART8_BASE (0x401A0000u)
25563/* Peripheral LPUART8 base pointer */
25564#define LPUART8 ((LPUART_Type *)LPUART8_BASE)
25565/* Array initializer of LPUART peripheral base addresses */
25566#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE }
25567/* Array initializer of LPUART peripheral base pointers */
25568#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 }
25569/* Interrupt vectors for the LPUART peripheral type */
25570#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn }
25571
25572/*
25573 * @}
25574 */ /* end of group LPUART_Peripheral_Access_Layer */
25575
25576
25577/* ----------------------------------------------------------------------------
25578 -- OCOTP Peripheral Access Layer
25579 ---------------------------------------------------------------------------- */
25580
25581/*
25582 * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
25583 * @{
25584 */
25585
25586/* OCOTP - Register Layout Typedef */
25587typedef struct {
25588 __IO uint32_t CTRL;
25589 __IO uint32_t CTRL_SET;
25590 __IO uint32_t CTRL_CLR;
25591 __IO uint32_t CTRL_TOG;
25592 __IO uint32_t TIMING;
25593 uint8_t RESERVED_0[12];
25594 __IO uint32_t DATA;
25595 uint8_t RESERVED_1[12];
25596 __IO uint32_t READ_CTRL;
25597 uint8_t RESERVED_2[12];
25598 __IO uint32_t READ_FUSE_DATA;
25599 uint8_t RESERVED_3[12];
25600 __IO uint32_t SW_STICKY;
25601 uint8_t RESERVED_4[12];
25602 __IO uint32_t SCS;
25603 __IO uint32_t SCS_SET;
25604 __IO uint32_t SCS_CLR;
25605 __IO uint32_t SCS_TOG;
25606 __IO uint32_t CRC_ADDR;
25607 uint8_t RESERVED_5[12];
25608 __IO uint32_t CRC_VALUE;
25609 uint8_t RESERVED_6[12];
25610 __I uint32_t VERSION;
25611 uint8_t RESERVED_7[108];
25612 __IO uint32_t TIMING2;
25613 uint8_t RESERVED_8[764];
25614 __IO uint32_t LOCK;
25615 uint8_t RESERVED_9[12];
25616 __IO uint32_t CFG0;
25617 uint8_t RESERVED_10[12];
25618 __IO uint32_t CFG1;
25619 uint8_t RESERVED_11[12];
25620 __IO uint32_t CFG2;
25621 uint8_t RESERVED_12[12];
25622 __IO uint32_t CFG3;
25623 uint8_t RESERVED_13[12];
25624 __IO uint32_t CFG4;
25625 uint8_t RESERVED_14[12];
25626 __IO uint32_t CFG5;
25627 uint8_t RESERVED_15[12];
25628 __IO uint32_t CFG6;
25629 uint8_t RESERVED_16[12];
25630 __IO uint32_t MEM0;
25631 uint8_t RESERVED_17[12];
25632 __IO uint32_t MEM1;
25633 uint8_t RESERVED_18[12];
25634 __IO uint32_t MEM2;
25635 uint8_t RESERVED_19[12];
25636 __IO uint32_t MEM3;
25637 uint8_t RESERVED_20[12];
25638 __IO uint32_t MEM4;
25639 uint8_t RESERVED_21[12];
25640 __IO uint32_t ANA0;
25641 uint8_t RESERVED_22[12];
25642 __IO uint32_t ANA1;
25643 uint8_t RESERVED_23[12];
25644 __IO uint32_t ANA2;
25645 uint8_t RESERVED_24[12];
25646 __IO uint32_t OTPMK0;
25647 uint8_t RESERVED_25[12];
25648 __IO uint32_t OTPMK1;
25649 uint8_t RESERVED_26[12];
25650 __IO uint32_t OTPMK2;
25651 uint8_t RESERVED_27[12];
25652 __IO uint32_t OTPMK3;
25653 uint8_t RESERVED_28[12];
25654 __IO uint32_t OTPMK4;
25655 uint8_t RESERVED_29[12];
25656 __IO uint32_t OTPMK5;
25657 uint8_t RESERVED_30[12];
25658 __IO uint32_t OTPMK6;
25659 uint8_t RESERVED_31[12];
25660 __IO uint32_t OTPMK7;
25661 uint8_t RESERVED_32[12];
25662 __IO uint32_t SRK0;
25663 uint8_t RESERVED_33[12];
25664 __IO uint32_t SRK1;
25665 uint8_t RESERVED_34[12];
25666 __IO uint32_t SRK2;
25667 uint8_t RESERVED_35[12];
25668 __IO uint32_t SRK3;
25669 uint8_t RESERVED_36[12];
25670 __IO uint32_t SRK4;
25671 uint8_t RESERVED_37[12];
25672 __IO uint32_t SRK5;
25673 uint8_t RESERVED_38[12];
25674 __IO uint32_t SRK6;
25675 uint8_t RESERVED_39[12];
25676 __IO uint32_t SRK7;
25677 uint8_t RESERVED_40[12];
25678 __IO uint32_t SJC_RESP0;
25679 uint8_t RESERVED_41[12];
25680 __IO uint32_t SJC_RESP1;
25681 uint8_t RESERVED_42[12];
25682 __IO uint32_t MAC0;
25683 uint8_t RESERVED_43[12];
25684 __IO uint32_t MAC1;
25685 uint8_t RESERVED_44[12];
25686 __IO uint32_t MAC2;
25687 uint8_t RESERVED_45[12];
25688 __IO uint32_t OTPMK_CRC32;
25689 uint8_t RESERVED_46[12];
25690 __IO uint32_t GP1;
25691 uint8_t RESERVED_47[12];
25692 __IO uint32_t GP2;
25693 uint8_t RESERVED_48[12];
25694 __IO uint32_t SW_GP1;
25695 uint8_t RESERVED_49[12];
25696 __IO uint32_t SW_GP20;
25697 uint8_t RESERVED_50[12];
25698 __IO uint32_t SW_GP21;
25699 uint8_t RESERVED_51[12];
25700 __IO uint32_t SW_GP22;
25701 uint8_t RESERVED_52[12];
25702 __IO uint32_t SW_GP23;
25703 uint8_t RESERVED_53[12];
25704 __IO uint32_t MISC_CONF0;
25705 uint8_t RESERVED_54[12];
25706 __IO uint32_t MISC_CONF1;
25707 uint8_t RESERVED_55[12];
25708 __IO uint32_t SRK_REVOKE;
25709 uint8_t RESERVED_56[268];
25710 __IO uint32_t ROM_PATCH0;
25711 uint8_t RESERVED_57[12];
25712 __IO uint32_t ROM_PATCH1;
25713 uint8_t RESERVED_58[12];
25714 __IO uint32_t ROM_PATCH2;
25715 uint8_t RESERVED_59[12];
25716 __IO uint32_t ROM_PATCH3;
25717 uint8_t RESERVED_60[12];
25718 __IO uint32_t ROM_PATCH4;
25719 uint8_t RESERVED_61[12];
25720 __IO uint32_t ROM_PATCH5;
25721 uint8_t RESERVED_62[12];
25722 __IO uint32_t ROM_PATCH6;
25723 uint8_t RESERVED_63[12];
25724 __IO uint32_t ROM_PATCH7;
25725 uint8_t RESERVED_64[12];
25726 __IO uint32_t GP30;
25727 uint8_t RESERVED_65[12];
25728 __IO uint32_t GP31;
25729 uint8_t RESERVED_66[12];
25730 __IO uint32_t GP32;
25731 uint8_t RESERVED_67[12];
25732 __IO uint32_t GP33;
25733 uint8_t RESERVED_68[12];
25734 __IO uint32_t GP40;
25735 uint8_t RESERVED_69[12];
25736 __IO uint32_t GP41;
25737 uint8_t RESERVED_70[12];
25738 __IO uint32_t GP42;
25739 uint8_t RESERVED_71[12];
25740 __IO uint32_t GP43;
25741} OCOTP_Type;
25742
25743/* ----------------------------------------------------------------------------
25744 -- OCOTP Register Masks
25745 ---------------------------------------------------------------------------- */
25746
25747/*
25748 * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
25749 * @{
25750 */
25751
25752/* @name CTRL - OTP Controller Control Register */
25753/* @{ */
25754#define OCOTP_CTRL_ADDR_MASK (0x3FU)
25755#define OCOTP_CTRL_ADDR_SHIFT (0U)
25756#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
25757#define OCOTP_CTRL_RSVD0_MASK (0xC0U)
25758#define OCOTP_CTRL_RSVD0_SHIFT (6U)
25759#define OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD0_SHIFT)) & OCOTP_CTRL_RSVD0_MASK)
25760#define OCOTP_CTRL_BUSY_MASK (0x100U)
25761#define OCOTP_CTRL_BUSY_SHIFT (8U)
25762#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
25763#define OCOTP_CTRL_ERROR_MASK (0x200U)
25764#define OCOTP_CTRL_ERROR_SHIFT (9U)
25765#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
25766#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
25767#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
25768#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
25769#define OCOTP_CTRL_CRC_TEST_MASK (0x800U)
25770#define OCOTP_CTRL_CRC_TEST_SHIFT (11U)
25771#define OCOTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_CTRL_CRC_TEST_MASK)
25772#define OCOTP_CTRL_CRC_FAIL_MASK (0x1000U)
25773#define OCOTP_CTRL_CRC_FAIL_SHIFT (12U)
25774#define OCOTP_CTRL_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CRC_FAIL_MASK)
25775#define OCOTP_CTRL_RSVD1_MASK (0xE000U)
25776#define OCOTP_CTRL_RSVD1_SHIFT (13U)
25777#define OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD1_SHIFT)) & OCOTP_CTRL_RSVD1_MASK)
25778#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
25779#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
25780/* WR_UNLOCK - WR_UNLOCK
25781 * 0b0011111001110111..Key needed to unlock HW_OCOTP_DATA register.
25782 */
25783#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
25784/* @} */
25785
25786/* @name CTRL_SET - OTP Controller Control Register */
25787/* @{ */
25788#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU)
25789#define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
25790#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
25791#define OCOTP_CTRL_SET_RSVD0_MASK (0xC0U)
25792#define OCOTP_CTRL_SET_RSVD0_SHIFT (6U)
25793#define OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD0_SHIFT)) & OCOTP_CTRL_SET_RSVD0_MASK)
25794#define OCOTP_CTRL_SET_BUSY_MASK (0x100U)
25795#define OCOTP_CTRL_SET_BUSY_SHIFT (8U)
25796#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
25797#define OCOTP_CTRL_SET_ERROR_MASK (0x200U)
25798#define OCOTP_CTRL_SET_ERROR_SHIFT (9U)
25799#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
25800#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
25801#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
25802#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
25803#define OCOTP_CTRL_SET_CRC_TEST_MASK (0x800U)
25804#define OCOTP_CTRL_SET_CRC_TEST_SHIFT (11U)
25805#define OCOTP_CTRL_SET_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_TEST_SHIFT)) & OCOTP_CTRL_SET_CRC_TEST_MASK)
25806#define OCOTP_CTRL_SET_CRC_FAIL_MASK (0x1000U)
25807#define OCOTP_CTRL_SET_CRC_FAIL_SHIFT (12U)
25808#define OCOTP_CTRL_SET_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_FAIL_SHIFT)) & OCOTP_CTRL_SET_CRC_FAIL_MASK)
25809#define OCOTP_CTRL_SET_RSVD1_MASK (0xE000U)
25810#define OCOTP_CTRL_SET_RSVD1_SHIFT (13U)
25811#define OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD1_SHIFT)) & OCOTP_CTRL_SET_RSVD1_MASK)
25812#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
25813#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
25814#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
25815/* @} */
25816
25817/* @name CTRL_CLR - OTP Controller Control Register */
25818/* @{ */
25819#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU)
25820#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
25821#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
25822#define OCOTP_CTRL_CLR_RSVD0_MASK (0xC0U)
25823#define OCOTP_CTRL_CLR_RSVD0_SHIFT (6U)
25824#define OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD0_SHIFT)) & OCOTP_CTRL_CLR_RSVD0_MASK)
25825#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
25826#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
25827#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
25828#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
25829#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
25830#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
25831#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
25832#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
25833#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
25834#define OCOTP_CTRL_CLR_CRC_TEST_MASK (0x800U)
25835#define OCOTP_CTRL_CLR_CRC_TEST_SHIFT (11U)
25836#define OCOTP_CTRL_CLR_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_TEST_SHIFT)) & OCOTP_CTRL_CLR_CRC_TEST_MASK)
25837#define OCOTP_CTRL_CLR_CRC_FAIL_MASK (0x1000U)
25838#define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT (12U)
25839#define OCOTP_CTRL_CLR_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CLR_CRC_FAIL_MASK)
25840#define OCOTP_CTRL_CLR_RSVD1_MASK (0xE000U)
25841#define OCOTP_CTRL_CLR_RSVD1_SHIFT (13U)
25842#define OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD1_SHIFT)) & OCOTP_CTRL_CLR_RSVD1_MASK)
25843#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
25844#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
25845#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
25846/* @} */
25847
25848/* @name CTRL_TOG - OTP Controller Control Register */
25849/* @{ */
25850#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU)
25851#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
25852#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
25853#define OCOTP_CTRL_TOG_RSVD0_MASK (0xC0U)
25854#define OCOTP_CTRL_TOG_RSVD0_SHIFT (6U)
25855#define OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD0_SHIFT)) & OCOTP_CTRL_TOG_RSVD0_MASK)
25856#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
25857#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
25858#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
25859#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
25860#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
25861#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
25862#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
25863#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
25864#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
25865#define OCOTP_CTRL_TOG_CRC_TEST_MASK (0x800U)
25866#define OCOTP_CTRL_TOG_CRC_TEST_SHIFT (11U)
25867#define OCOTP_CTRL_TOG_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_TEST_SHIFT)) & OCOTP_CTRL_TOG_CRC_TEST_MASK)
25868#define OCOTP_CTRL_TOG_CRC_FAIL_MASK (0x1000U)
25869#define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT (12U)
25870#define OCOTP_CTRL_TOG_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_FAIL_SHIFT)) & OCOTP_CTRL_TOG_CRC_FAIL_MASK)
25871#define OCOTP_CTRL_TOG_RSVD1_MASK (0xE000U)
25872#define OCOTP_CTRL_TOG_RSVD1_SHIFT (13U)
25873#define OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD1_SHIFT)) & OCOTP_CTRL_TOG_RSVD1_MASK)
25874#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
25875#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
25876#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
25877/* @} */
25878
25879/* @name TIMING - OTP Controller Timing Register */
25880/* @{ */
25881#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
25882#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
25883#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK)
25884#define OCOTP_TIMING_RELAX_MASK (0xF000U)
25885#define OCOTP_TIMING_RELAX_SHIFT (12U)
25886#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK)
25887#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
25888#define OCOTP_TIMING_STROBE_READ_SHIFT (16U)
25889#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK)
25890#define OCOTP_TIMING_WAIT_MASK (0xFC00000U)
25891#define OCOTP_TIMING_WAIT_SHIFT (22U)
25892#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK)
25893#define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U)
25894#define OCOTP_TIMING_RSRVD0_SHIFT (28U)
25895#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK)
25896/* @} */
25897
25898/* @name DATA - OTP Controller Write Data Register */
25899/* @{ */
25900#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
25901#define OCOTP_DATA_DATA_SHIFT (0U)
25902#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
25903/* @} */
25904
25905/* @name READ_CTRL - OTP Controller Write Data Register */
25906/* @{ */
25907#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
25908#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
25909#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
25910#define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU)
25911#define OCOTP_READ_CTRL_RSVD0_SHIFT (1U)
25912#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK)
25913/* @} */
25914
25915/* @name READ_FUSE_DATA - OTP Controller Read Data Register */
25916/* @{ */
25917#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
25918#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
25919#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
25920/* @} */
25921
25922/* @name SW_STICKY - Sticky bit Register */
25923/* @{ */
25924#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U)
25925#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U)
25926#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK)
25927#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
25928#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
25929#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
25930#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
25931#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
25932#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
25933#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)
25934#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)
25935#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)
25936#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)
25937#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)
25938#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)
25939#define OCOTP_SW_STICKY_RSVD0_MASK (0xFFFFFFE0U)
25940#define OCOTP_SW_STICKY_RSVD0_SHIFT (5U)
25941#define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK)
25942/* @} */
25943
25944/* @name SCS - Software Controllable Signals Register */
25945/* @{ */
25946#define OCOTP_SCS_HAB_JDE_MASK (0x1U)
25947#define OCOTP_SCS_HAB_JDE_SHIFT (0U)
25948#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK)
25949#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
25950#define OCOTP_SCS_SPARE_SHIFT (1U)
25951#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK)
25952#define OCOTP_SCS_LOCK_MASK (0x80000000U)
25953#define OCOTP_SCS_LOCK_SHIFT (31U)
25954#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK)
25955/* @} */
25956
25957/* @name SCS_SET - Software Controllable Signals Register */
25958/* @{ */
25959#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
25960#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
25961#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK)
25962#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
25963#define OCOTP_SCS_SET_SPARE_SHIFT (1U)
25964#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK)
25965#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
25966#define OCOTP_SCS_SET_LOCK_SHIFT (31U)
25967#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK)
25968/* @} */
25969
25970/* @name SCS_CLR - Software Controllable Signals Register */
25971/* @{ */
25972#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
25973#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
25974#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK)
25975#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
25976#define OCOTP_SCS_CLR_SPARE_SHIFT (1U)
25977#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK)
25978#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
25979#define OCOTP_SCS_CLR_LOCK_SHIFT (31U)
25980#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK)
25981/* @} */
25982
25983/* @name SCS_TOG - Software Controllable Signals Register */
25984/* @{ */
25985#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
25986#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
25987#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK)
25988#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
25989#define OCOTP_SCS_TOG_SPARE_SHIFT (1U)
25990#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK)
25991#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
25992#define OCOTP_SCS_TOG_LOCK_SHIFT (31U)
25993#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK)
25994/* @} */
25995
25996/* @name CRC_ADDR - OTP Controller CRC test address */
25997/* @{ */
25998#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xFFU)
25999#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0U)
26000#define OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_START_ADDR_MASK)
26001#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xFF00U)
26002#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8U)
26003#define OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_END_ADDR_MASK)
26004#define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0xFF0000U)
26005#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16U)
26006#define OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)) & OCOTP_CRC_ADDR_CRC_ADDR_MASK)
26007#define OCOTP_CRC_ADDR_OTPMK_CRC_MASK (0x1000000U)
26008#define OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT (24U)
26009#define OCOTP_CRC_ADDR_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT)) & OCOTP_CRC_ADDR_OTPMK_CRC_MASK)
26010#define OCOTP_CRC_ADDR_RSVD0_MASK (0xFE000000U)
26011#define OCOTP_CRC_ADDR_RSVD0_SHIFT (25U)
26012#define OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_RSVD0_SHIFT)) & OCOTP_CRC_ADDR_RSVD0_MASK)
26013/* @} */
26014
26015/* @name CRC_VALUE - OTP Controller CRC Value Register */
26016/* @{ */
26017#define OCOTP_CRC_VALUE_DATA_MASK (0xFFFFFFFFU)
26018#define OCOTP_CRC_VALUE_DATA_SHIFT (0U)
26019#define OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_VALUE_DATA_SHIFT)) & OCOTP_CRC_VALUE_DATA_MASK)
26020/* @} */
26021
26022/* @name VERSION - OTP Controller Version Register */
26023/* @{ */
26024#define OCOTP_VERSION_STEP_MASK (0xFFFFU)
26025#define OCOTP_VERSION_STEP_SHIFT (0U)
26026#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
26027#define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
26028#define OCOTP_VERSION_MINOR_SHIFT (16U)
26029#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
26030#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
26031#define OCOTP_VERSION_MAJOR_SHIFT (24U)
26032#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
26033/* @} */
26034
26035/* @name TIMING2 - OTP Controller Timing Register */
26036/* @{ */
26037#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU)
26038#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U)
26039#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK)
26040#define OCOTP_TIMING2_RSRVD0_MASK (0xF000U)
26041#define OCOTP_TIMING2_RSRVD0_SHIFT (12U)
26042#define OCOTP_TIMING2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RSRVD0_SHIFT)) & OCOTP_TIMING2_RSRVD0_MASK)
26043#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U)
26044#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U)
26045#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK)
26046#define OCOTP_TIMING2_RSRVD1_MASK (0xFFC00000U)
26047#define OCOTP_TIMING2_RSRVD1_SHIFT (22U)
26048#define OCOTP_TIMING2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RSRVD1_SHIFT)) & OCOTP_TIMING2_RSRVD1_MASK)
26049/* @} */
26050
26051/* @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */
26052/* @{ */
26053#define OCOTP_LOCK_TESTER_MASK (0x3U)
26054#define OCOTP_LOCK_TESTER_SHIFT (0U)
26055#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK)
26056#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
26057#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
26058#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK)
26059#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U)
26060#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U)
26061#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK)
26062#define OCOTP_LOCK_SJC_RESP_MASK (0x40U)
26063#define OCOTP_LOCK_SJC_RESP_SHIFT (6U)
26064#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK)
26065#define OCOTP_LOCK_GP4_RLOCK_MASK (0x80U)
26066#define OCOTP_LOCK_GP4_RLOCK_SHIFT (7U)
26067#define OCOTP_LOCK_GP4_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_RLOCK_SHIFT)) & OCOTP_LOCK_GP4_RLOCK_MASK)
26068#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U)
26069#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U)
26070#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK)
26071#define OCOTP_LOCK_GP1_MASK (0xC00U)
26072#define OCOTP_LOCK_GP1_SHIFT (10U)
26073#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK)
26074#define OCOTP_LOCK_GP2_MASK (0x3000U)
26075#define OCOTP_LOCK_GP2_SHIFT (12U)
26076#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK)
26077#define OCOTP_LOCK_ROM_PATCH_MASK (0x8000U)
26078#define OCOTP_LOCK_ROM_PATCH_SHIFT (15U)
26079#define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK)
26080#define OCOTP_LOCK_SW_GP1_MASK (0x10000U)
26081#define OCOTP_LOCK_SW_GP1_SHIFT (16U)
26082#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK)
26083#define OCOTP_LOCK_OTPMK_MASK (0x20000U)
26084#define OCOTP_LOCK_OTPMK_SHIFT (17U)
26085#define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK)
26086#define OCOTP_LOCK_ANALOG_MASK (0xC0000U)
26087#define OCOTP_LOCK_ANALOG_SHIFT (18U)
26088#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK)
26089#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U)
26090#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U)
26091#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK)
26092#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U)
26093#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U)
26094#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK)
26095#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U)
26096#define OCOTP_LOCK_MISC_CONF_SHIFT (22U)
26097#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK)
26098#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U)
26099#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U)
26100#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK)
26101#define OCOTP_LOCK_GP4_MASK (0x3000000U)
26102#define OCOTP_LOCK_GP4_SHIFT (24U)
26103#define OCOTP_LOCK_GP4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_SHIFT)) & OCOTP_LOCK_GP4_MASK)
26104#define OCOTP_LOCK_GP3_MASK (0xC000000U)
26105#define OCOTP_LOCK_GP3_SHIFT (26U)
26106#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK)
26107#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U)
26108#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U)
26109#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK)
26110/* @} */
26111
26112/* @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */
26113/* @{ */
26114#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU)
26115#define OCOTP_CFG0_BITS_SHIFT (0U)
26116#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK)
26117/* @} */
26118
26119/* @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */
26120/* @{ */
26121#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU)
26122#define OCOTP_CFG1_BITS_SHIFT (0U)
26123#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK)
26124/* @} */
26125
26126/* @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */
26127/* @{ */
26128#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU)
26129#define OCOTP_CFG2_BITS_SHIFT (0U)
26130#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK)
26131/* @} */
26132
26133/* @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */
26134/* @{ */
26135#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU)
26136#define OCOTP_CFG3_BITS_SHIFT (0U)
26137#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK)
26138/* @} */
26139
26140/* @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */
26141/* @{ */
26142#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU)
26143#define OCOTP_CFG4_BITS_SHIFT (0U)
26144#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK)
26145/* @} */
26146
26147/* @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */
26148/* @{ */
26149#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU)
26150#define OCOTP_CFG5_BITS_SHIFT (0U)
26151#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK)
26152/* @} */
26153
26154/* @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */
26155/* @{ */
26156#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU)
26157#define OCOTP_CFG6_BITS_SHIFT (0U)
26158#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK)
26159/* @} */
26160
26161/* @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */
26162/* @{ */
26163#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU)
26164#define OCOTP_MEM0_BITS_SHIFT (0U)
26165#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK)
26166/* @} */
26167
26168/* @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */
26169/* @{ */
26170#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU)
26171#define OCOTP_MEM1_BITS_SHIFT (0U)
26172#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK)
26173/* @} */
26174
26175/* @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */
26176/* @{ */
26177#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU)
26178#define OCOTP_MEM2_BITS_SHIFT (0U)
26179#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK)
26180/* @} */
26181
26182/* @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */
26183/* @{ */
26184#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU)
26185#define OCOTP_MEM3_BITS_SHIFT (0U)
26186#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK)
26187/* @} */
26188
26189/* @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */
26190/* @{ */
26191#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU)
26192#define OCOTP_MEM4_BITS_SHIFT (0U)
26193#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK)
26194/* @} */
26195
26196/* @name ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) */
26197/* @{ */
26198#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
26199#define OCOTP_ANA0_BITS_SHIFT (0U)
26200#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK)
26201/* @} */
26202
26203/* @name ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) */
26204/* @{ */
26205#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
26206#define OCOTP_ANA1_BITS_SHIFT (0U)
26207#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK)
26208/* @} */
26209
26210/* @name ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) */
26211/* @{ */
26212#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU)
26213#define OCOTP_ANA2_BITS_SHIFT (0U)
26214#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK)
26215/* @} */
26216
26217/* @name OTPMK0 - Value of OTP Bank2 Word0 (OTPMK Key) */
26218/* @{ */
26219#define OCOTP_OTPMK0_BITS_MASK (0xFFFFFFFFU)
26220#define OCOTP_OTPMK0_BITS_SHIFT (0U)
26221#define OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK0_BITS_SHIFT)) & OCOTP_OTPMK0_BITS_MASK)
26222/* @} */
26223
26224/* @name OTPMK1 - Value of OTP Bank2 Word1 (OTPMK Key) */
26225/* @{ */
26226#define OCOTP_OTPMK1_BITS_MASK (0xFFFFFFFFU)
26227#define OCOTP_OTPMK1_BITS_SHIFT (0U)
26228#define OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK1_BITS_SHIFT)) & OCOTP_OTPMK1_BITS_MASK)
26229/* @} */
26230
26231/* @name OTPMK2 - Value of OTP Bank2 Word2 (OTPMK Key) */
26232/* @{ */
26233#define OCOTP_OTPMK2_BITS_MASK (0xFFFFFFFFU)
26234#define OCOTP_OTPMK2_BITS_SHIFT (0U)
26235#define OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK2_BITS_SHIFT)) & OCOTP_OTPMK2_BITS_MASK)
26236/* @} */
26237
26238/* @name OTPMK3 - Value of OTP Bank2 Word3 (OTPMK Key) */
26239/* @{ */
26240#define OCOTP_OTPMK3_BITS_MASK (0xFFFFFFFFU)
26241#define OCOTP_OTPMK3_BITS_SHIFT (0U)
26242#define OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK3_BITS_SHIFT)) & OCOTP_OTPMK3_BITS_MASK)
26243/* @} */
26244
26245/* @name OTPMK4 - Value of OTP Bank2 Word4 (OTPMK Key) */
26246/* @{ */
26247#define OCOTP_OTPMK4_BITS_MASK (0xFFFFFFFFU)
26248#define OCOTP_OTPMK4_BITS_SHIFT (0U)
26249#define OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK4_BITS_SHIFT)) & OCOTP_OTPMK4_BITS_MASK)
26250/* @} */
26251
26252/* @name OTPMK5 - Value of OTP Bank2 Word5 (OTPMK Key) */
26253/* @{ */
26254#define OCOTP_OTPMK5_BITS_MASK (0xFFFFFFFFU)
26255#define OCOTP_OTPMK5_BITS_SHIFT (0U)
26256#define OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK5_BITS_SHIFT)) & OCOTP_OTPMK5_BITS_MASK)
26257/* @} */
26258
26259/* @name OTPMK6 - Value of OTP Bank2 Word6 (OTPMK Key) */
26260/* @{ */
26261#define OCOTP_OTPMK6_BITS_MASK (0xFFFFFFFFU)
26262#define OCOTP_OTPMK6_BITS_SHIFT (0U)
26263#define OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK6_BITS_SHIFT)) & OCOTP_OTPMK6_BITS_MASK)
26264/* @} */
26265
26266/* @name OTPMK7 - Value of OTP Bank2 Word7 (OTPMK Key) */
26267/* @{ */
26268#define OCOTP_OTPMK7_BITS_MASK (0xFFFFFFFFU)
26269#define OCOTP_OTPMK7_BITS_SHIFT (0U)
26270#define OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK7_BITS_SHIFT)) & OCOTP_OTPMK7_BITS_MASK)
26271/* @} */
26272
26273/* @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */
26274/* @{ */
26275#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
26276#define OCOTP_SRK0_BITS_SHIFT (0U)
26277#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK)
26278/* @} */
26279
26280/* @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */
26281/* @{ */
26282#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
26283#define OCOTP_SRK1_BITS_SHIFT (0U)
26284#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK)
26285/* @} */
26286
26287/* @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */
26288/* @{ */
26289#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
26290#define OCOTP_SRK2_BITS_SHIFT (0U)
26291#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK)
26292/* @} */
26293
26294/* @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */
26295/* @{ */
26296#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
26297#define OCOTP_SRK3_BITS_SHIFT (0U)
26298#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK)
26299/* @} */
26300
26301/* @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */
26302/* @{ */
26303#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
26304#define OCOTP_SRK4_BITS_SHIFT (0U)
26305#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK)
26306/* @} */
26307
26308/* @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */
26309/* @{ */
26310#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
26311#define OCOTP_SRK5_BITS_SHIFT (0U)
26312#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK)
26313/* @} */
26314
26315/* @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */
26316/* @{ */
26317#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
26318#define OCOTP_SRK6_BITS_SHIFT (0U)
26319#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK)
26320/* @} */
26321
26322/* @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */
26323/* @{ */
26324#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
26325#define OCOTP_SRK7_BITS_SHIFT (0U)
26326#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK)
26327/* @} */
26328
26329/* @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */
26330/* @{ */
26331#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
26332#define OCOTP_SJC_RESP0_BITS_SHIFT (0U)
26333#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK)
26334/* @} */
26335
26336/* @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */
26337/* @{ */
26338#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
26339#define OCOTP_SJC_RESP1_BITS_SHIFT (0U)
26340#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK)
26341/* @} */
26342
26343/* @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */
26344/* @{ */
26345#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU)
26346#define OCOTP_MAC0_BITS_SHIFT (0U)
26347#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK)
26348/* @} */
26349
26350/* @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */
26351/* @{ */
26352#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU)
26353#define OCOTP_MAC1_BITS_SHIFT (0U)
26354#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK)
26355/* @} */
26356
26357/* @name MAC2 - Value of OTP Bank4 Word4 (MAC2 Address) */
26358/* @{ */
26359#define OCOTP_MAC2_BITS_MASK (0xFFFFFFFFU)
26360#define OCOTP_MAC2_BITS_SHIFT (0U)
26361#define OCOTP_MAC2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC2_BITS_SHIFT)) & OCOTP_MAC2_BITS_MASK)
26362/* @} */
26363
26364/* @name OTPMK_CRC32 - Value of OTP Bank4 Word5 (CRC Key) */
26365/* @{ */
26366#define OCOTP_OTPMK_CRC32_BITS_MASK (0xFFFFFFFFU)
26367#define OCOTP_OTPMK_CRC32_BITS_SHIFT (0U)
26368#define OCOTP_OTPMK_CRC32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK_CRC32_BITS_SHIFT)) & OCOTP_OTPMK_CRC32_BITS_MASK)
26369/* @} */
26370
26371/* @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */
26372/* @{ */
26373#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU)
26374#define OCOTP_GP1_BITS_SHIFT (0U)
26375#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK)
26376/* @} */
26377
26378/* @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */
26379/* @{ */
26380#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU)
26381#define OCOTP_GP2_BITS_SHIFT (0U)
26382#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK)
26383/* @} */
26384
26385/* @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */
26386/* @{ */
26387#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU)
26388#define OCOTP_SW_GP1_BITS_SHIFT (0U)
26389#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK)
26390/* @} */
26391
26392/* @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */
26393/* @{ */
26394#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU)
26395#define OCOTP_SW_GP20_BITS_SHIFT (0U)
26396#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK)
26397/* @} */
26398
26399/* @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */
26400/* @{ */
26401#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU)
26402#define OCOTP_SW_GP21_BITS_SHIFT (0U)
26403#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK)
26404/* @} */
26405
26406/* @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */
26407/* @{ */
26408#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU)
26409#define OCOTP_SW_GP22_BITS_SHIFT (0U)
26410#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK)
26411/* @} */
26412
26413/* @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */
26414/* @{ */
26415#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU)
26416#define OCOTP_SW_GP23_BITS_SHIFT (0U)
26417#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK)
26418/* @} */
26419
26420/* @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */
26421/* @{ */
26422#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU)
26423#define OCOTP_MISC_CONF0_BITS_SHIFT (0U)
26424#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK)
26425/* @} */
26426
26427/* @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */
26428/* @{ */
26429#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU)
26430#define OCOTP_MISC_CONF1_BITS_SHIFT (0U)
26431#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK)
26432/* @} */
26433
26434/* @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */
26435/* @{ */
26436#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
26437#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
26438#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK)
26439/* @} */
26440
26441/* @name ROM_PATCH0 - Value of OTP Bank6 Word0 (ROM Patch) */
26442/* @{ */
26443#define OCOTP_ROM_PATCH0_BITS_MASK (0xFFFFFFFFU)
26444#define OCOTP_ROM_PATCH0_BITS_SHIFT (0U)
26445#define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH0_BITS_SHIFT)) & OCOTP_ROM_PATCH0_BITS_MASK)
26446/* @} */
26447
26448/* @name ROM_PATCH1 - Value of OTP Bank6 Word1 (ROM Patch) */
26449/* @{ */
26450#define OCOTP_ROM_PATCH1_BITS_MASK (0xFFFFFFFFU)
26451#define OCOTP_ROM_PATCH1_BITS_SHIFT (0U)
26452#define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH1_BITS_SHIFT)) & OCOTP_ROM_PATCH1_BITS_MASK)
26453/* @} */
26454
26455/* @name ROM_PATCH2 - Value of OTP Bank6 Word2 (ROM Patch) */
26456/* @{ */
26457#define OCOTP_ROM_PATCH2_BITS_MASK (0xFFFFFFFFU)
26458#define OCOTP_ROM_PATCH2_BITS_SHIFT (0U)
26459#define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH2_BITS_SHIFT)) & OCOTP_ROM_PATCH2_BITS_MASK)
26460/* @} */
26461
26462/* @name ROM_PATCH3 - Value of OTP Bank6 Word3 (ROM Patch) */
26463/* @{ */
26464#define OCOTP_ROM_PATCH3_BITS_MASK (0xFFFFFFFFU)
26465#define OCOTP_ROM_PATCH3_BITS_SHIFT (0U)
26466#define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH3_BITS_SHIFT)) & OCOTP_ROM_PATCH3_BITS_MASK)
26467/* @} */
26468
26469/* @name ROM_PATCH4 - Value of OTP Bank6 Word4 (ROM Patch) */
26470/* @{ */
26471#define OCOTP_ROM_PATCH4_BITS_MASK (0xFFFFFFFFU)
26472#define OCOTP_ROM_PATCH4_BITS_SHIFT (0U)
26473#define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH4_BITS_SHIFT)) & OCOTP_ROM_PATCH4_BITS_MASK)
26474/* @} */
26475
26476/* @name ROM_PATCH5 - Value of OTP Bank6 Word5 (ROM Patch) */
26477/* @{ */
26478#define OCOTP_ROM_PATCH5_BITS_MASK (0xFFFFFFFFU)
26479#define OCOTP_ROM_PATCH5_BITS_SHIFT (0U)
26480#define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH5_BITS_SHIFT)) & OCOTP_ROM_PATCH5_BITS_MASK)
26481/* @} */
26482
26483/* @name ROM_PATCH6 - Value of OTP Bank6 Word6 (ROM Patch) */
26484/* @{ */
26485#define OCOTP_ROM_PATCH6_BITS_MASK (0xFFFFFFFFU)
26486#define OCOTP_ROM_PATCH6_BITS_SHIFT (0U)
26487#define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH6_BITS_SHIFT)) & OCOTP_ROM_PATCH6_BITS_MASK)
26488/* @} */
26489
26490/* @name ROM_PATCH7 - Value of OTP Bank6 Word7 (ROM Patch) */
26491/* @{ */
26492#define OCOTP_ROM_PATCH7_BITS_MASK (0xFFFFFFFFU)
26493#define OCOTP_ROM_PATCH7_BITS_SHIFT (0U)
26494#define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH7_BITS_SHIFT)) & OCOTP_ROM_PATCH7_BITS_MASK)
26495/* @} */
26496
26497/* @name GP30 - Value of OTP Bank7 Word0 (GP3) */
26498/* @{ */
26499#define OCOTP_GP30_BITS_MASK (0xFFFFFFFFU)
26500#define OCOTP_GP30_BITS_SHIFT (0U)
26501#define OCOTP_GP30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP30_BITS_SHIFT)) & OCOTP_GP30_BITS_MASK)
26502/* @} */
26503
26504/* @name GP31 - Value of OTP Bank7 Word1 (GP3) */
26505/* @{ */
26506#define OCOTP_GP31_BITS_MASK (0xFFFFFFFFU)
26507#define OCOTP_GP31_BITS_SHIFT (0U)
26508#define OCOTP_GP31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP31_BITS_SHIFT)) & OCOTP_GP31_BITS_MASK)
26509/* @} */
26510
26511/* @name GP32 - Value of OTP Bank7 Word2 (GP3) */
26512/* @{ */
26513#define OCOTP_GP32_BITS_MASK (0xFFFFFFFFU)
26514#define OCOTP_GP32_BITS_SHIFT (0U)
26515#define OCOTP_GP32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP32_BITS_SHIFT)) & OCOTP_GP32_BITS_MASK)
26516/* @} */
26517
26518/* @name GP33 - Value of OTP Bank7 Word3 (GP3) */
26519/* @{ */
26520#define OCOTP_GP33_BITS_MASK (0xFFFFFFFFU)
26521#define OCOTP_GP33_BITS_SHIFT (0U)
26522#define OCOTP_GP33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP33_BITS_SHIFT)) & OCOTP_GP33_BITS_MASK)
26523/* @} */
26524
26525/* @name GP40 - Value of OTP Bank7 Word4 (GP4) */
26526/* @{ */
26527#define OCOTP_GP40_BITS_MASK (0xFFFFFFFFU)
26528#define OCOTP_GP40_BITS_SHIFT (0U)
26529#define OCOTP_GP40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP40_BITS_SHIFT)) & OCOTP_GP40_BITS_MASK)
26530/* @} */
26531
26532/* @name GP41 - Value of OTP Bank7 Word5 (GP4) */
26533/* @{ */
26534#define OCOTP_GP41_BITS_MASK (0xFFFFFFFFU)
26535#define OCOTP_GP41_BITS_SHIFT (0U)
26536#define OCOTP_GP41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP41_BITS_SHIFT)) & OCOTP_GP41_BITS_MASK)
26537/* @} */
26538
26539/* @name GP42 - Value of OTP Bank7 Word6 (GP4) */
26540/* @{ */
26541#define OCOTP_GP42_BITS_MASK (0xFFFFFFFFU)
26542#define OCOTP_GP42_BITS_SHIFT (0U)
26543#define OCOTP_GP42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP42_BITS_SHIFT)) & OCOTP_GP42_BITS_MASK)
26544/* @} */
26545
26546/* @name GP43 - Value of OTP Bank7 Word7 (GP4) */
26547/* @{ */
26548#define OCOTP_GP43_BITS_MASK (0xFFFFFFFFU)
26549#define OCOTP_GP43_BITS_SHIFT (0U)
26550#define OCOTP_GP43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP43_BITS_SHIFT)) & OCOTP_GP43_BITS_MASK)
26551/* @} */
26552
26553
26554/*
26555 * @}
26556 */ /* end of group OCOTP_Register_Masks */
26557
26558
26559/* OCOTP - Peripheral instance base addresses */
26560/* Peripheral OCOTP base address */
26561#define OCOTP_BASE (0x401F4000u)
26562/* Peripheral OCOTP base pointer */
26563#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
26564/* Array initializer of OCOTP peripheral base addresses */
26565#define OCOTP_BASE_ADDRS { OCOTP_BASE }
26566/* Array initializer of OCOTP peripheral base pointers */
26567#define OCOTP_BASE_PTRS { OCOTP }
26568
26569/*
26570 * @}
26571 */ /* end of group OCOTP_Peripheral_Access_Layer */
26572
26573
26574/* ----------------------------------------------------------------------------
26575 -- PGC Peripheral Access Layer
26576 ---------------------------------------------------------------------------- */
26577
26578/*
26579 * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer
26580 * @{
26581 */
26582
26583/* PGC - Register Layout Typedef */
26584typedef struct {
26585 uint8_t RESERVED_0[544];
26586 __IO uint32_t MEGA_CTRL;
26587 __IO uint32_t MEGA_PUPSCR;
26588 __IO uint32_t MEGA_PDNSCR;
26589 __IO uint32_t MEGA_SR;
26590 uint8_t RESERVED_1[112];
26591 __IO uint32_t CPU_CTRL;
26592 __IO uint32_t CPU_PUPSCR;
26593 __IO uint32_t CPU_PDNSCR;
26594 __IO uint32_t CPU_SR;
26595} PGC_Type;
26596
26597/* ----------------------------------------------------------------------------
26598 -- PGC Register Masks
26599 ---------------------------------------------------------------------------- */
26600
26601/*
26602 * @addtogroup PGC_Register_Masks PGC Register Masks
26603 * @{
26604 */
26605
26606/* @name MEGA_CTRL - PGC Mega Control Register */
26607/* @{ */
26608#define PGC_MEGA_CTRL_PCR_MASK (0x1U)
26609#define PGC_MEGA_CTRL_PCR_SHIFT (0U)
26610/* PCR
26611 * 0b0..Do not switch off power even if pdn_req is asserted.
26612 * 0b1..Switch off power when pdn_req is asserted.
26613 */
26614#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK)
26615/* @} */
26616
26617/* @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */
26618/* @{ */
26619#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU)
26620#define PGC_MEGA_PUPSCR_SW_SHIFT (0U)
26621#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK)
26622#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U)
26623#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U)
26624#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK)
26625/* @} */
26626
26627/* @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */
26628/* @{ */
26629#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU)
26630#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U)
26631#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK)
26632#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U)
26633#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U)
26634#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK)
26635/* @} */
26636
26637/* @name MEGA_SR - PGC Mega Power Gating Controller Status Register */
26638/* @{ */
26639#define PGC_MEGA_SR_PSR_MASK (0x1U)
26640#define PGC_MEGA_SR_PSR_SHIFT (0U)
26641/* PSR
26642 * 0b0..The target subsystem was not powered down for the previous power-down request.
26643 * 0b1..The target subsystem was powered down for the previous power-down request.
26644 */
26645#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK)
26646/* @} */
26647
26648/* @name CPU_CTRL - PGC CPU Control Register */
26649/* @{ */
26650#define PGC_CPU_CTRL_PCR_MASK (0x1U)
26651#define PGC_CPU_CTRL_PCR_SHIFT (0U)
26652/* PCR
26653 * 0b0..Do not switch off power even if pdn_req is asserted.
26654 * 0b1..Switch off power when pdn_req is asserted.
26655 */
26656#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK)
26657/* @} */
26658
26659/* @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */
26660/* @{ */
26661#define PGC_CPU_PUPSCR_SW_MASK (0x3FU)
26662#define PGC_CPU_PUPSCR_SW_SHIFT (0U)
26663#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK)
26664#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U)
26665#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U)
26666#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK)
26667/* @} */
26668
26669/* @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */
26670/* @{ */
26671#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU)
26672#define PGC_CPU_PDNSCR_ISO_SHIFT (0U)
26673#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK)
26674#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U)
26675#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U)
26676#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK)
26677/* @} */
26678
26679/* @name CPU_SR - PGC CPU Power Gating Controller Status Register */
26680/* @{ */
26681#define PGC_CPU_SR_PSR_MASK (0x1U)
26682#define PGC_CPU_SR_PSR_SHIFT (0U)
26683/* PSR
26684 * 0b0..The target subsystem was not powered down for the previous power-down request.
26685 * 0b1..The target subsystem was powered down for the previous power-down request.
26686 */
26687#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK)
26688/* @} */
26689
26690
26691/*
26692 * @}
26693 */ /* end of group PGC_Register_Masks */
26694
26695
26696/* PGC - Peripheral instance base addresses */
26697/* Peripheral PGC base address */
26698#define PGC_BASE (0x400F4000u)
26699/* Peripheral PGC base pointer */
26700#define PGC ((PGC_Type *)PGC_BASE)
26701/* Array initializer of PGC peripheral base addresses */
26702#define PGC_BASE_ADDRS { PGC_BASE }
26703/* Array initializer of PGC peripheral base pointers */
26704#define PGC_BASE_PTRS { PGC }
26705
26706/*
26707 * @}
26708 */ /* end of group PGC_Peripheral_Access_Layer */
26709
26710
26711/* ----------------------------------------------------------------------------
26712 -- PIT Peripheral Access Layer
26713 ---------------------------------------------------------------------------- */
26714
26715/*
26716 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
26717 * @{
26718 */
26719
26720/* PIT - Register Layout Typedef */
26721typedef struct {
26722 __IO uint32_t MCR;
26723 uint8_t RESERVED_0[220];
26724 __I uint32_t LTMR64H;
26725 __I uint32_t LTMR64L;
26726 uint8_t RESERVED_1[24];
26727 struct { /* offset: 0x100, array step: 0x10 */
26728 __IO uint32_t LDVAL;
26729 __I uint32_t CVAL;
26730 __IO uint32_t TCTRL;
26731 __IO uint32_t TFLG;
26732 } CHANNEL[4];
26733} PIT_Type;
26734
26735/* ----------------------------------------------------------------------------
26736 -- PIT Register Masks
26737 ---------------------------------------------------------------------------- */
26738
26739/*
26740 * @addtogroup PIT_Register_Masks PIT Register Masks
26741 * @{
26742 */
26743
26744/* @name MCR - PIT Module Control Register */
26745/* @{ */
26746#define PIT_MCR_FRZ_MASK (0x1U)
26747#define PIT_MCR_FRZ_SHIFT (0U)
26748/* FRZ - Freeze
26749 * 0b0..Timers continue to run in Debug mode.
26750 * 0b1..Timers are stopped in Debug mode.
26751 */
26752#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
26753#define PIT_MCR_MDIS_MASK (0x2U)
26754#define PIT_MCR_MDIS_SHIFT (1U)
26755/* MDIS - Module Disable - (PIT section)
26756 * 0b0..Clock for standard PIT timers is enabled.
26757 * 0b1..Clock for standard PIT timers is disabled.
26758 */
26759#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
26760/* @} */
26761
26762/* @name LTMR64H - PIT Upper Lifetime Timer Register */
26763/* @{ */
26764#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
26765#define PIT_LTMR64H_LTH_SHIFT (0U)
26766#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
26767/* @} */
26768
26769/* @name LTMR64L - PIT Lower Lifetime Timer Register */
26770/* @{ */
26771#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
26772#define PIT_LTMR64L_LTL_SHIFT (0U)
26773#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
26774/* @} */
26775
26776/* @name LDVAL - Timer Load Value Register */
26777/* @{ */
26778#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
26779#define PIT_LDVAL_TSV_SHIFT (0U)
26780#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
26781/* @} */
26782
26783/* The count of PIT_LDVAL */
26784#define PIT_LDVAL_COUNT (4U)
26785
26786/* @name CVAL - Current Timer Value Register */
26787/* @{ */
26788#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
26789#define PIT_CVAL_TVL_SHIFT (0U)
26790#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
26791/* @} */
26792
26793/* The count of PIT_CVAL */
26794#define PIT_CVAL_COUNT (4U)
26795
26796/* @name TCTRL - Timer Control Register */
26797/* @{ */
26798#define PIT_TCTRL_TEN_MASK (0x1U)
26799#define PIT_TCTRL_TEN_SHIFT (0U)
26800/* TEN - Timer Enable
26801 * 0b0..Timer n is disabled.
26802 * 0b1..Timer n is enabled.
26803 */
26804#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
26805#define PIT_TCTRL_TIE_MASK (0x2U)
26806#define PIT_TCTRL_TIE_SHIFT (1U)
26807/* TIE - Timer Interrupt Enable
26808 * 0b0..Interrupt requests from Timer n are disabled.
26809 * 0b1..Interrupt will be requested whenever TIF is set.
26810 */
26811#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
26812#define PIT_TCTRL_CHN_MASK (0x4U)
26813#define PIT_TCTRL_CHN_SHIFT (2U)
26814/* CHN - Chain Mode
26815 * 0b0..Timer is not chained.
26816 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
26817 */
26818#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
26819/* @} */
26820
26821/* The count of PIT_TCTRL */
26822#define PIT_TCTRL_COUNT (4U)
26823
26824/* @name TFLG - Timer Flag Register */
26825/* @{ */
26826#define PIT_TFLG_TIF_MASK (0x1U)
26827#define PIT_TFLG_TIF_SHIFT (0U)
26828/* TIF - Timer Interrupt Flag
26829 * 0b0..Timeout has not yet occurred.
26830 * 0b1..Timeout has occurred.
26831 */
26832#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
26833/* @} */
26834
26835/* The count of PIT_TFLG */
26836#define PIT_TFLG_COUNT (4U)
26837
26838
26839/*
26840 * @}
26841 */ /* end of group PIT_Register_Masks */
26842
26843
26844/* PIT - Peripheral instance base addresses */
26845/* Peripheral PIT base address */
26846#define PIT_BASE (0x40084000u)
26847/* Peripheral PIT base pointer */
26848#define PIT ((PIT_Type *)PIT_BASE)
26849/* Array initializer of PIT peripheral base addresses */
26850#define PIT_BASE_ADDRS { PIT_BASE }
26851/* Array initializer of PIT peripheral base pointers */
26852#define PIT_BASE_PTRS { PIT }
26853/* Interrupt vectors for the PIT peripheral type */
26854#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } }
26855
26856/*
26857 * @}
26858 */ /* end of group PIT_Peripheral_Access_Layer */
26859
26860
26861/* ----------------------------------------------------------------------------
26862 -- PMU Peripheral Access Layer
26863 ---------------------------------------------------------------------------- */
26864
26865/*
26866 * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
26867 * @{
26868 */
26869
26870/* PMU - Register Layout Typedef */
26871typedef struct {
26872 uint8_t RESERVED_0[272];
26873 __IO uint32_t REG_1P1;
26874 __IO uint32_t REG_1P1_SET;
26875 __IO uint32_t REG_1P1_CLR;
26876 __IO uint32_t REG_1P1_TOG;
26877 __IO uint32_t REG_3P0;
26878 __IO uint32_t REG_3P0_SET;
26879 __IO uint32_t REG_3P0_CLR;
26880 __IO uint32_t REG_3P0_TOG;
26881 __IO uint32_t REG_2P5;
26882 __IO uint32_t REG_2P5_SET;
26883 __IO uint32_t REG_2P5_CLR;
26884 __IO uint32_t REG_2P5_TOG;
26885 __IO uint32_t REG_CORE;
26886 __IO uint32_t REG_CORE_SET;
26887 __IO uint32_t REG_CORE_CLR;
26888 __IO uint32_t REG_CORE_TOG;
26889 __IO uint32_t MISC0;
26890 __IO uint32_t MISC0_SET;
26891 __IO uint32_t MISC0_CLR;
26892 __IO uint32_t MISC0_TOG;
26893 __IO uint32_t MISC1;
26894 __IO uint32_t MISC1_SET;
26895 __IO uint32_t MISC1_CLR;
26896 __IO uint32_t MISC1_TOG;
26897 __IO uint32_t MISC2;
26898 __IO uint32_t MISC2_SET;
26899 __IO uint32_t MISC2_CLR;
26900 __IO uint32_t MISC2_TOG;
26901} PMU_Type;
26902
26903/* ----------------------------------------------------------------------------
26904 -- PMU Register Masks
26905 ---------------------------------------------------------------------------- */
26906
26907/*
26908 * @addtogroup PMU_Register_Masks PMU Register Masks
26909 * @{
26910 */
26911
26912/* @name REG_1P1 - Regulator 1P1 Register */
26913/* @{ */
26914#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U)
26915#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U)
26916#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK)
26917#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U)
26918#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U)
26919#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK)
26920#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U)
26921#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U)
26922#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK)
26923#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U)
26924#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U)
26925#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK)
26926#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U)
26927#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U)
26928#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK)
26929#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U)
26930#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U)
26931/* OUTPUT_TRG
26932 * 0b00100..0.8V
26933 * 0b10000..1.1V
26934 * 0b000x1..1.375V
26935 */
26936#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK)
26937#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U)
26938#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U)
26939#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK)
26940#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U)
26941#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U)
26942#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK)
26943#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U)
26944#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U)
26945#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK)
26946#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U)
26947#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U)
26948/* SELREF_WEAK_LINREG
26949 * 0b0..Weak-linreg output tracks low-power-bandgap voltage
26950 * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage
26951 */
26952#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK)
26953/* @} */
26954
26955/* @name REG_1P1_SET - Regulator 1P1 Register */
26956/* @{ */
26957#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U)
26958#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U)
26959#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK)
26960#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U)
26961#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U)
26962#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK)
26963#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U)
26964#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U)
26965#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK)
26966#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U)
26967#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U)
26968#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK)
26969#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U)
26970#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U)
26971#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK)
26972#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U)
26973#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U)
26974/* OUTPUT_TRG
26975 * 0b00100..0.8V
26976 * 0b10000..1.1V
26977 * 0b000x1..1.375V
26978 */
26979#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK)
26980#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U)
26981#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U)
26982#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK)
26983#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U)
26984#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U)
26985#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK)
26986#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
26987#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
26988#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK)
26989#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U)
26990#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U)
26991/* SELREF_WEAK_LINREG
26992 * 0b0..Weak-linreg output tracks low-power-bandgap voltage
26993 * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage
26994 */
26995#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK)
26996/* @} */
26997
26998/* @name REG_1P1_CLR - Regulator 1P1 Register */
26999/* @{ */
27000#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U)
27001#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U)
27002#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK)
27003#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U)
27004#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U)
27005#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK)
27006#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U)
27007#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U)
27008#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK)
27009#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U)
27010#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U)
27011#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK)
27012#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U)
27013#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U)
27014#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK)
27015#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U)
27016#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U)
27017/* OUTPUT_TRG
27018 * 0b00100..0.8V
27019 * 0b10000..1.1V
27020 * 0b000x1..1.375V
27021 */
27022#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK)
27023#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U)
27024#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U)
27025#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK)
27026#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U)
27027#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U)
27028#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK)
27029#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
27030#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
27031#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK)
27032#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U)
27033#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U)
27034/* SELREF_WEAK_LINREG
27035 * 0b0..Weak-linreg output tracks low-power-bandgap voltage
27036 * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage
27037 */
27038#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK)
27039/* @} */
27040
27041/* @name REG_1P1_TOG - Regulator 1P1 Register */
27042/* @{ */
27043#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U)
27044#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U)
27045#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK)
27046#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U)
27047#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U)
27048#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK)
27049#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U)
27050#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U)
27051#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK)
27052#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U)
27053#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U)
27054#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK)
27055#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U)
27056#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U)
27057#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK)
27058#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U)
27059#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U)
27060/* OUTPUT_TRG
27061 * 0b00100..0.8V
27062 * 0b10000..1.1V
27063 * 0b000x1..1.375V
27064 */
27065#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK)
27066#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U)
27067#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U)
27068#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK)
27069#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U)
27070#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U)
27071#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK)
27072#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
27073#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
27074#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK)
27075#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U)
27076#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U)
27077/* SELREF_WEAK_LINREG
27078 * 0b0..Weak-linreg output tracks low-power-bandgap voltage
27079 * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage
27080 */
27081#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK)
27082/* @} */
27083
27084/* @name REG_3P0 - Regulator 3P0 Register */
27085/* @{ */
27086#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U)
27087#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U)
27088#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK)
27089#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U)
27090#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U)
27091#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK)
27092#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U)
27093#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U)
27094#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK)
27095#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U)
27096#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U)
27097#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK)
27098#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U)
27099#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U)
27100/* VBUS_SEL
27101 * 0b1..Utilize VBUS OTG1 power
27102 * 0b0..Utilize VBUS OTG2 power
27103 */
27104#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK)
27105#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U)
27106#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U)
27107/* OUTPUT_TRG
27108 * 0b00000..2.625V
27109 * 0b01111..3.000V
27110 * 0b11111..3.400V
27111 */
27112#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK)
27113#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U)
27114#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U)
27115#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK)
27116#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U)
27117#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U)
27118#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK)
27119/* @} */
27120
27121/* @name REG_3P0_SET - Regulator 3P0 Register */
27122/* @{ */
27123#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U)
27124#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U)
27125#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK)
27126#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U)
27127#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U)
27128#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK)
27129#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U)
27130#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U)
27131#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK)
27132#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U)
27133#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U)
27134#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK)
27135#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U)
27136#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U)
27137/* VBUS_SEL
27138 * 0b1..Utilize VBUS OTG1 power
27139 * 0b0..Utilize VBUS OTG2 power
27140 */
27141#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK)
27142#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U)
27143#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U)
27144/* OUTPUT_TRG
27145 * 0b00000..2.625V
27146 * 0b01111..3.000V
27147 * 0b11111..3.400V
27148 */
27149#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
27150#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U)
27151#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U)
27152#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK)
27153#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U)
27154#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U)
27155#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK)
27156/* @} */
27157
27158/* @name REG_3P0_CLR - Regulator 3P0 Register */
27159/* @{ */
27160#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U)
27161#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U)
27162#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK)
27163#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U)
27164#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U)
27165#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK)
27166#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U)
27167#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U)
27168#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK)
27169#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U)
27170#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U)
27171#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK)
27172#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U)
27173#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U)
27174/* VBUS_SEL
27175 * 0b1..Utilize VBUS OTG1 power
27176 * 0b0..Utilize VBUS OTG2 power
27177 */
27178#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK)
27179#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U)
27180#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U)
27181/* OUTPUT_TRG
27182 * 0b00000..2.625V
27183 * 0b01111..3.000V
27184 * 0b11111..3.400V
27185 */
27186#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
27187#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U)
27188#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U)
27189#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK)
27190#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U)
27191#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U)
27192#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK)
27193/* @} */
27194
27195/* @name REG_3P0_TOG - Regulator 3P0 Register */
27196/* @{ */
27197#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U)
27198#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U)
27199#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK)
27200#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U)
27201#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U)
27202#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK)
27203#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U)
27204#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U)
27205#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK)
27206#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U)
27207#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U)
27208#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK)
27209#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U)
27210#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U)
27211/* VBUS_SEL
27212 * 0b1..Utilize VBUS OTG1 power
27213 * 0b0..Utilize VBUS OTG2 power
27214 */
27215#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK)
27216#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U)
27217#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U)
27218/* OUTPUT_TRG
27219 * 0b00000..2.625V
27220 * 0b01111..3.000V
27221 * 0b11111..3.400V
27222 */
27223#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
27224#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U)
27225#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U)
27226#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK)
27227#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U)
27228#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U)
27229#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK)
27230/* @} */
27231
27232/* @name REG_2P5 - Regulator 2P5 Register */
27233/* @{ */
27234#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U)
27235#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U)
27236#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK)
27237#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U)
27238#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U)
27239#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK)
27240#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U)
27241#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U)
27242#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK)
27243#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U)
27244#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U)
27245#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK)
27246#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U)
27247#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U)
27248#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK)
27249#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U)
27250#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U)
27251/* OUTPUT_TRG
27252 * 0b00000..2.10V
27253 * 0b10000..2.50V
27254 * 0b11111..2.875V
27255 */
27256#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK)
27257#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U)
27258#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U)
27259#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK)
27260#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U)
27261#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U)
27262#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK)
27263#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U)
27264#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U)
27265#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK)
27266/* @} */
27267
27268/* @name REG_2P5_SET - Regulator 2P5 Register */
27269/* @{ */
27270#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U)
27271#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U)
27272#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK)
27273#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U)
27274#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U)
27275#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK)
27276#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U)
27277#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U)
27278#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK)
27279#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U)
27280#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U)
27281#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK)
27282#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U)
27283#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U)
27284#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK)
27285#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U)
27286#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U)
27287/* OUTPUT_TRG
27288 * 0b00000..2.10V
27289 * 0b10000..2.50V
27290 * 0b11111..2.875V
27291 */
27292#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK)
27293#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U)
27294#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U)
27295#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK)
27296#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U)
27297#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U)
27298#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK)
27299#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U)
27300#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U)
27301#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK)
27302/* @} */
27303
27304/* @name REG_2P5_CLR - Regulator 2P5 Register */
27305/* @{ */
27306#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U)
27307#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U)
27308#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK)
27309#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U)
27310#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U)
27311#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK)
27312#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U)
27313#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U)
27314#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK)
27315#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U)
27316#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U)
27317#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK)
27318#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U)
27319#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U)
27320#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK)
27321#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U)
27322#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U)
27323/* OUTPUT_TRG
27324 * 0b00000..2.10V
27325 * 0b10000..2.50V
27326 * 0b11111..2.875V
27327 */
27328#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK)
27329#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U)
27330#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U)
27331#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK)
27332#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U)
27333#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U)
27334#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK)
27335#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U)
27336#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U)
27337#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK)
27338/* @} */
27339
27340/* @name REG_2P5_TOG - Regulator 2P5 Register */
27341/* @{ */
27342#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U)
27343#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U)
27344#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK)
27345#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U)
27346#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U)
27347#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK)
27348#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U)
27349#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U)
27350#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK)
27351#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U)
27352#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U)
27353#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK)
27354#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U)
27355#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U)
27356#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK)
27357#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U)
27358#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U)
27359/* OUTPUT_TRG
27360 * 0b00000..2.10V
27361 * 0b10000..2.50V
27362 * 0b11111..2.875V
27363 */
27364#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK)
27365#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U)
27366#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U)
27367#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK)
27368#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U)
27369#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U)
27370#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK)
27371#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U)
27372#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U)
27373#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK)
27374/* @} */
27375
27376/* @name REG_CORE - Digital Regulator Core Register */
27377/* @{ */
27378#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU)
27379#define PMU_REG_CORE_REG0_TARG_SHIFT (0U)
27380/* REG0_TARG
27381 * 0b00000..Power gated off
27382 * 0b00001..Target core voltage = 0.725V
27383 * 0b00010..Target core voltage = 0.750V
27384 * 0b00011..Target core voltage = 0.775V
27385 * 0b10000..Target core voltage = 1.100V
27386 * 0b11110..Target core voltage = 1.450V
27387 * 0b11111..Power FET switched full on. No regulation.
27388 */
27389#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK)
27390#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U)
27391#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U)
27392/* REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
27393 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27394 * register.
27395 * 0b0000..No adjustment
27396 * 0b0001..+ 0.25%
27397 * 0b0010..+ 0.50%
27398 * 0b0011..+ 0.75%
27399 * 0b0100..+ 1.00%
27400 * 0b0101..+ 1.25%
27401 * 0b0110..+ 1.50%
27402 * 0b0111..+ 1.75%
27403 * 0b1000..- 0.25%
27404 * 0b1001..- 0.50%
27405 * 0b1010..- 0.75%
27406 * 0b1011..- 1.00%
27407 * 0b1100..- 1.25%
27408 * 0b1101..- 1.50%
27409 * 0b1110..- 1.75%
27410 * 0b1111..- 2.00%
27411 */
27412#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK)
27413#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U)
27414#define PMU_REG_CORE_REG1_TARG_SHIFT (9U)
27415/* REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
27416 * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
27417 * of input supply limitations or load operation.
27418 * 0b00000..Power gated off
27419 * 0b00001..Target core voltage = 0.725V
27420 * 0b00010..Target core voltage = 0.750V
27421 * 0b00011..Target core voltage = 0.775V
27422 * 0b10000..Target core voltage = 1.100V
27423 * 0b11110..Target core voltage = 1.450V
27424 * 0b11111..Power FET switched full on. No regulation.
27425 */
27426#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK)
27427#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U)
27428#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U)
27429/* REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
27430 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27431 * register.
27432 * 0b0000..No adjustment
27433 * 0b0001..+ 0.25%
27434 * 0b0010..+ 0.50%
27435 * 0b0011..+ 0.75%
27436 * 0b0100..+ 1.00%
27437 * 0b0101..+ 1.25%
27438 * 0b0110..+ 1.50%
27439 * 0b0111..+ 1.75%
27440 * 0b1000..- 0.25%
27441 * 0b1001..- 0.50%
27442 * 0b1010..- 0.75%
27443 * 0b1011..- 1.00%
27444 * 0b1100..- 1.25%
27445 * 0b1101..- 1.50%
27446 * 0b1110..- 1.75%
27447 * 0b1111..- 2.00%
27448 */
27449#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK)
27450#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U)
27451#define PMU_REG_CORE_REG2_TARG_SHIFT (18U)
27452/* REG2_TARG
27453 * 0b00000..Power gated off
27454 * 0b00001..Target core voltage = 0.725V
27455 * 0b00010..Target core voltage = 0.750V
27456 * 0b00011..Target core voltage = 0.775V
27457 * 0b10000..Target core voltage = 1.100V
27458 * 0b11110..Target core voltage = 1.450V
27459 * 0b11111..Power FET switched full on. No regulation.
27460 */
27461#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK)
27462#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U)
27463#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U)
27464/* REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
27465 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27466 * register.
27467 * 0b0000..No adjustment
27468 * 0b0001..+ 0.25%
27469 * 0b0010..+ 0.50%
27470 * 0b0011..+ 0.75%
27471 * 0b0100..+ 1.00%
27472 * 0b0101..+ 1.25%
27473 * 0b0110..+ 1.50%
27474 * 0b0111..+ 1.75%
27475 * 0b1000..- 0.25%
27476 * 0b1001..- 0.50%
27477 * 0b1010..- 0.75%
27478 * 0b1011..- 1.00%
27479 * 0b1100..- 1.25%
27480 * 0b1101..- 1.50%
27481 * 0b1110..- 1.75%
27482 * 0b1111..- 2.00%
27483 */
27484#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK)
27485#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U)
27486#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U)
27487/* RAMP_RATE
27488 * 0b00..Fast
27489 * 0b01..Medium Fast
27490 * 0b10..Medium Slow
27491 * 0b11..Slow
27492 */
27493#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK)
27494#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U)
27495#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U)
27496#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK)
27497/* @} */
27498
27499/* @name REG_CORE_SET - Digital Regulator Core Register */
27500/* @{ */
27501#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU)
27502#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U)
27503/* REG0_TARG
27504 * 0b00000..Power gated off
27505 * 0b00001..Target core voltage = 0.725V
27506 * 0b00010..Target core voltage = 0.750V
27507 * 0b00011..Target core voltage = 0.775V
27508 * 0b10000..Target core voltage = 1.100V
27509 * 0b11110..Target core voltage = 1.450V
27510 * 0b11111..Power FET switched full on. No regulation.
27511 */
27512#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK)
27513#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U)
27514#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U)
27515/* REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
27516 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27517 * register.
27518 * 0b0000..No adjustment
27519 * 0b0001..+ 0.25%
27520 * 0b0010..+ 0.50%
27521 * 0b0011..+ 0.75%
27522 * 0b0100..+ 1.00%
27523 * 0b0101..+ 1.25%
27524 * 0b0110..+ 1.50%
27525 * 0b0111..+ 1.75%
27526 * 0b1000..- 0.25%
27527 * 0b1001..- 0.50%
27528 * 0b1010..- 0.75%
27529 * 0b1011..- 1.00%
27530 * 0b1100..- 1.25%
27531 * 0b1101..- 1.50%
27532 * 0b1110..- 1.75%
27533 * 0b1111..- 2.00%
27534 */
27535#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK)
27536#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U)
27537#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U)
27538/* REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
27539 * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
27540 * of input supply limitations or load operation.
27541 * 0b00000..Power gated off
27542 * 0b00001..Target core voltage = 0.725V
27543 * 0b00010..Target core voltage = 0.750V
27544 * 0b00011..Target core voltage = 0.775V
27545 * 0b10000..Target core voltage = 1.100V
27546 * 0b11110..Target core voltage = 1.450V
27547 * 0b11111..Power FET switched full on. No regulation.
27548 */
27549#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK)
27550#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U)
27551#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U)
27552/* REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
27553 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27554 * register.
27555 * 0b0000..No adjustment
27556 * 0b0001..+ 0.25%
27557 * 0b0010..+ 0.50%
27558 * 0b0011..+ 0.75%
27559 * 0b0100..+ 1.00%
27560 * 0b0101..+ 1.25%
27561 * 0b0110..+ 1.50%
27562 * 0b0111..+ 1.75%
27563 * 0b1000..- 0.25%
27564 * 0b1001..- 0.50%
27565 * 0b1010..- 0.75%
27566 * 0b1011..- 1.00%
27567 * 0b1100..- 1.25%
27568 * 0b1101..- 1.50%
27569 * 0b1110..- 1.75%
27570 * 0b1111..- 2.00%
27571 */
27572#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK)
27573#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U)
27574#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U)
27575/* REG2_TARG
27576 * 0b00000..Power gated off
27577 * 0b00001..Target core voltage = 0.725V
27578 * 0b00010..Target core voltage = 0.750V
27579 * 0b00011..Target core voltage = 0.775V
27580 * 0b10000..Target core voltage = 1.100V
27581 * 0b11110..Target core voltage = 1.450V
27582 * 0b11111..Power FET switched full on. No regulation.
27583 */
27584#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK)
27585#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U)
27586#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U)
27587/* REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
27588 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27589 * register.
27590 * 0b0000..No adjustment
27591 * 0b0001..+ 0.25%
27592 * 0b0010..+ 0.50%
27593 * 0b0011..+ 0.75%
27594 * 0b0100..+ 1.00%
27595 * 0b0101..+ 1.25%
27596 * 0b0110..+ 1.50%
27597 * 0b0111..+ 1.75%
27598 * 0b1000..- 0.25%
27599 * 0b1001..- 0.50%
27600 * 0b1010..- 0.75%
27601 * 0b1011..- 1.00%
27602 * 0b1100..- 1.25%
27603 * 0b1101..- 1.50%
27604 * 0b1110..- 1.75%
27605 * 0b1111..- 2.00%
27606 */
27607#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK)
27608#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U)
27609#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U)
27610/* RAMP_RATE
27611 * 0b00..Fast
27612 * 0b01..Medium Fast
27613 * 0b10..Medium Slow
27614 * 0b11..Slow
27615 */
27616#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK)
27617#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U)
27618#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U)
27619#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK)
27620/* @} */
27621
27622/* @name REG_CORE_CLR - Digital Regulator Core Register */
27623/* @{ */
27624#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU)
27625#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U)
27626/* REG0_TARG
27627 * 0b00000..Power gated off
27628 * 0b00001..Target core voltage = 0.725V
27629 * 0b00010..Target core voltage = 0.750V
27630 * 0b00011..Target core voltage = 0.775V
27631 * 0b10000..Target core voltage = 1.100V
27632 * 0b11110..Target core voltage = 1.450V
27633 * 0b11111..Power FET switched full on. No regulation.
27634 */
27635#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK)
27636#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U)
27637#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U)
27638/* REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
27639 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27640 * register.
27641 * 0b0000..No adjustment
27642 * 0b0001..+ 0.25%
27643 * 0b0010..+ 0.50%
27644 * 0b0011..+ 0.75%
27645 * 0b0100..+ 1.00%
27646 * 0b0101..+ 1.25%
27647 * 0b0110..+ 1.50%
27648 * 0b0111..+ 1.75%
27649 * 0b1000..- 0.25%
27650 * 0b1001..- 0.50%
27651 * 0b1010..- 0.75%
27652 * 0b1011..- 1.00%
27653 * 0b1100..- 1.25%
27654 * 0b1101..- 1.50%
27655 * 0b1110..- 1.75%
27656 * 0b1111..- 2.00%
27657 */
27658#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK)
27659#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U)
27660#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U)
27661/* REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
27662 * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
27663 * of input supply limitations or load operation.
27664 * 0b00000..Power gated off
27665 * 0b00001..Target core voltage = 0.725V
27666 * 0b00010..Target core voltage = 0.750V
27667 * 0b00011..Target core voltage = 0.775V
27668 * 0b10000..Target core voltage = 1.100V
27669 * 0b11110..Target core voltage = 1.450V
27670 * 0b11111..Power FET switched full on. No regulation.
27671 */
27672#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK)
27673#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U)
27674#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U)
27675/* REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
27676 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27677 * register.
27678 * 0b0000..No adjustment
27679 * 0b0001..+ 0.25%
27680 * 0b0010..+ 0.50%
27681 * 0b0011..+ 0.75%
27682 * 0b0100..+ 1.00%
27683 * 0b0101..+ 1.25%
27684 * 0b0110..+ 1.50%
27685 * 0b0111..+ 1.75%
27686 * 0b1000..- 0.25%
27687 * 0b1001..- 0.50%
27688 * 0b1010..- 0.75%
27689 * 0b1011..- 1.00%
27690 * 0b1100..- 1.25%
27691 * 0b1101..- 1.50%
27692 * 0b1110..- 1.75%
27693 * 0b1111..- 2.00%
27694 */
27695#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK)
27696#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U)
27697#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U)
27698/* REG2_TARG
27699 * 0b00000..Power gated off
27700 * 0b00001..Target core voltage = 0.725V
27701 * 0b00010..Target core voltage = 0.750V
27702 * 0b00011..Target core voltage = 0.775V
27703 * 0b10000..Target core voltage = 1.100V
27704 * 0b11110..Target core voltage = 1.450V
27705 * 0b11111..Power FET switched full on. No regulation.
27706 */
27707#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK)
27708#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U)
27709#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U)
27710/* REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
27711 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27712 * register.
27713 * 0b0000..No adjustment
27714 * 0b0001..+ 0.25%
27715 * 0b0010..+ 0.50%
27716 * 0b0011..+ 0.75%
27717 * 0b0100..+ 1.00%
27718 * 0b0101..+ 1.25%
27719 * 0b0110..+ 1.50%
27720 * 0b0111..+ 1.75%
27721 * 0b1000..- 0.25%
27722 * 0b1001..- 0.50%
27723 * 0b1010..- 0.75%
27724 * 0b1011..- 1.00%
27725 * 0b1100..- 1.25%
27726 * 0b1101..- 1.50%
27727 * 0b1110..- 1.75%
27728 * 0b1111..- 2.00%
27729 */
27730#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK)
27731#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U)
27732#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U)
27733/* RAMP_RATE
27734 * 0b00..Fast
27735 * 0b01..Medium Fast
27736 * 0b10..Medium Slow
27737 * 0b11..Slow
27738 */
27739#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK)
27740#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U)
27741#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U)
27742#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK)
27743/* @} */
27744
27745/* @name REG_CORE_TOG - Digital Regulator Core Register */
27746/* @{ */
27747#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU)
27748#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U)
27749/* REG0_TARG
27750 * 0b00000..Power gated off
27751 * 0b00001..Target core voltage = 0.725V
27752 * 0b00010..Target core voltage = 0.750V
27753 * 0b00011..Target core voltage = 0.775V
27754 * 0b10000..Target core voltage = 1.100V
27755 * 0b11110..Target core voltage = 1.450V
27756 * 0b11111..Power FET switched full on. No regulation.
27757 */
27758#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK)
27759#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U)
27760#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U)
27761/* REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The
27762 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27763 * register.
27764 * 0b0000..No adjustment
27765 * 0b0001..+ 0.25%
27766 * 0b0010..+ 0.50%
27767 * 0b0011..+ 0.75%
27768 * 0b0100..+ 1.00%
27769 * 0b0101..+ 1.25%
27770 * 0b0110..+ 1.50%
27771 * 0b0111..+ 1.75%
27772 * 0b1000..- 0.25%
27773 * 0b1001..- 0.50%
27774 * 0b1010..- 0.75%
27775 * 0b1011..- 1.00%
27776 * 0b1100..- 1.25%
27777 * 0b1101..- 1.50%
27778 * 0b1110..- 1.75%
27779 * 0b1111..- 2.00%
27780 */
27781#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK)
27782#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U)
27783#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U)
27784/* REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit
27785 * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because
27786 * of input supply limitations or load operation.
27787 * 0b00000..Power gated off
27788 * 0b00001..Target core voltage = 0.725V
27789 * 0b00010..Target core voltage = 0.750V
27790 * 0b00011..Target core voltage = 0.775V
27791 * 0b10000..Target core voltage = 1.100V
27792 * 0b11110..Target core voltage = 1.450V
27793 * 0b11111..Power FET switched full on. No regulation.
27794 */
27795#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK)
27796#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U)
27797#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U)
27798/* REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The
27799 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27800 * register.
27801 * 0b0000..No adjustment
27802 * 0b0001..+ 0.25%
27803 * 0b0010..+ 0.50%
27804 * 0b0011..+ 0.75%
27805 * 0b0100..+ 1.00%
27806 * 0b0101..+ 1.25%
27807 * 0b0110..+ 1.50%
27808 * 0b0111..+ 1.75%
27809 * 0b1000..- 0.25%
27810 * 0b1001..- 0.50%
27811 * 0b1010..- 0.75%
27812 * 0b1011..- 1.00%
27813 * 0b1100..- 1.25%
27814 * 0b1101..- 1.50%
27815 * 0b1110..- 1.75%
27816 * 0b1111..- 2.00%
27817 */
27818#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK)
27819#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U)
27820#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U)
27821/* REG2_TARG
27822 * 0b00000..Power gated off
27823 * 0b00001..Target core voltage = 0.725V
27824 * 0b00010..Target core voltage = 0.750V
27825 * 0b00011..Target core voltage = 0.775V
27826 * 0b10000..Target core voltage = 1.100V
27827 * 0b11110..Target core voltage = 1.450V
27828 * 0b11111..Power FET switched full on. No regulation.
27829 */
27830#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK)
27831#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U)
27832#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U)
27833/* REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The
27834 * adjustment is applied on top on any adjustment applied to the global reference in the misc0
27835 * register.
27836 * 0b0000..No adjustment
27837 * 0b0001..+ 0.25%
27838 * 0b0010..+ 0.50%
27839 * 0b0011..+ 0.75%
27840 * 0b0100..+ 1.00%
27841 * 0b0101..+ 1.25%
27842 * 0b0110..+ 1.50%
27843 * 0b0111..+ 1.75%
27844 * 0b1000..- 0.25%
27845 * 0b1001..- 0.50%
27846 * 0b1010..- 0.75%
27847 * 0b1011..- 1.00%
27848 * 0b1100..- 1.25%
27849 * 0b1101..- 1.50%
27850 * 0b1110..- 1.75%
27851 * 0b1111..- 2.00%
27852 */
27853#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK)
27854#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U)
27855#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U)
27856/* RAMP_RATE
27857 * 0b00..Fast
27858 * 0b01..Medium Fast
27859 * 0b10..Medium Slow
27860 * 0b11..Slow
27861 */
27862#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK)
27863#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U)
27864#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U)
27865#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK)
27866/* @} */
27867
27868/* @name MISC0 - Miscellaneous Register 0 */
27869/* @{ */
27870#define PMU_MISC0_REFTOP_PWD_MASK (0x1U)
27871#define PMU_MISC0_REFTOP_PWD_SHIFT (0U)
27872#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK)
27873#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
27874#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
27875/* REFTOP_SELFBIASOFF
27876 * 0b0..Uses coarse bias currents for startup
27877 * 0b1..Uses bandgap-based bias currents for best performance.
27878 */
27879#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK)
27880#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U)
27881#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U)
27882/* REFTOP_VBGADJ
27883 * 0b000..Nominal VBG
27884 * 0b001..VBG+0.78%
27885 * 0b010..VBG+1.56%
27886 * 0b011..VBG+2.34%
27887 * 0b100..VBG-0.78%
27888 * 0b101..VBG-1.56%
27889 * 0b110..VBG-2.34%
27890 * 0b111..VBG-3.12%
27891 */
27892#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK)
27893#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U)
27894#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U)
27895#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK)
27896#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
27897#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
27898/* STOP_MODE_CONFIG
27899 * 0b00..SUSPEND (DSM)
27900 * 0b01..Analog regulators are ON.
27901 * 0b10..STOP (lower power)
27902 * 0b11..STOP (very lower power)
27903 */
27904#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK)
27905#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
27906#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
27907/* DISCON_HIGH_SNVS
27908 * 0b0..Turn on the switch
27909 * 0b1..Turn off the switch
27910 */
27911#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK)
27912#define PMU_MISC0_OSC_I_MASK (0x6000U)
27913#define PMU_MISC0_OSC_I_SHIFT (13U)
27914/* OSC_I
27915 * 0b00..Nominal
27916 * 0b01..Decrease current by 12.5%
27917 * 0b10..Decrease current by 25.0%
27918 * 0b11..Decrease current by 37.5%
27919 */
27920#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK)
27921#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U)
27922#define PMU_MISC0_OSC_XTALOK_SHIFT (15U)
27923#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK)
27924#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
27925#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U)
27926#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK)
27927#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
27928#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U)
27929/* CLKGATE_CTRL
27930 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
27931 * 0b1..Prevent the logic from ever gating off the clock.
27932 */
27933#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK)
27934#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
27935#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U)
27936/* CLKGATE_DELAY
27937 * 0b000..0.5ms
27938 * 0b001..1.0ms
27939 * 0b010..2.0ms
27940 * 0b011..3.0ms
27941 * 0b100..4.0ms
27942 * 0b101..5.0ms
27943 * 0b110..6.0ms
27944 * 0b111..7.0ms
27945 */
27946#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK)
27947#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
27948#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
27949/* RTC_XTAL_SOURCE
27950 * 0b0..Internal ring oscillator
27951 * 0b1..RTC_XTAL
27952 */
27953#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK)
27954#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
27955#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U)
27956#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK)
27957#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
27958#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U)
27959/* VID_PLL_PREDIV
27960 * 0b0..Divide by 1
27961 * 0b1..Divide by 2
27962 */
27963#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK)
27964/* @} */
27965
27966/* @name MISC0_SET - Miscellaneous Register 0 */
27967/* @{ */
27968#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U)
27969#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U)
27970#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK)
27971#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
27972#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
27973/* REFTOP_SELFBIASOFF
27974 * 0b0..Uses coarse bias currents for startup
27975 * 0b1..Uses bandgap-based bias currents for best performance.
27976 */
27977#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
27978#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
27979#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
27980/* REFTOP_VBGADJ
27981 * 0b000..Nominal VBG
27982 * 0b001..VBG+0.78%
27983 * 0b010..VBG+1.56%
27984 * 0b011..VBG+2.34%
27985 * 0b100..VBG-0.78%
27986 * 0b101..VBG-1.56%
27987 * 0b110..VBG-2.34%
27988 * 0b111..VBG-3.12%
27989 */
27990#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK)
27991#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
27992#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
27993#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK)
27994#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
27995#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
27996/* STOP_MODE_CONFIG
27997 * 0b00..SUSPEND (DSM)
27998 * 0b01..Analog regulators are ON.
27999 * 0b10..STOP (lower power)
28000 * 0b11..STOP (very lower power)
28001 */
28002#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK)
28003#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
28004#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
28005/* DISCON_HIGH_SNVS
28006 * 0b0..Turn on the switch
28007 * 0b1..Turn off the switch
28008 */
28009#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK)
28010#define PMU_MISC0_SET_OSC_I_MASK (0x6000U)
28011#define PMU_MISC0_SET_OSC_I_SHIFT (13U)
28012/* OSC_I
28013 * 0b00..Nominal
28014 * 0b01..Decrease current by 12.5%
28015 * 0b10..Decrease current by 25.0%
28016 * 0b11..Decrease current by 37.5%
28017 */
28018#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK)
28019#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
28020#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U)
28021#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK)
28022#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
28023#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
28024#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK)
28025#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
28026#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
28027/* CLKGATE_CTRL
28028 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
28029 * 0b1..Prevent the logic from ever gating off the clock.
28030 */
28031#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK)
28032#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
28033#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
28034/* CLKGATE_DELAY
28035 * 0b000..0.5ms
28036 * 0b001..1.0ms
28037 * 0b010..2.0ms
28038 * 0b011..3.0ms
28039 * 0b100..4.0ms
28040 * 0b101..5.0ms
28041 * 0b110..6.0ms
28042 * 0b111..7.0ms
28043 */
28044#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK)
28045#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
28046#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
28047/* RTC_XTAL_SOURCE
28048 * 0b0..Internal ring oscillator
28049 * 0b1..RTC_XTAL
28050 */
28051#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK)
28052#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
28053#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
28054#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK)
28055#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
28056#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
28057/* VID_PLL_PREDIV
28058 * 0b0..Divide by 1
28059 * 0b1..Divide by 2
28060 */
28061#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK)
28062/* @} */
28063
28064/* @name MISC0_CLR - Miscellaneous Register 0 */
28065/* @{ */
28066#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
28067#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
28068#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK)
28069#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
28070#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
28071/* REFTOP_SELFBIASOFF
28072 * 0b0..Uses coarse bias currents for startup
28073 * 0b1..Uses bandgap-based bias currents for best performance.
28074 */
28075#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
28076#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
28077#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
28078/* REFTOP_VBGADJ
28079 * 0b000..Nominal VBG
28080 * 0b001..VBG+0.78%
28081 * 0b010..VBG+1.56%
28082 * 0b011..VBG+2.34%
28083 * 0b100..VBG-0.78%
28084 * 0b101..VBG-1.56%
28085 * 0b110..VBG-2.34%
28086 * 0b111..VBG-3.12%
28087 */
28088#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK)
28089#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
28090#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
28091#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK)
28092#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
28093#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
28094/* STOP_MODE_CONFIG
28095 * 0b00..SUSPEND (DSM)
28096 * 0b01..Analog regulators are ON.
28097 * 0b10..STOP (lower power)
28098 * 0b11..STOP (very lower power)
28099 */
28100#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK)
28101#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
28102#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
28103/* DISCON_HIGH_SNVS
28104 * 0b0..Turn on the switch
28105 * 0b1..Turn off the switch
28106 */
28107#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
28108#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U)
28109#define PMU_MISC0_CLR_OSC_I_SHIFT (13U)
28110/* OSC_I
28111 * 0b00..Nominal
28112 * 0b01..Decrease current by 12.5%
28113 * 0b10..Decrease current by 25.0%
28114 * 0b11..Decrease current by 37.5%
28115 */
28116#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK)
28117#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
28118#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
28119#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK)
28120#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
28121#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
28122#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK)
28123#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
28124#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
28125/* CLKGATE_CTRL
28126 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
28127 * 0b1..Prevent the logic from ever gating off the clock.
28128 */
28129#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK)
28130#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
28131#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
28132/* CLKGATE_DELAY
28133 * 0b000..0.5ms
28134 * 0b001..1.0ms
28135 * 0b010..2.0ms
28136 * 0b011..3.0ms
28137 * 0b100..4.0ms
28138 * 0b101..5.0ms
28139 * 0b110..6.0ms
28140 * 0b111..7.0ms
28141 */
28142#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK)
28143#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
28144#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
28145/* RTC_XTAL_SOURCE
28146 * 0b0..Internal ring oscillator
28147 * 0b1..RTC_XTAL
28148 */
28149#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
28150#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
28151#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
28152#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK)
28153#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
28154#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
28155/* VID_PLL_PREDIV
28156 * 0b0..Divide by 1
28157 * 0b1..Divide by 2
28158 */
28159#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK)
28160/* @} */
28161
28162/* @name MISC0_TOG - Miscellaneous Register 0 */
28163/* @{ */
28164#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
28165#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
28166#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK)
28167#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
28168#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
28169/* REFTOP_SELFBIASOFF
28170 * 0b0..Uses coarse bias currents for startup
28171 * 0b1..Uses bandgap-based bias currents for best performance.
28172 */
28173#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
28174#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
28175#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
28176/* REFTOP_VBGADJ
28177 * 0b000..Nominal VBG
28178 * 0b001..VBG+0.78%
28179 * 0b010..VBG+1.56%
28180 * 0b011..VBG+2.34%
28181 * 0b100..VBG-0.78%
28182 * 0b101..VBG-1.56%
28183 * 0b110..VBG-2.34%
28184 * 0b111..VBG-3.12%
28185 */
28186#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK)
28187#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
28188#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
28189#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK)
28190#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
28191#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
28192/* STOP_MODE_CONFIG
28193 * 0b00..SUSPEND (DSM)
28194 * 0b01..Analog regulators are ON.
28195 * 0b10..STOP (lower power)
28196 * 0b11..STOP (very lower power)
28197 */
28198#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK)
28199#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
28200#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
28201/* DISCON_HIGH_SNVS
28202 * 0b0..Turn on the switch
28203 * 0b1..Turn off the switch
28204 */
28205#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
28206#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U)
28207#define PMU_MISC0_TOG_OSC_I_SHIFT (13U)
28208/* OSC_I
28209 * 0b00..Nominal
28210 * 0b01..Decrease current by 12.5%
28211 * 0b10..Decrease current by 25.0%
28212 * 0b11..Decrease current by 37.5%
28213 */
28214#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK)
28215#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
28216#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
28217#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK)
28218#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
28219#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
28220#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK)
28221#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
28222#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
28223/* CLKGATE_CTRL
28224 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
28225 * 0b1..Prevent the logic from ever gating off the clock.
28226 */
28227#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK)
28228#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
28229#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
28230/* CLKGATE_DELAY
28231 * 0b000..0.5ms
28232 * 0b001..1.0ms
28233 * 0b010..2.0ms
28234 * 0b011..3.0ms
28235 * 0b100..4.0ms
28236 * 0b101..5.0ms
28237 * 0b110..6.0ms
28238 * 0b111..7.0ms
28239 */
28240#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK)
28241#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
28242#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
28243/* RTC_XTAL_SOURCE
28244 * 0b0..Internal ring oscillator
28245 * 0b1..RTC_XTAL
28246 */
28247#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
28248#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
28249#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
28250#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK)
28251#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
28252#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
28253/* VID_PLL_PREDIV
28254 * 0b0..Divide by 1
28255 * 0b1..Divide by 2
28256 */
28257#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK)
28258/* @} */
28259
28260/* @name MISC1 - Miscellaneous Register 1 */
28261/* @{ */
28262#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
28263#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
28264/* LVDS1_CLK_SEL
28265 * 0b00000..Arm PLL
28266 * 0b00001..System PLL
28267 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
28268 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
28269 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
28270 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
28271 * 0b00110..Audio PLL
28272 * 0b00111..Video PLL
28273 * 0b01001..ethernet ref clock (ENET_PLL)
28274 * 0b01100..USB1 PLL clock
28275 * 0b01101..USB2 PLL clock
28276 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
28277 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
28278 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
28279 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
28280 * 0b10010..xtal (24M)
28281 */
28282#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK)
28283#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U)
28284#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U)
28285/* LVDS2_CLK_SEL
28286 * 0b00000..Arm PLL
28287 * 0b00001..System PLL
28288 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
28289 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
28290 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
28291 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
28292 * 0b00110..Audio PLL
28293 * 0b00111..Video PLL
28294 * 0b01000..MLB PLL
28295 * 0b01001..ethernet ref clock (ENET_PLL)
28296 * 0b01010..PCIe ref clock (125M)
28297 * 0b01011..SATA ref clock (100M)
28298 * 0b01100..USB1 PLL clock
28299 * 0b01101..USB2 PLL clock
28300 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
28301 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
28302 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
28303 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
28304 * 0b10010..xtal (24M)
28305 * 0b10011..LVDS1 (loopback)
28306 * 0b10100..LVDS2 (not useful)
28307 */
28308#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK)
28309#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
28310#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
28311#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK)
28312#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U)
28313#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U)
28314#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK)
28315#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
28316#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
28317#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK)
28318#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U)
28319#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U)
28320#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK)
28321#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
28322#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
28323#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK)
28324#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
28325#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
28326#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK)
28327#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
28328#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
28329#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK)
28330#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
28331#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U)
28332#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK)
28333#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
28334#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
28335#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK)
28336#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
28337#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U)
28338#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK)
28339#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
28340#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U)
28341#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK)
28342/* @} */
28343
28344/* @name MISC1_SET - Miscellaneous Register 1 */
28345/* @{ */
28346#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
28347#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
28348/* LVDS1_CLK_SEL
28349 * 0b00000..Arm PLL
28350 * 0b00001..System PLL
28351 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
28352 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
28353 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
28354 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
28355 * 0b00110..Audio PLL
28356 * 0b00111..Video PLL
28357 * 0b01001..ethernet ref clock (ENET_PLL)
28358 * 0b01100..USB1 PLL clock
28359 * 0b01101..USB2 PLL clock
28360 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
28361 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
28362 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
28363 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
28364 * 0b10010..xtal (24M)
28365 */
28366#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK)
28367#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U)
28368#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U)
28369/* LVDS2_CLK_SEL
28370 * 0b00000..Arm PLL
28371 * 0b00001..System PLL
28372 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
28373 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
28374 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
28375 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
28376 * 0b00110..Audio PLL
28377 * 0b00111..Video PLL
28378 * 0b01000..MLB PLL
28379 * 0b01001..ethernet ref clock (ENET_PLL)
28380 * 0b01010..PCIe ref clock (125M)
28381 * 0b01011..SATA ref clock (100M)
28382 * 0b01100..USB1 PLL clock
28383 * 0b01101..USB2 PLL clock
28384 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
28385 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
28386 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
28387 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
28388 * 0b10010..xtal (24M)
28389 * 0b10011..LVDS1 (loopback)
28390 * 0b10100..LVDS2 (not useful)
28391 */
28392#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK)
28393#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
28394#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
28395#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK)
28396#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U)
28397#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U)
28398#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK)
28399#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
28400#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
28401#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK)
28402#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U)
28403#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U)
28404#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK)
28405#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
28406#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
28407#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
28408#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
28409#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
28410#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
28411#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
28412#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
28413#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK)
28414#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
28415#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
28416#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK)
28417#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
28418#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
28419#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK)
28420#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
28421#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
28422#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK)
28423#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
28424#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
28425#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK)
28426/* @} */
28427
28428/* @name MISC1_CLR - Miscellaneous Register 1 */
28429/* @{ */
28430#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
28431#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
28432/* LVDS1_CLK_SEL
28433 * 0b00000..Arm PLL
28434 * 0b00001..System PLL
28435 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
28436 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
28437 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
28438 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
28439 * 0b00110..Audio PLL
28440 * 0b00111..Video PLL
28441 * 0b01001..ethernet ref clock (ENET_PLL)
28442 * 0b01100..USB1 PLL clock
28443 * 0b01101..USB2 PLL clock
28444 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
28445 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
28446 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
28447 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
28448 * 0b10010..xtal (24M)
28449 */
28450#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK)
28451#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U)
28452#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U)
28453/* LVDS2_CLK_SEL
28454 * 0b00000..Arm PLL
28455 * 0b00001..System PLL
28456 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
28457 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
28458 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
28459 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
28460 * 0b00110..Audio PLL
28461 * 0b00111..Video PLL
28462 * 0b01000..MLB PLL
28463 * 0b01001..ethernet ref clock (ENET_PLL)
28464 * 0b01010..PCIe ref clock (125M)
28465 * 0b01011..SATA ref clock (100M)
28466 * 0b01100..USB1 PLL clock
28467 * 0b01101..USB2 PLL clock
28468 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
28469 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
28470 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
28471 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
28472 * 0b10010..xtal (24M)
28473 * 0b10011..LVDS1 (loopback)
28474 * 0b10100..LVDS2 (not useful)
28475 */
28476#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK)
28477#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
28478#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
28479#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK)
28480#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U)
28481#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U)
28482#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK)
28483#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
28484#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
28485#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK)
28486#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U)
28487#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U)
28488#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK)
28489#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
28490#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
28491#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
28492#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
28493#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
28494#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
28495#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
28496#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
28497#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK)
28498#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
28499#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
28500#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK)
28501#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
28502#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
28503#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK)
28504#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
28505#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
28506#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK)
28507#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
28508#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
28509#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK)
28510/* @} */
28511
28512/* @name MISC1_TOG - Miscellaneous Register 1 */
28513/* @{ */
28514#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
28515#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
28516/* LVDS1_CLK_SEL
28517 * 0b00000..Arm PLL
28518 * 0b00001..System PLL
28519 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
28520 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
28521 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
28522 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
28523 * 0b00110..Audio PLL
28524 * 0b00111..Video PLL
28525 * 0b01001..ethernet ref clock (ENET_PLL)
28526 * 0b01100..USB1 PLL clock
28527 * 0b01101..USB2 PLL clock
28528 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
28529 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
28530 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
28531 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
28532 * 0b10010..xtal (24M)
28533 */
28534#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK)
28535#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U)
28536#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U)
28537/* LVDS2_CLK_SEL
28538 * 0b00000..Arm PLL
28539 * 0b00001..System PLL
28540 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
28541 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
28542 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
28543 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
28544 * 0b00110..Audio PLL
28545 * 0b00111..Video PLL
28546 * 0b01000..MLB PLL
28547 * 0b01001..ethernet ref clock (ENET_PLL)
28548 * 0b01010..PCIe ref clock (125M)
28549 * 0b01011..SATA ref clock (100M)
28550 * 0b01100..USB1 PLL clock
28551 * 0b01101..USB2 PLL clock
28552 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
28553 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
28554 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
28555 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
28556 * 0b10010..xtal (24M)
28557 * 0b10011..LVDS1 (loopback)
28558 * 0b10100..LVDS2 (not useful)
28559 */
28560#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK)
28561#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
28562#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
28563#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK)
28564#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U)
28565#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U)
28566#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK)
28567#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
28568#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
28569#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK)
28570#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U)
28571#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U)
28572#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK)
28573#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
28574#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
28575#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
28576#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
28577#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
28578#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
28579#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
28580#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
28581#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK)
28582#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
28583#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
28584#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK)
28585#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
28586#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
28587#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK)
28588#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
28589#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
28590#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK)
28591#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
28592#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
28593#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK)
28594/* @} */
28595
28596/* @name MISC2 - Miscellaneous Control Register */
28597/* @{ */
28598#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U)
28599#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U)
28600/* REG0_BO_OFFSET
28601 * 0b100..Brownout offset = 0.100V
28602 * 0b111..Brownout offset = 0.175V
28603 */
28604#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK)
28605#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U)
28606#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U)
28607/* REG0_BO_STATUS
28608 * 0b1..Brownout, supply is below target minus brownout offset.
28609 */
28610#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK)
28611#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U)
28612#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U)
28613#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK)
28614#define PMU_MISC2_PLL3_disable_MASK (0x80U)
28615#define PMU_MISC2_PLL3_disable_SHIFT (7U)
28616#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK)
28617#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U)
28618#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U)
28619/* REG1_BO_OFFSET
28620 * 0b100..Brownout offset = 0.100V
28621 * 0b111..Brownout offset = 0.175V
28622 */
28623#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK)
28624#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U)
28625#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U)
28626/* REG1_BO_STATUS
28627 * 0b1..Brownout, supply is below target minus brownout offset.
28628 */
28629#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK)
28630#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
28631#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U)
28632#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK)
28633#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
28634#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
28635/* AUDIO_DIV_LSB
28636 * 0b0..divide by 1 (Default)
28637 * 0b1..divide by 2
28638 */
28639#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK)
28640#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
28641#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U)
28642/* REG2_BO_OFFSET
28643 * 0b100..Brownout offset = 0.100V
28644 * 0b111..Brownout offset = 0.175V
28645 */
28646#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK)
28647#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U)
28648#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U)
28649#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK)
28650#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
28651#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U)
28652#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK)
28653#define PMU_MISC2_REG2_OK_MASK (0x400000U)
28654#define PMU_MISC2_REG2_OK_SHIFT (22U)
28655#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK)
28656#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
28657#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
28658/* AUDIO_DIV_MSB
28659 * 0b0..divide by 1 (Default)
28660 * 0b1..divide by 2
28661 */
28662#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK)
28663#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
28664#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U)
28665/* REG0_STEP_TIME
28666 * 0b00..64
28667 * 0b01..128
28668 * 0b10..256
28669 * 0b11..512
28670 */
28671#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK)
28672#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
28673#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U)
28674/* REG1_STEP_TIME
28675 * 0b00..64
28676 * 0b01..128
28677 * 0b10..256
28678 * 0b11..512
28679 */
28680#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK)
28681#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
28682#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U)
28683/* REG2_STEP_TIME
28684 * 0b00..64
28685 * 0b01..128
28686 * 0b10..256
28687 * 0b11..512
28688 */
28689#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK)
28690#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U)
28691#define PMU_MISC2_VIDEO_DIV_SHIFT (30U)
28692/* VIDEO_DIV
28693 * 0b00..divide by 1 (Default)
28694 * 0b01..divide by 2
28695 * 0b10..divide by 1
28696 * 0b11..divide by 4
28697 */
28698#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK)
28699/* @} */
28700
28701/* @name MISC2_SET - Miscellaneous Control Register */
28702/* @{ */
28703#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
28704#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
28705/* REG0_BO_OFFSET
28706 * 0b100..Brownout offset = 0.100V
28707 * 0b111..Brownout offset = 0.175V
28708 */
28709#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK)
28710#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
28711#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
28712/* REG0_BO_STATUS
28713 * 0b1..Brownout, supply is below target minus brownout offset.
28714 */
28715#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK)
28716#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
28717#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
28718#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK)
28719#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U)
28720#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U)
28721#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK)
28722#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
28723#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
28724/* REG1_BO_OFFSET
28725 * 0b100..Brownout offset = 0.100V
28726 * 0b111..Brownout offset = 0.175V
28727 */
28728#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK)
28729#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
28730#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
28731/* REG1_BO_STATUS
28732 * 0b1..Brownout, supply is below target minus brownout offset.
28733 */
28734#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK)
28735#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
28736#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
28737#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK)
28738#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
28739#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
28740/* AUDIO_DIV_LSB
28741 * 0b0..divide by 1 (Default)
28742 * 0b1..divide by 2
28743 */
28744#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK)
28745#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
28746#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
28747/* REG2_BO_OFFSET
28748 * 0b100..Brownout offset = 0.100V
28749 * 0b111..Brownout offset = 0.175V
28750 */
28751#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK)
28752#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
28753#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
28754#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK)
28755#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
28756#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
28757#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK)
28758#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U)
28759#define PMU_MISC2_SET_REG2_OK_SHIFT (22U)
28760#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK)
28761#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
28762#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
28763/* AUDIO_DIV_MSB
28764 * 0b0..divide by 1 (Default)
28765 * 0b1..divide by 2
28766 */
28767#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK)
28768#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
28769#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
28770/* REG0_STEP_TIME
28771 * 0b00..64
28772 * 0b01..128
28773 * 0b10..256
28774 * 0b11..512
28775 */
28776#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK)
28777#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
28778#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
28779/* REG1_STEP_TIME
28780 * 0b00..64
28781 * 0b01..128
28782 * 0b10..256
28783 * 0b11..512
28784 */
28785#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK)
28786#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
28787#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
28788/* REG2_STEP_TIME
28789 * 0b00..64
28790 * 0b01..128
28791 * 0b10..256
28792 * 0b11..512
28793 */
28794#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK)
28795#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
28796#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U)
28797/* VIDEO_DIV
28798 * 0b00..divide by 1 (Default)
28799 * 0b01..divide by 2
28800 * 0b10..divide by 1
28801 * 0b11..divide by 4
28802 */
28803#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK)
28804/* @} */
28805
28806/* @name MISC2_CLR - Miscellaneous Control Register */
28807/* @{ */
28808#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
28809#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
28810/* REG0_BO_OFFSET
28811 * 0b100..Brownout offset = 0.100V
28812 * 0b111..Brownout offset = 0.175V
28813 */
28814#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK)
28815#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
28816#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
28817/* REG0_BO_STATUS
28818 * 0b1..Brownout, supply is below target minus brownout offset.
28819 */
28820#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK)
28821#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
28822#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
28823#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK)
28824#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U)
28825#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U)
28826#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK)
28827#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
28828#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
28829/* REG1_BO_OFFSET
28830 * 0b100..Brownout offset = 0.100V
28831 * 0b111..Brownout offset = 0.175V
28832 */
28833#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK)
28834#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
28835#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
28836/* REG1_BO_STATUS
28837 * 0b1..Brownout, supply is below target minus brownout offset.
28838 */
28839#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK)
28840#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
28841#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
28842#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK)
28843#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
28844#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
28845/* AUDIO_DIV_LSB
28846 * 0b0..divide by 1 (Default)
28847 * 0b1..divide by 2
28848 */
28849#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK)
28850#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
28851#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
28852/* REG2_BO_OFFSET
28853 * 0b100..Brownout offset = 0.100V
28854 * 0b111..Brownout offset = 0.175V
28855 */
28856#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK)
28857#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
28858#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
28859#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK)
28860#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
28861#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
28862#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK)
28863#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U)
28864#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U)
28865#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK)
28866#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
28867#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
28868/* AUDIO_DIV_MSB
28869 * 0b0..divide by 1 (Default)
28870 * 0b1..divide by 2
28871 */
28872#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK)
28873#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
28874#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
28875/* REG0_STEP_TIME
28876 * 0b00..64
28877 * 0b01..128
28878 * 0b10..256
28879 * 0b11..512
28880 */
28881#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK)
28882#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
28883#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
28884/* REG1_STEP_TIME
28885 * 0b00..64
28886 * 0b01..128
28887 * 0b10..256
28888 * 0b11..512
28889 */
28890#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK)
28891#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
28892#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
28893/* REG2_STEP_TIME
28894 * 0b00..64
28895 * 0b01..128
28896 * 0b10..256
28897 * 0b11..512
28898 */
28899#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK)
28900#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
28901#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
28902/* VIDEO_DIV
28903 * 0b00..divide by 1 (Default)
28904 * 0b01..divide by 2
28905 * 0b10..divide by 1
28906 * 0b11..divide by 4
28907 */
28908#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK)
28909/* @} */
28910
28911/* @name MISC2_TOG - Miscellaneous Control Register */
28912/* @{ */
28913#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
28914#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
28915/* REG0_BO_OFFSET
28916 * 0b100..Brownout offset = 0.100V
28917 * 0b111..Brownout offset = 0.175V
28918 */
28919#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK)
28920#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
28921#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
28922/* REG0_BO_STATUS
28923 * 0b1..Brownout, supply is below target minus brownout offset.
28924 */
28925#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK)
28926#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
28927#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
28928#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK)
28929#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U)
28930#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U)
28931#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK)
28932#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
28933#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
28934/* REG1_BO_OFFSET
28935 * 0b100..Brownout offset = 0.100V
28936 * 0b111..Brownout offset = 0.175V
28937 */
28938#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK)
28939#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
28940#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
28941/* REG1_BO_STATUS
28942 * 0b1..Brownout, supply is below target minus brownout offset.
28943 */
28944#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK)
28945#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
28946#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
28947#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK)
28948#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
28949#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
28950/* AUDIO_DIV_LSB
28951 * 0b0..divide by 1 (Default)
28952 * 0b1..divide by 2
28953 */
28954#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK)
28955#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
28956#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
28957/* REG2_BO_OFFSET
28958 * 0b100..Brownout offset = 0.100V
28959 * 0b111..Brownout offset = 0.175V
28960 */
28961#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK)
28962#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
28963#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
28964#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK)
28965#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
28966#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
28967#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK)
28968#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U)
28969#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U)
28970#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK)
28971#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
28972#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
28973/* AUDIO_DIV_MSB
28974 * 0b0..divide by 1 (Default)
28975 * 0b1..divide by 2
28976 */
28977#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK)
28978#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
28979#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
28980/* REG0_STEP_TIME
28981 * 0b00..64
28982 * 0b01..128
28983 * 0b10..256
28984 * 0b11..512
28985 */
28986#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK)
28987#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
28988#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
28989/* REG1_STEP_TIME
28990 * 0b00..64
28991 * 0b01..128
28992 * 0b10..256
28993 * 0b11..512
28994 */
28995#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK)
28996#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
28997#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
28998/* REG2_STEP_TIME
28999 * 0b00..64
29000 * 0b01..128
29001 * 0b10..256
29002 * 0b11..512
29003 */
29004#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK)
29005#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
29006#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
29007/* VIDEO_DIV
29008 * 0b00..divide by 1 (Default)
29009 * 0b01..divide by 2
29010 * 0b10..divide by 1
29011 * 0b11..divide by 4
29012 */
29013#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK)
29014/* @} */
29015
29016
29017/*
29018 * @}
29019 */ /* end of group PMU_Register_Masks */
29020
29021
29022/* PMU - Peripheral instance base addresses */
29023/* Peripheral PMU base address */
29024#define PMU_BASE (0x400D8000u)
29025/* Peripheral PMU base pointer */
29026#define PMU ((PMU_Type *)PMU_BASE)
29027/* Array initializer of PMU peripheral base addresses */
29028#define PMU_BASE_ADDRS { PMU_BASE }
29029/* Array initializer of PMU peripheral base pointers */
29030#define PMU_BASE_PTRS { PMU }
29031
29032/*
29033 * @}
29034 */ /* end of group PMU_Peripheral_Access_Layer */
29035
29036
29037/* ----------------------------------------------------------------------------
29038 -- PWM Peripheral Access Layer
29039 ---------------------------------------------------------------------------- */
29040
29041/*
29042 * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
29043 * @{
29044 */
29045
29046/* PWM - Register Layout Typedef */
29047typedef struct {
29048 struct { /* offset: 0x0, array step: 0x60 */
29049 __I uint16_t CNT;
29050 __IO uint16_t INIT;
29051 __IO uint16_t CTRL2;
29052 __IO uint16_t CTRL;
29053 uint8_t RESERVED_0[2];
29054 __IO uint16_t VAL0;
29055 __IO uint16_t FRACVAL1;
29056 __IO uint16_t VAL1;
29057 __IO uint16_t FRACVAL2;
29058 __IO uint16_t VAL2;
29059 __IO uint16_t FRACVAL3;
29060 __IO uint16_t VAL3;
29061 __IO uint16_t FRACVAL4;
29062 __IO uint16_t VAL4;
29063 __IO uint16_t FRACVAL5;
29064 __IO uint16_t VAL5;
29065 __IO uint16_t FRCTRL;
29066 __IO uint16_t OCTRL;
29067 __IO uint16_t STS;
29068 __IO uint16_t INTEN;
29069 __IO uint16_t DMAEN;
29070 __IO uint16_t TCTRL;
29071 __IO uint16_t DISMAP[2];
29072 __IO uint16_t DTCNT0;
29073 __IO uint16_t DTCNT1;
29074 __IO uint16_t CAPTCTRLA;
29075 __IO uint16_t CAPTCOMPA;
29076 __IO uint16_t CAPTCTRLB;
29077 __IO uint16_t CAPTCOMPB;
29078 __IO uint16_t CAPTCTRLX;
29079 __IO uint16_t CAPTCOMPX;
29080 __I uint16_t CVAL0;
29081 __I uint16_t CVAL0CYC;
29082 __I uint16_t CVAL1;
29083 __I uint16_t CVAL1CYC;
29084 __I uint16_t CVAL2;
29085 __I uint16_t CVAL2CYC;
29086 __I uint16_t CVAL3;
29087 __I uint16_t CVAL3CYC;
29088 __I uint16_t CVAL4;
29089 __I uint16_t CVAL4CYC;
29090 __I uint16_t CVAL5;
29091 __I uint16_t CVAL5CYC;
29092 uint8_t RESERVED_1[8];
29093 } SM[4];
29094 __IO uint16_t OUTEN;
29095 __IO uint16_t MASK;
29096 __IO uint16_t SWCOUT;
29097 __IO uint16_t DTSRCSEL;
29098 __IO uint16_t MCTRL;
29099 __IO uint16_t MCTRL2;
29100 __IO uint16_t FCTRL;
29101 __IO uint16_t FSTS;
29102 __IO uint16_t FFILT;
29103 __IO uint16_t FTST;
29104 __IO uint16_t FCTRL2;
29105} PWM_Type;
29106
29107/* ----------------------------------------------------------------------------
29108 -- PWM Register Masks
29109 ---------------------------------------------------------------------------- */
29110
29111/*
29112 * @addtogroup PWM_Register_Masks PWM Register Masks
29113 * @{
29114 */
29115
29116/* @name CNT - Counter Register */
29117/* @{ */
29118#define PWM_CNT_CNT_MASK (0xFFFFU)
29119#define PWM_CNT_CNT_SHIFT (0U)
29120#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
29121/* @} */
29122
29123/* The count of PWM_CNT */
29124#define PWM_CNT_COUNT (4U)
29125
29126/* @name INIT - Initial Count Register */
29127/* @{ */
29128#define PWM_INIT_INIT_MASK (0xFFFFU)
29129#define PWM_INIT_INIT_SHIFT (0U)
29130#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
29131/* @} */
29132
29133/* The count of PWM_INIT */
29134#define PWM_INIT_COUNT (4U)
29135
29136/* @name CTRL2 - Control 2 Register */
29137/* @{ */
29138#define PWM_CTRL2_CLK_SEL_MASK (0x3U)
29139#define PWM_CTRL2_CLK_SEL_SHIFT (0U)
29140/* CLK_SEL - Clock Source Select
29141 * 0b00..The IPBus clock is used as the clock for the local prescaler and counter.
29142 * 0b01..EXT_CLK is used as the clock for the local prescaler and counter.
29143 * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
29144 * setting should not be used in submodule 0 as it will force the clock to logic 0.
29145 * 0b11..reserved
29146 */
29147#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
29148#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
29149#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
29150/* RELOAD_SEL - Reload Source Select
29151 * 0b0..The local RELOAD signal is used to reload registers.
29152 * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
29153 * in submodule 0 as it will force the RELOAD signal to logic 0.
29154 */
29155#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
29156#define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
29157#define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
29158/* FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
29159 * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
29160 * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
29161 * submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
29162 * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
29163 * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
29164 * not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
29165 * 0b100..The local sync signal from this submodule is used to force updates.
29166 * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
29167 * submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
29168 * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
29169 * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
29170 */
29171#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
29172#define PWM_CTRL2_FORCE_MASK (0x40U)
29173#define PWM_CTRL2_FORCE_SHIFT (6U)
29174#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
29175#define PWM_CTRL2_FRCEN_MASK (0x80U)
29176#define PWM_CTRL2_FRCEN_SHIFT (7U)
29177/* FRCEN - FRCEN
29178 * 0b0..Initialization from a FORCE_OUT is disabled.
29179 * 0b1..Initialization from a FORCE_OUT is enabled.
29180 */
29181#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
29182#define PWM_CTRL2_INIT_SEL_MASK (0x300U)
29183#define PWM_CTRL2_INIT_SEL_SHIFT (8U)
29184/* INIT_SEL - Initialization Control Select
29185 * 0b00..Local sync (PWM_X) causes initialization.
29186 * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
29187 * it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master
29188 * reload occurs.
29189 * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it
29190 * will force the INIT signal to logic 0.
29191 * 0b11..EXT_SYNC causes initialization.
29192 */
29193#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
29194#define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
29195#define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
29196#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
29197#define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
29198#define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
29199#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
29200#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
29201#define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
29202#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
29203#define PWM_CTRL2_INDEP_MASK (0x2000U)
29204#define PWM_CTRL2_INDEP_SHIFT (13U)
29205/* INDEP - Independent or Complementary Pair Operation
29206 * 0b0..PWM_A and PWM_B form a complementary PWM pair.
29207 * 0b1..PWM_A and PWM_B outputs are independent PWMs.
29208 */
29209#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
29210#define PWM_CTRL2_WAITEN_MASK (0x4000U)
29211#define PWM_CTRL2_WAITEN_SHIFT (14U)
29212#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
29213#define PWM_CTRL2_DBGEN_MASK (0x8000U)
29214#define PWM_CTRL2_DBGEN_SHIFT (15U)
29215#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
29216/* @} */
29217
29218/* The count of PWM_CTRL2 */
29219#define PWM_CTRL2_COUNT (4U)
29220
29221/* @name CTRL - Control Register */
29222/* @{ */
29223#define PWM_CTRL_DBLEN_MASK (0x1U)
29224#define PWM_CTRL_DBLEN_SHIFT (0U)
29225/* DBLEN - Double Switching Enable
29226 * 0b0..Double switching disabled.
29227 * 0b1..Double switching enabled.
29228 */
29229#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
29230#define PWM_CTRL_DBLX_MASK (0x2U)
29231#define PWM_CTRL_DBLX_SHIFT (1U)
29232/* DBLX - PWMX Double Switching Enable
29233 * 0b0..PWMX double pulse disabled.
29234 * 0b1..PWMX double pulse enabled.
29235 */
29236#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
29237#define PWM_CTRL_LDMOD_MASK (0x4U)
29238#define PWM_CTRL_LDMOD_SHIFT (2U)
29239/* LDMOD - Load Mode Select
29240 * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
29241 * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
29242 * In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
29243 */
29244#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
29245#define PWM_CTRL_SPLIT_MASK (0x8U)
29246#define PWM_CTRL_SPLIT_SHIFT (3U)
29247/* SPLIT - Split the DBLPWM signal to PWMA and PWMB
29248 * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses.
29249 * 0b1..DBLPWM is split to PWMA and PWMB.
29250 */
29251#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
29252#define PWM_CTRL_PRSC_MASK (0x70U)
29253#define PWM_CTRL_PRSC_SHIFT (4U)
29254/* PRSC - Prescaler
29255 * 0b000..PWM clock frequency = fclk
29256 * 0b001..PWM clock frequency = fclk/2
29257 * 0b010..PWM clock frequency = fclk/4
29258 * 0b011..PWM clock frequency = fclk/8
29259 * 0b100..PWM clock frequency = fclk/16
29260 * 0b101..PWM clock frequency = fclk/32
29261 * 0b110..PWM clock frequency = fclk/64
29262 * 0b111..PWM clock frequency = fclk/128
29263 */
29264#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
29265#define PWM_CTRL_COMPMODE_MASK (0x80U)
29266#define PWM_CTRL_COMPMODE_SHIFT (7U)
29267/* COMPMODE - Compare Mode
29268 * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
29269 * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA
29270 * output that is high at the end of a period will maintain this state until a match with VAL3 clears the
29271 * output in the following period.
29272 * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
29273 * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
29274 * values. This implies that a PWMA output that is high at the end of a period could go low at the start of the
29275 * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
29276 */
29277#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
29278#define PWM_CTRL_DT_MASK (0x300U)
29279#define PWM_CTRL_DT_SHIFT (8U)
29280#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
29281#define PWM_CTRL_FULL_MASK (0x400U)
29282#define PWM_CTRL_FULL_SHIFT (10U)
29283/* FULL - Full Cycle Reload
29284 * 0b0..Full-cycle reloads disabled.
29285 * 0b1..Full-cycle reloads enabled.
29286 */
29287#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
29288#define PWM_CTRL_HALF_MASK (0x800U)
29289#define PWM_CTRL_HALF_SHIFT (11U)
29290/* HALF - Half Cycle Reload
29291 * 0b0..Half-cycle reloads disabled.
29292 * 0b1..Half-cycle reloads enabled.
29293 */
29294#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
29295#define PWM_CTRL_LDFQ_MASK (0xF000U)
29296#define PWM_CTRL_LDFQ_SHIFT (12U)
29297/* LDFQ - Load Frequency
29298 * 0b0000..Every PWM opportunity
29299 * 0b0001..Every 2 PWM opportunities
29300 * 0b0010..Every 3 PWM opportunities
29301 * 0b0011..Every 4 PWM opportunities
29302 * 0b0100..Every 5 PWM opportunities
29303 * 0b0101..Every 6 PWM opportunities
29304 * 0b0110..Every 7 PWM opportunities
29305 * 0b0111..Every 8 PWM opportunities
29306 * 0b1000..Every 9 PWM opportunities
29307 * 0b1001..Every 10 PWM opportunities
29308 * 0b1010..Every 11 PWM opportunities
29309 * 0b1011..Every 12 PWM opportunities
29310 * 0b1100..Every 13 PWM opportunities
29311 * 0b1101..Every 14 PWM opportunities
29312 * 0b1110..Every 15 PWM opportunities
29313 * 0b1111..Every 16 PWM opportunities
29314 */
29315#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
29316/* @} */
29317
29318/* The count of PWM_CTRL */
29319#define PWM_CTRL_COUNT (4U)
29320
29321/* @name VAL0 - Value Register 0 */
29322/* @{ */
29323#define PWM_VAL0_VAL0_MASK (0xFFFFU)
29324#define PWM_VAL0_VAL0_SHIFT (0U)
29325#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
29326/* @} */
29327
29328/* The count of PWM_VAL0 */
29329#define PWM_VAL0_COUNT (4U)
29330
29331/* @name FRACVAL1 - Fractional Value Register 1 */
29332/* @{ */
29333#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
29334#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
29335#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
29336/* @} */
29337
29338/* The count of PWM_FRACVAL1 */
29339#define PWM_FRACVAL1_COUNT (4U)
29340
29341/* @name VAL1 - Value Register 1 */
29342/* @{ */
29343#define PWM_VAL1_VAL1_MASK (0xFFFFU)
29344#define PWM_VAL1_VAL1_SHIFT (0U)
29345#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
29346/* @} */
29347
29348/* The count of PWM_VAL1 */
29349#define PWM_VAL1_COUNT (4U)
29350
29351/* @name FRACVAL2 - Fractional Value Register 2 */
29352/* @{ */
29353#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
29354#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
29355#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
29356/* @} */
29357
29358/* The count of PWM_FRACVAL2 */
29359#define PWM_FRACVAL2_COUNT (4U)
29360
29361/* @name VAL2 - Value Register 2 */
29362/* @{ */
29363#define PWM_VAL2_VAL2_MASK (0xFFFFU)
29364#define PWM_VAL2_VAL2_SHIFT (0U)
29365#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
29366/* @} */
29367
29368/* The count of PWM_VAL2 */
29369#define PWM_VAL2_COUNT (4U)
29370
29371/* @name FRACVAL3 - Fractional Value Register 3 */
29372/* @{ */
29373#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
29374#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
29375#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
29376/* @} */
29377
29378/* The count of PWM_FRACVAL3 */
29379#define PWM_FRACVAL3_COUNT (4U)
29380
29381/* @name VAL3 - Value Register 3 */
29382/* @{ */
29383#define PWM_VAL3_VAL3_MASK (0xFFFFU)
29384#define PWM_VAL3_VAL3_SHIFT (0U)
29385#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
29386/* @} */
29387
29388/* The count of PWM_VAL3 */
29389#define PWM_VAL3_COUNT (4U)
29390
29391/* @name FRACVAL4 - Fractional Value Register 4 */
29392/* @{ */
29393#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
29394#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
29395#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
29396/* @} */
29397
29398/* The count of PWM_FRACVAL4 */
29399#define PWM_FRACVAL4_COUNT (4U)
29400
29401/* @name VAL4 - Value Register 4 */
29402/* @{ */
29403#define PWM_VAL4_VAL4_MASK (0xFFFFU)
29404#define PWM_VAL4_VAL4_SHIFT (0U)
29405#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
29406/* @} */
29407
29408/* The count of PWM_VAL4 */
29409#define PWM_VAL4_COUNT (4U)
29410
29411/* @name FRACVAL5 - Fractional Value Register 5 */
29412/* @{ */
29413#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
29414#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
29415#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
29416/* @} */
29417
29418/* The count of PWM_FRACVAL5 */
29419#define PWM_FRACVAL5_COUNT (4U)
29420
29421/* @name VAL5 - Value Register 5 */
29422/* @{ */
29423#define PWM_VAL5_VAL5_MASK (0xFFFFU)
29424#define PWM_VAL5_VAL5_SHIFT (0U)
29425#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
29426/* @} */
29427
29428/* The count of PWM_VAL5 */
29429#define PWM_VAL5_COUNT (4U)
29430
29431/* @name FRCTRL - Fractional Control Register */
29432/* @{ */
29433#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
29434#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
29435/* FRAC1_EN - Fractional Cycle PWM Period Enable
29436 * 0b0..Disable fractional cycle length for the PWM period.
29437 * 0b1..Enable fractional cycle length for the PWM period.
29438 */
29439#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
29440#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
29441#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
29442/* FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
29443 * 0b0..Disable fractional cycle placement for PWM_A.
29444 * 0b1..Enable fractional cycle placement for PWM_A.
29445 */
29446#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
29447#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
29448#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
29449/* FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
29450 * 0b0..Disable fractional cycle placement for PWM_B.
29451 * 0b1..Enable fractional cycle placement for PWM_B.
29452 */
29453#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
29454#define PWM_FRCTRL_FRAC_PU_MASK (0x100U)
29455#define PWM_FRCTRL_FRAC_PU_SHIFT (8U)
29456/* FRAC_PU - Fractional Delay Circuit Power Up
29457 * 0b0..Turn off fractional delay logic.
29458 * 0b1..Power up fractional delay logic.
29459 */
29460#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
29461#define PWM_FRCTRL_TEST_MASK (0x8000U)
29462#define PWM_FRCTRL_TEST_SHIFT (15U)
29463#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
29464/* @} */
29465
29466/* The count of PWM_FRCTRL */
29467#define PWM_FRCTRL_COUNT (4U)
29468
29469/* @name OCTRL - Output Control Register */
29470/* @{ */
29471#define PWM_OCTRL_PWMXFS_MASK (0x3U)
29472#define PWM_OCTRL_PWMXFS_SHIFT (0U)
29473/* PWMXFS - PWM_X Fault State
29474 * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
29475 * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
29476 * 0b10..Output is tristated.
29477 * 0b11..Output is tristated.
29478 */
29479#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
29480#define PWM_OCTRL_PWMBFS_MASK (0xCU)
29481#define PWM_OCTRL_PWMBFS_SHIFT (2U)
29482/* PWMBFS - PWM_B Fault State
29483 * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
29484 * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
29485 * 0b10..Output is tristated.
29486 * 0b11..Output is tristated.
29487 */
29488#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
29489#define PWM_OCTRL_PWMAFS_MASK (0x30U)
29490#define PWM_OCTRL_PWMAFS_SHIFT (4U)
29491/* PWMAFS - PWM_A Fault State
29492 * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
29493 * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
29494 * 0b10..Output is tristated.
29495 * 0b11..Output is tristated.
29496 */
29497#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
29498#define PWM_OCTRL_POLX_MASK (0x100U)
29499#define PWM_OCTRL_POLX_SHIFT (8U)
29500/* POLX - PWM_X Output Polarity
29501 * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
29502 * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
29503 */
29504#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
29505#define PWM_OCTRL_POLB_MASK (0x200U)
29506#define PWM_OCTRL_POLB_SHIFT (9U)
29507/* POLB - PWM_B Output Polarity
29508 * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
29509 * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
29510 */
29511#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
29512#define PWM_OCTRL_POLA_MASK (0x400U)
29513#define PWM_OCTRL_POLA_SHIFT (10U)
29514/* POLA - PWM_A Output Polarity
29515 * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
29516 * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
29517 */
29518#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
29519#define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
29520#define PWM_OCTRL_PWMX_IN_SHIFT (13U)
29521#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
29522#define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
29523#define PWM_OCTRL_PWMB_IN_SHIFT (14U)
29524#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
29525#define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
29526#define PWM_OCTRL_PWMA_IN_SHIFT (15U)
29527#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
29528/* @} */
29529
29530/* The count of PWM_OCTRL */
29531#define PWM_OCTRL_COUNT (4U)
29532
29533/* @name STS - Status Register */
29534/* @{ */
29535#define PWM_STS_CMPF_MASK (0x3FU)
29536#define PWM_STS_CMPF_SHIFT (0U)
29537/* CMPF - Compare Flags
29538 * 0b000000..No compare event has occurred for a particular VALx value.
29539 * 0b000001..A compare event has occurred for a particular VALx value.
29540 */
29541#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
29542#define PWM_STS_CFX0_MASK (0x40U)
29543#define PWM_STS_CFX0_SHIFT (6U)
29544#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
29545#define PWM_STS_CFX1_MASK (0x80U)
29546#define PWM_STS_CFX1_SHIFT (7U)
29547#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
29548#define PWM_STS_CFB0_MASK (0x100U)
29549#define PWM_STS_CFB0_SHIFT (8U)
29550#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
29551#define PWM_STS_CFB1_MASK (0x200U)
29552#define PWM_STS_CFB1_SHIFT (9U)
29553#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
29554#define PWM_STS_CFA0_MASK (0x400U)
29555#define PWM_STS_CFA0_SHIFT (10U)
29556#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
29557#define PWM_STS_CFA1_MASK (0x800U)
29558#define PWM_STS_CFA1_SHIFT (11U)
29559#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
29560#define PWM_STS_RF_MASK (0x1000U)
29561#define PWM_STS_RF_SHIFT (12U)
29562/* RF - Reload Flag
29563 * 0b0..No new reload cycle since last STS[RF] clearing
29564 * 0b1..New reload cycle since last STS[RF] clearing
29565 */
29566#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
29567#define PWM_STS_REF_MASK (0x2000U)
29568#define PWM_STS_REF_SHIFT (13U)
29569/* REF - Reload Error Flag
29570 * 0b0..No reload error occurred.
29571 * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
29572 */
29573#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
29574#define PWM_STS_RUF_MASK (0x4000U)
29575#define PWM_STS_RUF_SHIFT (14U)
29576/* RUF - Registers Updated Flag
29577 * 0b0..No register update has occurred since last reload.
29578 * 0b1..At least one of the double buffered registers has been updated since the last reload.
29579 */
29580#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
29581/* @} */
29582
29583/* The count of PWM_STS */
29584#define PWM_STS_COUNT (4U)
29585
29586/* @name INTEN - Interrupt Enable Register */
29587/* @{ */
29588#define PWM_INTEN_CMPIE_MASK (0x3FU)
29589#define PWM_INTEN_CMPIE_SHIFT (0U)
29590/* CMPIE - Compare Interrupt Enables
29591 * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
29592 * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
29593 */
29594#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
29595#define PWM_INTEN_CX0IE_MASK (0x40U)
29596#define PWM_INTEN_CX0IE_SHIFT (6U)
29597/* CX0IE - Capture X 0 Interrupt Enable
29598 * 0b0..Interrupt request disabled for STS[CFX0].
29599 * 0b1..Interrupt request enabled for STS[CFX0].
29600 */
29601#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
29602#define PWM_INTEN_CX1IE_MASK (0x80U)
29603#define PWM_INTEN_CX1IE_SHIFT (7U)
29604/* CX1IE - Capture X 1 Interrupt Enable
29605 * 0b0..Interrupt request disabled for STS[CFX1].
29606 * 0b1..Interrupt request enabled for STS[CFX1].
29607 */
29608#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
29609#define PWM_INTEN_CB0IE_MASK (0x100U)
29610#define PWM_INTEN_CB0IE_SHIFT (8U)
29611/* CB0IE - Capture B 0 Interrupt Enable
29612 * 0b0..Interrupt request disabled for STS[CFB0].
29613 * 0b1..Interrupt request enabled for STS[CFB0].
29614 */
29615#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
29616#define PWM_INTEN_CB1IE_MASK (0x200U)
29617#define PWM_INTEN_CB1IE_SHIFT (9U)
29618/* CB1IE - Capture B 1 Interrupt Enable
29619 * 0b0..Interrupt request disabled for STS[CFB1].
29620 * 0b1..Interrupt request enabled for STS[CFB1].
29621 */
29622#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
29623#define PWM_INTEN_CA0IE_MASK (0x400U)
29624#define PWM_INTEN_CA0IE_SHIFT (10U)
29625/* CA0IE - Capture A 0 Interrupt Enable
29626 * 0b0..Interrupt request disabled for STS[CFA0].
29627 * 0b1..Interrupt request enabled for STS[CFA0].
29628 */
29629#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
29630#define PWM_INTEN_CA1IE_MASK (0x800U)
29631#define PWM_INTEN_CA1IE_SHIFT (11U)
29632/* CA1IE - Capture A 1 Interrupt Enable
29633 * 0b0..Interrupt request disabled for STS[CFA1].
29634 * 0b1..Interrupt request enabled for STS[CFA1].
29635 */
29636#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
29637#define PWM_INTEN_RIE_MASK (0x1000U)
29638#define PWM_INTEN_RIE_SHIFT (12U)
29639/* RIE - Reload Interrupt Enable
29640 * 0b0..STS[RF] CPU interrupt requests disabled
29641 * 0b1..STS[RF] CPU interrupt requests enabled
29642 */
29643#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
29644#define PWM_INTEN_REIE_MASK (0x2000U)
29645#define PWM_INTEN_REIE_SHIFT (13U)
29646/* REIE - Reload Error Interrupt Enable
29647 * 0b0..STS[REF] CPU interrupt requests disabled
29648 * 0b1..STS[REF] CPU interrupt requests enabled
29649 */
29650#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
29651/* @} */
29652
29653/* The count of PWM_INTEN */
29654#define PWM_INTEN_COUNT (4U)
29655
29656/* @name DMAEN - DMA Enable Register */
29657/* @{ */
29658#define PWM_DMAEN_CX0DE_MASK (0x1U)
29659#define PWM_DMAEN_CX0DE_SHIFT (0U)
29660#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
29661#define PWM_DMAEN_CX1DE_MASK (0x2U)
29662#define PWM_DMAEN_CX1DE_SHIFT (1U)
29663#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
29664#define PWM_DMAEN_CB0DE_MASK (0x4U)
29665#define PWM_DMAEN_CB0DE_SHIFT (2U)
29666#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
29667#define PWM_DMAEN_CB1DE_MASK (0x8U)
29668#define PWM_DMAEN_CB1DE_SHIFT (3U)
29669#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
29670#define PWM_DMAEN_CA0DE_MASK (0x10U)
29671#define PWM_DMAEN_CA0DE_SHIFT (4U)
29672#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
29673#define PWM_DMAEN_CA1DE_MASK (0x20U)
29674#define PWM_DMAEN_CA1DE_SHIFT (5U)
29675#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
29676#define PWM_DMAEN_CAPTDE_MASK (0xC0U)
29677#define PWM_DMAEN_CAPTDE_SHIFT (6U)
29678/* CAPTDE - Capture DMA Enable Source Select
29679 * 0b00..Read DMA requests disabled.
29680 * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
29681 * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to
29682 * which watermark(s) the DMA request is sensitive.
29683 * 0b10..A local sync (VAL1 matches counter) sets the read DMA request.
29684 * 0b11..A local reload (STS[RF] being set) sets the read DMA request.
29685 */
29686#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
29687#define PWM_DMAEN_FAND_MASK (0x100U)
29688#define PWM_DMAEN_FAND_SHIFT (8U)
29689/* FAND - FIFO Watermark AND Control
29690 * 0b0..Selected FIFO watermarks are OR'ed together.
29691 * 0b1..Selected FIFO watermarks are AND'ed together.
29692 */
29693#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
29694#define PWM_DMAEN_VALDE_MASK (0x200U)
29695#define PWM_DMAEN_VALDE_SHIFT (9U)
29696/* VALDE - Value Registers DMA Enable
29697 * 0b0..DMA write requests disabled
29698 * 0b1..DMA write requests for the VALx and FRACVALx registers enabled
29699 */
29700#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
29701/* @} */
29702
29703/* The count of PWM_DMAEN */
29704#define PWM_DMAEN_COUNT (4U)
29705
29706/* @name TCTRL - Output Trigger Control Register */
29707/* @{ */
29708#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
29709#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
29710/* OUT_TRIG_EN - Output Trigger Enables
29711 * 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value.
29712 * 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value.
29713 */
29714#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
29715#define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
29716#define PWM_TCTRL_TRGFRQ_SHIFT (12U)
29717/* TRGFRQ - Trigger frequency
29718 * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
29719 * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
29720 * is not reloaded every period due to CTRL[LDFQ] being non-zero.
29721 */
29722#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
29723#define PWM_TCTRL_PWBOT1_MASK (0x4000U)
29724#define PWM_TCTRL_PWBOT1_SHIFT (14U)
29725/* PWBOT1 - Output Trigger 1 Source Select
29726 * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
29727 * 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port.
29728 */
29729#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
29730#define PWM_TCTRL_PWAOT0_MASK (0x8000U)
29731#define PWM_TCTRL_PWAOT0_SHIFT (15U)
29732/* PWAOT0 - Output Trigger 0 Source Select
29733 * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
29734 * 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port.
29735 */
29736#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
29737/* @} */
29738
29739/* The count of PWM_TCTRL */
29740#define PWM_TCTRL_COUNT (4U)
29741
29742/* @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */
29743/* @{ */
29744#define PWM_DISMAP_DIS0A_MASK (0xFU)
29745#define PWM_DISMAP_DIS0A_SHIFT (0U)
29746#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
29747#define PWM_DISMAP_DIS1A_MASK (0xFU)
29748#define PWM_DISMAP_DIS1A_SHIFT (0U)
29749#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
29750#define PWM_DISMAP_DIS0B_MASK (0xF0U)
29751#define PWM_DISMAP_DIS0B_SHIFT (4U)
29752#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
29753#define PWM_DISMAP_DIS1B_MASK (0xF0U)
29754#define PWM_DISMAP_DIS1B_SHIFT (4U)
29755#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
29756#define PWM_DISMAP_DIS0X_MASK (0xF00U)
29757#define PWM_DISMAP_DIS0X_SHIFT (8U)
29758#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
29759#define PWM_DISMAP_DIS1X_MASK (0xF00U)
29760#define PWM_DISMAP_DIS1X_SHIFT (8U)
29761#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
29762/* @} */
29763
29764/* The count of PWM_DISMAP */
29765#define PWM_DISMAP_COUNT (4U)
29766
29767/* The count of PWM_DISMAP */
29768#define PWM_DISMAP_COUNT2 (2U)
29769
29770/* @name DTCNT0 - Deadtime Count Register 0 */
29771/* @{ */
29772#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
29773#define PWM_DTCNT0_DTCNT0_SHIFT (0U)
29774#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
29775/* @} */
29776
29777/* The count of PWM_DTCNT0 */
29778#define PWM_DTCNT0_COUNT (4U)
29779
29780/* @name DTCNT1 - Deadtime Count Register 1 */
29781/* @{ */
29782#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
29783#define PWM_DTCNT1_DTCNT1_SHIFT (0U)
29784#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
29785/* @} */
29786
29787/* The count of PWM_DTCNT1 */
29788#define PWM_DTCNT1_COUNT (4U)
29789
29790/* @name CAPTCTRLA - Capture Control A Register */
29791/* @{ */
29792#define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
29793#define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
29794/* ARMA - Arm A
29795 * 0b0..Input capture operation is disabled.
29796 * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
29797 */
29798#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
29799#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
29800#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
29801/* ONESHOTA - One Shot Mode A
29802 * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
29803 * first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1
29804 * is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed.
29805 * The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
29806 * indefinitely on the enabled capture circuit.
29807 * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
29808 * after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
29809 * armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No
29810 * further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is
29811 * enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.
29812 */
29813#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
29814#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
29815#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
29816/* EDGA0 - Edge A 0
29817 * 0b00..Disabled
29818 * 0b01..Capture falling edges
29819 * 0b10..Capture rising edges
29820 * 0b11..Capture any edge
29821 */
29822#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
29823#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
29824#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
29825/* EDGA1 - Edge A 1
29826 * 0b00..Disabled
29827 * 0b01..Capture falling edges
29828 * 0b10..Capture rising edges
29829 * 0b11..Capture any edge
29830 */
29831#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
29832#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
29833#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
29834/* INP_SELA - Input Select A
29835 * 0b0..Raw PWM_A input signal selected as source.
29836 * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
29837 * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and
29838 * CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the
29839 * CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.
29840 */
29841#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
29842#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
29843#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
29844/* EDGCNTA_EN - Edge Counter A Enable
29845 * 0b0..Edge counter disabled and held in reset
29846 * 0b1..Edge counter enabled
29847 */
29848#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
29849#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
29850#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
29851#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
29852#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
29853#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
29854#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
29855#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
29856#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
29857#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
29858/* @} */
29859
29860/* The count of PWM_CAPTCTRLA */
29861#define PWM_CAPTCTRLA_COUNT (4U)
29862
29863/* @name CAPTCOMPA - Capture Compare A Register */
29864/* @{ */
29865#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
29866#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
29867#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
29868#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
29869#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
29870#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
29871/* @} */
29872
29873/* The count of PWM_CAPTCOMPA */
29874#define PWM_CAPTCOMPA_COUNT (4U)
29875
29876/* @name CAPTCTRLB - Capture Control B Register */
29877/* @{ */
29878#define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
29879#define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
29880/* ARMB - Arm B
29881 * 0b0..Input capture operation is disabled.
29882 * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
29883 */
29884#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
29885#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
29886#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
29887/* ONESHOTB - One Shot Mode B
29888 * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
29889 * first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1
29890 * is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed.
29891 * The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
29892 * indefinitely on the enabled capture circuit.
29893 * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
29894 * after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
29895 * armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No
29896 * further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is
29897 * enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.
29898 */
29899#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
29900#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
29901#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
29902/* EDGB0 - Edge B 0
29903 * 0b00..Disabled
29904 * 0b01..Capture falling edges
29905 * 0b10..Capture rising edges
29906 * 0b11..Capture any edge
29907 */
29908#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
29909#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
29910#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
29911/* EDGB1 - Edge B 1
29912 * 0b00..Disabled
29913 * 0b01..Capture falling edges
29914 * 0b10..Capture rising edges
29915 * 0b11..Capture any edge
29916 */
29917#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
29918#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
29919#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
29920/* INP_SELB - Input Select B
29921 * 0b0..Raw PWM_B input signal selected as source.
29922 * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
29923 * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and
29924 * CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the
29925 * CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.
29926 */
29927#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
29928#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
29929#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
29930/* EDGCNTB_EN - Edge Counter B Enable
29931 * 0b0..Edge counter disabled and held in reset
29932 * 0b1..Edge counter enabled
29933 */
29934#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
29935#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
29936#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
29937#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
29938#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
29939#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
29940#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
29941#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
29942#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
29943#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
29944/* @} */
29945
29946/* The count of PWM_CAPTCTRLB */
29947#define PWM_CAPTCTRLB_COUNT (4U)
29948
29949/* @name CAPTCOMPB - Capture Compare B Register */
29950/* @{ */
29951#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
29952#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
29953#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
29954#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
29955#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
29956#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
29957/* @} */
29958
29959/* The count of PWM_CAPTCOMPB */
29960#define PWM_CAPTCOMPB_COUNT (4U)
29961
29962/* @name CAPTCTRLX - Capture Control X Register */
29963/* @{ */
29964#define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
29965#define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
29966/* ARMX - Arm X
29967 * 0b0..Input capture operation is disabled.
29968 * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
29969 */
29970#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
29971#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
29972#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
29973/* ONESHOTX - One Shot Mode Aux
29974 * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed
29975 * first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
29976 * armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The
29977 * process continues indefinitely.If only one of the capture circuits is enabled, then captures continue
29978 * indefinitely on the enabled capture circuit.
29979 * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first
29980 * after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is
29981 * armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further
29982 * captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled,
29983 * then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.
29984 */
29985#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
29986#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
29987#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
29988/* EDGX0 - Edge X 0
29989 * 0b00..Disabled
29990 * 0b01..Capture falling edges
29991 * 0b10..Capture rising edges
29992 * 0b11..Capture any edge
29993 */
29994#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
29995#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
29996#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
29997/* EDGX1 - Edge X 1
29998 * 0b00..Disabled
29999 * 0b01..Capture falling edges
30000 * 0b10..Capture rising edges
30001 * 0b11..Capture any edge
30002 */
30003#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
30004#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
30005#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
30006/* INP_SELX - Input Select X
30007 * 0b0..Raw PWM_X input signal selected as source.
30008 * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal
30009 * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and
30010 * CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the
30011 * CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.
30012 */
30013#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
30014#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
30015#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
30016/* EDGCNTX_EN - Edge Counter X Enable
30017 * 0b0..Edge counter disabled and held in reset
30018 * 0b1..Edge counter enabled
30019 */
30020#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
30021#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
30022#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
30023#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
30024#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
30025#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
30026#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
30027#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
30028#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
30029#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
30030/* @} */
30031
30032/* The count of PWM_CAPTCTRLX */
30033#define PWM_CAPTCTRLX_COUNT (4U)
30034
30035/* @name CAPTCOMPX - Capture Compare X Register */
30036/* @{ */
30037#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
30038#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
30039#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
30040#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
30041#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
30042#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
30043/* @} */
30044
30045/* The count of PWM_CAPTCOMPX */
30046#define PWM_CAPTCOMPX_COUNT (4U)
30047
30048/* @name CVAL0 - Capture Value 0 Register */
30049/* @{ */
30050#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
30051#define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
30052#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
30053/* @} */
30054
30055/* The count of PWM_CVAL0 */
30056#define PWM_CVAL0_COUNT (4U)
30057
30058/* @name CVAL0CYC - Capture Value 0 Cycle Register */
30059/* @{ */
30060#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
30061#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
30062#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
30063/* @} */
30064
30065/* The count of PWM_CVAL0CYC */
30066#define PWM_CVAL0CYC_COUNT (4U)
30067
30068/* @name CVAL1 - Capture Value 1 Register */
30069/* @{ */
30070#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
30071#define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
30072#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
30073/* @} */
30074
30075/* The count of PWM_CVAL1 */
30076#define PWM_CVAL1_COUNT (4U)
30077
30078/* @name CVAL1CYC - Capture Value 1 Cycle Register */
30079/* @{ */
30080#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
30081#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
30082#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
30083/* @} */
30084
30085/* The count of PWM_CVAL1CYC */
30086#define PWM_CVAL1CYC_COUNT (4U)
30087
30088/* @name CVAL2 - Capture Value 2 Register */
30089/* @{ */
30090#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
30091#define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
30092#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
30093/* @} */
30094
30095/* The count of PWM_CVAL2 */
30096#define PWM_CVAL2_COUNT (4U)
30097
30098/* @name CVAL2CYC - Capture Value 2 Cycle Register */
30099/* @{ */
30100#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
30101#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
30102#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
30103/* @} */
30104
30105/* The count of PWM_CVAL2CYC */
30106#define PWM_CVAL2CYC_COUNT (4U)
30107
30108/* @name CVAL3 - Capture Value 3 Register */
30109/* @{ */
30110#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
30111#define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
30112#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
30113/* @} */
30114
30115/* The count of PWM_CVAL3 */
30116#define PWM_CVAL3_COUNT (4U)
30117
30118/* @name CVAL3CYC - Capture Value 3 Cycle Register */
30119/* @{ */
30120#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
30121#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
30122#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
30123/* @} */
30124
30125/* The count of PWM_CVAL3CYC */
30126#define PWM_CVAL3CYC_COUNT (4U)
30127
30128/* @name CVAL4 - Capture Value 4 Register */
30129/* @{ */
30130#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
30131#define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
30132#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
30133/* @} */
30134
30135/* The count of PWM_CVAL4 */
30136#define PWM_CVAL4_COUNT (4U)
30137
30138/* @name CVAL4CYC - Capture Value 4 Cycle Register */
30139/* @{ */
30140#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
30141#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
30142#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
30143/* @} */
30144
30145/* The count of PWM_CVAL4CYC */
30146#define PWM_CVAL4CYC_COUNT (4U)
30147
30148/* @name CVAL5 - Capture Value 5 Register */
30149/* @{ */
30150#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
30151#define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
30152#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
30153/* @} */
30154
30155/* The count of PWM_CVAL5 */
30156#define PWM_CVAL5_COUNT (4U)
30157
30158/* @name CVAL5CYC - Capture Value 5 Cycle Register */
30159/* @{ */
30160#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
30161#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
30162#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
30163/* @} */
30164
30165/* The count of PWM_CVAL5CYC */
30166#define PWM_CVAL5CYC_COUNT (4U)
30167
30168/* @name OUTEN - Output Enable Register */
30169/* @{ */
30170#define PWM_OUTEN_PWMX_EN_MASK (0xFU)
30171#define PWM_OUTEN_PWMX_EN_SHIFT (0U)
30172/* PWMX_EN - PWM_X Output Enables
30173 * 0b0000..PWM_X output disabled.
30174 * 0b0001..PWM_X output enabled.
30175 */
30176#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
30177#define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
30178#define PWM_OUTEN_PWMB_EN_SHIFT (4U)
30179/* PWMB_EN - PWM_B Output Enables
30180 * 0b0000..PWM_B output disabled.
30181 * 0b0001..PWM_B output enabled.
30182 */
30183#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
30184#define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
30185#define PWM_OUTEN_PWMA_EN_SHIFT (8U)
30186/* PWMA_EN - PWM_A Output Enables
30187 * 0b0000..PWM_A output disabled.
30188 * 0b0001..PWM_A output enabled.
30189 */
30190#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
30191/* @} */
30192
30193/* @name MASK - Mask Register */
30194/* @{ */
30195#define PWM_MASK_MASKX_MASK (0xFU)
30196#define PWM_MASK_MASKX_SHIFT (0U)
30197/* MASKX - PWM_X Masks
30198 * 0b0000..PWM_X output normal.
30199 * 0b0001..PWM_X output masked.
30200 */
30201#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
30202#define PWM_MASK_MASKB_MASK (0xF0U)
30203#define PWM_MASK_MASKB_SHIFT (4U)
30204/* MASKB - PWM_B Masks
30205 * 0b0000..PWM_B output normal.
30206 * 0b0001..PWM_B output masked.
30207 */
30208#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
30209#define PWM_MASK_MASKA_MASK (0xF00U)
30210#define PWM_MASK_MASKA_SHIFT (8U)
30211/* MASKA - PWM_A Masks
30212 * 0b0000..PWM_A output normal.
30213 * 0b0001..PWM_A output masked.
30214 */
30215#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
30216#define PWM_MASK_UPDATE_MASK_MASK (0xF000U)
30217#define PWM_MASK_UPDATE_MASK_SHIFT (12U)
30218/* UPDATE_MASK - Update Mask Bits Immediately
30219 * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule.
30220 * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit.
30221 */
30222#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
30223/* @} */
30224
30225/* @name SWCOUT - Software Controlled Output Register */
30226/* @{ */
30227#define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
30228#define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
30229/* SM0OUT45 - Submodule 0 Software Controlled Output 45
30230 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
30231 * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
30232 */
30233#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
30234#define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
30235#define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
30236/* SM0OUT23 - Submodule 0 Software Controlled Output 23
30237 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
30238 * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
30239 */
30240#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
30241#define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
30242#define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
30243/* SM1OUT45 - Submodule 1 Software Controlled Output 45
30244 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
30245 * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
30246 */
30247#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
30248#define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
30249#define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
30250/* SM1OUT23 - Submodule 1 Software Controlled Output 23
30251 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
30252 * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
30253 */
30254#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
30255#define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
30256#define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
30257/* SM2OUT45 - Submodule 2 Software Controlled Output 45
30258 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
30259 * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
30260 */
30261#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
30262#define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
30263#define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
30264/* SM2OUT23 - Submodule 2 Software Controlled Output 23
30265 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
30266 * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
30267 */
30268#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
30269#define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
30270#define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
30271/* SM3OUT45 - Submodule 3 Software Controlled Output 45
30272 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
30273 * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
30274 */
30275#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
30276#define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
30277#define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
30278/* SM3OUT23 - Submodule 3 Software Controlled Output 23
30279 * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
30280 * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
30281 */
30282#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
30283/* @} */
30284
30285/* @name DTSRCSEL - PWM Source Select Register */
30286/* @{ */
30287#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
30288#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
30289/* SM0SEL45 - Submodule 0 PWM45 Control Select
30290 * 0b00..Generated SM0PWM45 signal is used by the deadtime logic.
30291 * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic.
30292 * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic.
30293 * 0b11..PWM0_EXTB signal is used by the deadtime logic.
30294 */
30295#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
30296#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
30297#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
30298/* SM0SEL23 - Submodule 0 PWM23 Control Select
30299 * 0b00..Generated SM0PWM23 signal is used by the deadtime logic.
30300 * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic.
30301 * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic.
30302 * 0b11..PWM0_EXTA signal is used by the deadtime logic.
30303 */
30304#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
30305#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
30306#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
30307/* SM1SEL45 - Submodule 1 PWM45 Control Select
30308 * 0b00..Generated SM1PWM45 signal is used by the deadtime logic.
30309 * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic.
30310 * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic.
30311 * 0b11..PWM1_EXTB signal is used by the deadtime logic.
30312 */
30313#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
30314#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
30315#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
30316/* SM1SEL23 - Submodule 1 PWM23 Control Select
30317 * 0b00..Generated SM1PWM23 signal is used by the deadtime logic.
30318 * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic.
30319 * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic.
30320 * 0b11..PWM1_EXTA signal is used by the deadtime logic.
30321 */
30322#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
30323#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
30324#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
30325/* SM2SEL45 - Submodule 2 PWM45 Control Select
30326 * 0b00..Generated SM2PWM45 signal is used by the deadtime logic.
30327 * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic.
30328 * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic.
30329 * 0b11..PWM2_EXTB signal is used by the deadtime logic.
30330 */
30331#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
30332#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
30333#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
30334/* SM2SEL23 - Submodule 2 PWM23 Control Select
30335 * 0b00..Generated SM2PWM23 signal is used by the deadtime logic.
30336 * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic.
30337 * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic.
30338 * 0b11..PWM2_EXTA signal is used by the deadtime logic.
30339 */
30340#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
30341#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
30342#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
30343/* SM3SEL45 - Submodule 3 PWM45 Control Select
30344 * 0b00..Generated SM3PWM45 signal is used by the deadtime logic.
30345 * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic.
30346 * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic.
30347 * 0b11..PWM3_EXTB signal is used by the deadtime logic.
30348 */
30349#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
30350#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
30351#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
30352/* SM3SEL23 - Submodule 3 PWM23 Control Select
30353 * 0b00..Generated SM3PWM23 signal is used by the deadtime logic.
30354 * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic.
30355 * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic.
30356 * 0b11..PWM3_EXTA signal is used by the deadtime logic.
30357 */
30358#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
30359/* @} */
30360
30361/* @name MCTRL - Master Control Register */
30362/* @{ */
30363#define PWM_MCTRL_LDOK_MASK (0xFU)
30364#define PWM_MCTRL_LDOK_SHIFT (0U)
30365/* LDOK - Load Okay
30366 * 0b0000..Do not load new values.
30367 * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
30368 */
30369#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
30370#define PWM_MCTRL_CLDOK_MASK (0xF0U)
30371#define PWM_MCTRL_CLDOK_SHIFT (4U)
30372#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
30373#define PWM_MCTRL_RUN_MASK (0xF00U)
30374#define PWM_MCTRL_RUN_SHIFT (8U)
30375/* RUN - Run
30376 * 0b0000..PWM generator is disabled in the corresponding submodule.
30377 * 0b0001..PWM generator is enabled in the corresponding submodule.
30378 */
30379#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
30380#define PWM_MCTRL_IPOL_MASK (0xF000U)
30381#define PWM_MCTRL_IPOL_SHIFT (12U)
30382/* IPOL - Current Polarity
30383 * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
30384 * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
30385 */
30386#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
30387/* @} */
30388
30389/* @name MCTRL2 - Master Control 2 Register */
30390/* @{ */
30391#define PWM_MCTRL2_MONPLL_MASK (0x3U)
30392#define PWM_MCTRL2_MONPLL_SHIFT (0U)
30393/* MONPLL - Monitor PLL State
30394 * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
30395 * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
30396 * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock
30397 * will be controlled by software. These bits are write protected until the next reset.
30398 * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL
30399 * encounters problems. These bits are write protected until the next reset.
30400 */
30401#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
30402/* @} */
30403
30404/* @name FCTRL - Fault Control Register */
30405/* @{ */
30406#define PWM_FCTRL_FIE_MASK (0xFU)
30407#define PWM_FCTRL_FIE_SHIFT (0U)
30408/* FIE - Fault Interrupt Enables
30409 * 0b0000..FAULTx CPU interrupt requests disabled.
30410 * 0b0001..FAULTx CPU interrupt requests enabled.
30411 */
30412#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
30413#define PWM_FCTRL_FSAFE_MASK (0xF0U)
30414#define PWM_FCTRL_FSAFE_SHIFT (4U)
30415/* FSAFE - Fault Safety Mode
30416 * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
30417 * start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of
30418 * FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual
30419 * FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as
30420 * programmed in DISMAPn).
30421 * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
30422 * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL].
30423 */
30424#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
30425#define PWM_FCTRL_FAUTO_MASK (0xF00U)
30426#define PWM_FCTRL_FAUTO_SHIFT (8U)
30427/* FAUTO - Automatic Fault Clearing
30428 * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
30429 * at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further
30430 * controlled by FCTRL[FSAFE].
30431 * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
30432 * the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the
30433 * state of FSTS[FFLAGx].
30434 */
30435#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
30436#define PWM_FCTRL_FLVL_MASK (0xF000U)
30437#define PWM_FCTRL_FLVL_SHIFT (12U)
30438/* FLVL - Fault Level
30439 * 0b0000..A logic 0 on the fault input indicates a fault condition.
30440 * 0b0001..A logic 1 on the fault input indicates a fault condition.
30441 */
30442#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
30443/* @} */
30444
30445/* @name FSTS - Fault Status Register */
30446/* @{ */
30447#define PWM_FSTS_FFLAG_MASK (0xFU)
30448#define PWM_FSTS_FFLAG_SHIFT (0U)
30449/* FFLAG - Fault Flags
30450 * 0b0000..No fault on the FAULTx pin.
30451 * 0b0001..Fault on the FAULTx pin.
30452 */
30453#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
30454#define PWM_FSTS_FFULL_MASK (0xF0U)
30455#define PWM_FSTS_FFULL_SHIFT (4U)
30456/* FFULL - Full Cycle
30457 * 0b0000..PWM outputs are not re-enabled at the start of a full cycle
30458 * 0b0001..PWM outputs are re-enabled at the start of a full cycle
30459 */
30460#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
30461#define PWM_FSTS_FFPIN_MASK (0xF00U)
30462#define PWM_FSTS_FFPIN_SHIFT (8U)
30463#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
30464#define PWM_FSTS_FHALF_MASK (0xF000U)
30465#define PWM_FSTS_FHALF_SHIFT (12U)
30466/* FHALF - Half Cycle Fault Recovery
30467 * 0b0000..PWM outputs are not re-enabled at the start of a half cycle.
30468 * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
30469 */
30470#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
30471/* @} */
30472
30473/* @name FFILT - Fault Filter Register */
30474/* @{ */
30475#define PWM_FFILT_FILT_PER_MASK (0xFFU)
30476#define PWM_FFILT_FILT_PER_SHIFT (0U)
30477#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
30478#define PWM_FFILT_FILT_CNT_MASK (0x700U)
30479#define PWM_FFILT_FILT_CNT_SHIFT (8U)
30480#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
30481#define PWM_FFILT_GSTR_MASK (0x8000U)
30482#define PWM_FFILT_GSTR_SHIFT (15U)
30483/* GSTR - Fault Glitch Stretch Enable
30484 * 0b0..Fault input glitch stretching is disabled.
30485 * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.
30486 */
30487#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
30488/* @} */
30489
30490/* @name FTST - Fault Test Register */
30491/* @{ */
30492#define PWM_FTST_FTEST_MASK (0x1U)
30493#define PWM_FTST_FTEST_SHIFT (0U)
30494/* FTEST - Fault Test
30495 * 0b0..No fault
30496 * 0b1..Cause a simulated fault
30497 */
30498#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
30499/* @} */
30500
30501/* @name FCTRL2 - Fault Control 2 Register */
30502/* @{ */
30503#define PWM_FCTRL2_NOCOMB_MASK (0xFU)
30504#define PWM_FCTRL2_NOCOMB_SHIFT (0U)
30505/* NOCOMB - No Combinational Path From Fault Input To PWM Output
30506 * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
30507 * with the filtered and latched fault signals to disable the PWM outputs.
30508 * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
30509 * and latched fault signals are used to disable the PWM outputs.
30510 */
30511#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
30512/* @} */
30513
30514
30515/*
30516 * @}
30517 */ /* end of group PWM_Register_Masks */
30518
30519
30520/* PWM - Peripheral instance base addresses */
30521/* Peripheral PWM1 base address */
30522#define PWM1_BASE (0x403DC000u)
30523/* Peripheral PWM1 base pointer */
30524#define PWM1 ((PWM_Type *)PWM1_BASE)
30525/* Peripheral PWM2 base address */
30526#define PWM2_BASE (0x403E0000u)
30527/* Peripheral PWM2 base pointer */
30528#define PWM2 ((PWM_Type *)PWM2_BASE)
30529/* Peripheral PWM3 base address */
30530#define PWM3_BASE (0x403E4000u)
30531/* Peripheral PWM3 base pointer */
30532#define PWM3 ((PWM_Type *)PWM3_BASE)
30533/* Peripheral PWM4 base address */
30534#define PWM4_BASE (0x403E8000u)
30535/* Peripheral PWM4 base pointer */
30536#define PWM4 ((PWM_Type *)PWM4_BASE)
30537/* Array initializer of PWM peripheral base addresses */
30538#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
30539/* Array initializer of PWM peripheral base pointers */
30540#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
30541/* Interrupt vectors for the PWM peripheral type */
30542#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
30543#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
30544#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
30545#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
30546#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
30547
30548/*
30549 * @}
30550 */ /* end of group PWM_Peripheral_Access_Layer */
30551
30552
30553/* ----------------------------------------------------------------------------
30554 -- ROMC Peripheral Access Layer
30555 ---------------------------------------------------------------------------- */
30556
30557/*
30558 * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer
30559 * @{
30560 */
30561
30562/* ROMC - Register Layout Typedef */
30563typedef struct {
30564 uint8_t RESERVED_0[212];
30565 __IO uint32_t ROMPATCHD[8];
30566 __IO uint32_t ROMPATCHCNTL;
30567 uint32_t ROMPATCHENH;
30568 __IO uint32_t ROMPATCHENL;
30569 __IO uint32_t ROMPATCHA[16];
30570 uint8_t RESERVED_1[200];
30571 __IO uint32_t ROMPATCHSR;
30572} ROMC_Type;
30573
30574/* ----------------------------------------------------------------------------
30575 -- ROMC Register Masks
30576 ---------------------------------------------------------------------------- */
30577
30578/*
30579 * @addtogroup ROMC_Register_Masks ROMC Register Masks
30580 * @{
30581 */
30582
30583/* @name ROMPATCHD - ROMC Data Registers */
30584/* @{ */
30585#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU)
30586#define ROMC_ROMPATCHD_DATAX_SHIFT (0U)
30587#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK)
30588/* @} */
30589
30590/* The count of ROMC_ROMPATCHD */
30591#define ROMC_ROMPATCHD_COUNT (8U)
30592
30593/* @name ROMPATCHCNTL - ROMC Control Register */
30594/* @{ */
30595#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU)
30596#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U)
30597/* DATAFIX
30598 * 0b00000000..Address comparator triggers a opcode patch
30599 * 0b00000001..Address comparator triggers a data fix
30600 */
30601#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK)
30602#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U)
30603#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U)
30604/* DIS
30605 * 0b0..Does not affect any ROMC functions (default)
30606 * 0b1..Disable all ROMC functions: data fixing, and opcode patching
30607 */
30608#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK)
30609/* @} */
30610
30611/* @name ROMPATCHENL - ROMC Enable Register Low */
30612/* @{ */
30613#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU)
30614#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U)
30615/* ENABLE
30616 * 0b0000000000000000..Address comparator disabled
30617 * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address
30618 */
30619#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK)
30620/* @} */
30621
30622/* @name ROMPATCHA - ROMC Address Registers */
30623/* @{ */
30624#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U)
30625#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U)
30626/* THUMBX
30627 * 0b0..Arm patch
30628 * 0b1..THUMB patch (ignore if data fix)
30629 */
30630#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK)
30631#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU)
30632#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U)
30633#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK)
30634/* @} */
30635
30636/* The count of ROMC_ROMPATCHA */
30637#define ROMC_ROMPATCHA_COUNT (16U)
30638
30639/* @name ROMPATCHSR - ROMC Status Register */
30640/* @{ */
30641#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU)
30642#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U)
30643/* SOURCE
30644 * 0b000000..Address Comparator 0 matched
30645 * 0b000001..Address Comparator 1 matched
30646 * 0b001111..Address Comparator 15 matched
30647 */
30648#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK)
30649#define ROMC_ROMPATCHSR_SW_MASK (0x20000U)
30650#define ROMC_ROMPATCHSR_SW_SHIFT (17U)
30651/* SW
30652 * 0b0..no event or comparator collisions
30653 * 0b1..a collision has occurred
30654 */
30655#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK)
30656/* @} */
30657
30658
30659/*
30660 * @}
30661 */ /* end of group ROMC_Register_Masks */
30662
30663
30664/* ROMC - Peripheral instance base addresses */
30665/* Peripheral ROMC base address */
30666#define ROMC_BASE (0x40180000u)
30667/* Peripheral ROMC base pointer */
30668#define ROMC ((ROMC_Type *)ROMC_BASE)
30669/* Array initializer of ROMC peripheral base addresses */
30670#define ROMC_BASE_ADDRS { ROMC_BASE }
30671/* Array initializer of ROMC peripheral base pointers */
30672#define ROMC_BASE_PTRS { ROMC }
30673
30674/*
30675 * @}
30676 */ /* end of group ROMC_Peripheral_Access_Layer */
30677
30678
30679/* ----------------------------------------------------------------------------
30680 -- RTWDOG Peripheral Access Layer
30681 ---------------------------------------------------------------------------- */
30682
30683/*
30684 * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
30685 * @{
30686 */
30687
30688/* RTWDOG - Register Layout Typedef */
30689typedef struct {
30690 __IO uint32_t CS;
30691 __IO uint32_t CNT;
30692 __IO uint32_t TOVAL;
30693 __IO uint32_t WIN;
30694} RTWDOG_Type;
30695
30696/* ----------------------------------------------------------------------------
30697 -- RTWDOG Register Masks
30698 ---------------------------------------------------------------------------- */
30699
30700/*
30701 * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
30702 * @{
30703 */
30704
30705/* @name CS - Watchdog Control and Status Register */
30706/* @{ */
30707#define RTWDOG_CS_STOP_MASK (0x1U)
30708#define RTWDOG_CS_STOP_SHIFT (0U)
30709/* STOP - Stop Enable
30710 * 0b0..Watchdog disabled in chip stop mode.
30711 * 0b1..Watchdog enabled in chip stop mode.
30712 */
30713#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
30714#define RTWDOG_CS_WAIT_MASK (0x2U)
30715#define RTWDOG_CS_WAIT_SHIFT (1U)
30716/* WAIT - Wait Enable
30717 * 0b0..Watchdog disabled in chip wait mode.
30718 * 0b1..Watchdog enabled in chip wait mode.
30719 */
30720#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
30721#define RTWDOG_CS_DBG_MASK (0x4U)
30722#define RTWDOG_CS_DBG_SHIFT (2U)
30723/* DBG - Debug Enable
30724 * 0b0..Watchdog disabled in chip debug mode.
30725 * 0b1..Watchdog enabled in chip debug mode.
30726 */
30727#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
30728#define RTWDOG_CS_TST_MASK (0x18U)
30729#define RTWDOG_CS_TST_SHIFT (3U)
30730/* TST - Watchdog Test
30731 * 0b00..Watchdog test mode disabled.
30732 * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
30733 * use this setting to indicate that the watchdog is functioning normally in user mode.
30734 * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
30735 * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
30736 */
30737#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
30738#define RTWDOG_CS_UPDATE_MASK (0x20U)
30739#define RTWDOG_CS_UPDATE_SHIFT (5U)
30740/* UPDATE - Allow updates
30741 * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
30742 * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
30743 */
30744#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
30745#define RTWDOG_CS_INT_MASK (0x40U)
30746#define RTWDOG_CS_INT_SHIFT (6U)
30747/* INT - Watchdog Interrupt
30748 * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
30749 * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.
30750 */
30751#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
30752#define RTWDOG_CS_EN_MASK (0x80U)
30753#define RTWDOG_CS_EN_SHIFT (7U)
30754/* EN - Watchdog Enable
30755 * 0b0..Watchdog disabled.
30756 * 0b1..Watchdog enabled.
30757 */
30758#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
30759#define RTWDOG_CS_CLK_MASK (0x300U)
30760#define RTWDOG_CS_CLK_SHIFT (8U)
30761/* CLK - Watchdog Clock
30762 * 0b00..Bus clock
30763 * 0b01..LPO clock
30764 * 0b10..INTCLK (internal clock)
30765 * 0b11..ERCLK (external reference clock)
30766 */
30767#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
30768#define RTWDOG_CS_RCS_MASK (0x400U)
30769#define RTWDOG_CS_RCS_SHIFT (10U)
30770/* RCS - Reconfiguration Success
30771 * 0b0..Reconfiguring WDOG.
30772 * 0b1..Reconfiguration is successful.
30773 */
30774#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
30775#define RTWDOG_CS_ULK_MASK (0x800U)
30776#define RTWDOG_CS_ULK_SHIFT (11U)
30777/* ULK - Unlock status
30778 * 0b0..WDOG is locked.
30779 * 0b1..WDOG is unlocked.
30780 */
30781#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
30782#define RTWDOG_CS_PRES_MASK (0x1000U)
30783#define RTWDOG_CS_PRES_SHIFT (12U)
30784/* PRES - Watchdog prescaler
30785 * 0b0..256 prescaler disabled.
30786 * 0b1..256 prescaler enabled.
30787 */
30788#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
30789#define RTWDOG_CS_CMD32EN_MASK (0x2000U)
30790#define RTWDOG_CS_CMD32EN_SHIFT (13U)
30791/* CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
30792 * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
30793 * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
30794 */
30795#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
30796#define RTWDOG_CS_FLG_MASK (0x4000U)
30797#define RTWDOG_CS_FLG_SHIFT (14U)
30798/* FLG - Watchdog Interrupt Flag
30799 * 0b0..No interrupt occurred.
30800 * 0b1..An interrupt occurred.
30801 */
30802#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
30803#define RTWDOG_CS_WIN_MASK (0x8000U)
30804#define RTWDOG_CS_WIN_SHIFT (15U)
30805/* WIN - Watchdog Window
30806 * 0b0..Window mode disabled.
30807 * 0b1..Window mode enabled.
30808 */
30809#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
30810/* @} */
30811
30812/* @name CNT - Watchdog Counter Register */
30813/* @{ */
30814#define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
30815#define RTWDOG_CNT_CNTLOW_SHIFT (0U)
30816#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
30817#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
30818#define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
30819#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
30820/* @} */
30821
30822/* @name TOVAL - Watchdog Timeout Value Register */
30823/* @{ */
30824#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
30825#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
30826#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
30827#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
30828#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
30829#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
30830/* @} */
30831
30832/* @name WIN - Watchdog Window Register */
30833/* @{ */
30834#define RTWDOG_WIN_WINLOW_MASK (0xFFU)
30835#define RTWDOG_WIN_WINLOW_SHIFT (0U)
30836#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
30837#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
30838#define RTWDOG_WIN_WINHIGH_SHIFT (8U)
30839#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
30840/* @} */
30841
30842
30843/*
30844 * @}
30845 */ /* end of group RTWDOG_Register_Masks */
30846
30847
30848/* RTWDOG - Peripheral instance base addresses */
30849/* Peripheral RTWDOG base address */
30850#define RTWDOG_BASE (0x400BC000u)
30851/* Peripheral RTWDOG base pointer */
30852#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE)
30853/* Array initializer of RTWDOG peripheral base addresses */
30854#define RTWDOG_BASE_ADDRS { RTWDOG_BASE }
30855/* Array initializer of RTWDOG peripheral base pointers */
30856#define RTWDOG_BASE_PTRS { RTWDOG }
30857/* Interrupt vectors for the RTWDOG peripheral type */
30858#define RTWDOG_IRQS { RTWDOG_IRQn }
30859/* Extra definition */
30860#define RTWDOG_UPDATE_KEY (0xD928C520U)
30861#define RTWDOG_REFRESH_KEY (0xB480A602U)
30862
30863
30864/*
30865 * @}
30866 */ /* end of group RTWDOG_Peripheral_Access_Layer */
30867
30868
30869/* ----------------------------------------------------------------------------
30870 -- SEMC Peripheral Access Layer
30871 ---------------------------------------------------------------------------- */
30872
30873/*
30874 * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer
30875 * @{
30876 */
30877
30878/* SEMC - Register Layout Typedef */
30879typedef struct {
30880 __IO uint32_t MCR;
30881 __IO uint32_t IOCR;
30882 __IO uint32_t BMCR0;
30883 __IO uint32_t BMCR1;
30884 __IO uint32_t BR[9];
30885 __IO uint32_t DLLCR;
30886 __IO uint32_t INTEN;
30887 __IO uint32_t INTR;
30888 __IO uint32_t SDRAMCR0;
30889 __IO uint32_t SDRAMCR1;
30890 __IO uint32_t SDRAMCR2;
30891 __IO uint32_t SDRAMCR3;
30892 __IO uint32_t NANDCR0;
30893 __IO uint32_t NANDCR1;
30894 __IO uint32_t NANDCR2;
30895 __IO uint32_t NANDCR3;
30896 __IO uint32_t NORCR0;
30897 __IO uint32_t NORCR1;
30898 __IO uint32_t NORCR2;
30899 __IO uint32_t NORCR3;
30900 __IO uint32_t SRAMCR0;
30901 __IO uint32_t SRAMCR1;
30902 __IO uint32_t SRAMCR2;
30903 uint32_t SRAMCR3;
30904 __IO uint32_t DBICR0;
30905 __IO uint32_t DBICR1;
30906 uint8_t RESERVED_0[8];
30907 __IO uint32_t IPCR0;
30908 __IO uint32_t IPCR1;
30909 __IO uint32_t IPCR2;
30910 __IO uint32_t IPCMD;
30911 __IO uint32_t IPTXDAT;
30912 uint8_t RESERVED_1[12];
30913 __I uint32_t IPRXDAT;
30914 uint8_t RESERVED_2[12];
30915 __I uint32_t STS0;
30916 uint32_t STS1;
30917 __I uint32_t STS2;
30918 uint32_t STS3;
30919 uint32_t STS4;
30920 uint32_t STS5;
30921 uint32_t STS6;
30922 uint32_t STS7;
30923 uint32_t STS8;
30924 uint32_t STS9;
30925 uint32_t STS10;
30926 uint32_t STS11;
30927 __I uint32_t STS12;
30928 __I uint32_t STS13;
30929 uint32_t STS14;
30930 uint32_t STS15;
30931} SEMC_Type;
30932
30933/* ----------------------------------------------------------------------------
30934 -- SEMC Register Masks
30935 ---------------------------------------------------------------------------- */
30936
30937/*
30938 * @addtogroup SEMC_Register_Masks SEMC Register Masks
30939 * @{
30940 */
30941
30942/* @name MCR - Module Control Register */
30943/* @{ */
30944#define SEMC_MCR_SWRST_MASK (0x1U)
30945#define SEMC_MCR_SWRST_SHIFT (0U)
30946#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
30947#define SEMC_MCR_MDIS_MASK (0x2U)
30948#define SEMC_MCR_MDIS_SHIFT (1U)
30949/* MDIS - Module Disable
30950 * 0b0..Module enabled
30951 * 0b1..Module disabled.
30952 */
30953#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
30954#define SEMC_MCR_DQSMD_MASK (0x4U)
30955#define SEMC_MCR_DQSMD_SHIFT (2U)
30956/* DQSMD - DQS (read strobe) mode
30957 * 0b0..Dummy read strobe loopbacked internally
30958 * 0b1..Dummy read strobe loopbacked from DQS pad or DLL delay chain. Details information at descriptions of DQSSEL bit.
30959 */
30960#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
30961#define SEMC_MCR_WPOL0_MASK (0x40U)
30962#define SEMC_MCR_WPOL0_SHIFT (6U)
30963/* WPOL0 - WAIT/RDY# polarity for NOR/PSRAM
30964 * 0b0..Low active
30965 * 0b1..High active
30966 */
30967#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
30968#define SEMC_MCR_WPOL1_MASK (0x80U)
30969#define SEMC_MCR_WPOL1_SHIFT (7U)
30970/* WPOL1 - WAIT/RDY# polarity for NAND
30971 * 0b0..Low active
30972 * 0b1..High active
30973 */
30974#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
30975#define SEMC_MCR_DQSSEL_MASK (0x400U)
30976#define SEMC_MCR_DQSSEL_SHIFT (10U)
30977/* DQSSEL - Select DQS source when DQSMD and DLLSEL both set.
30978 * 0b0..SDRAM/NOR/SRAM read clock source is from DQS pad in synchronous mode.
30979 * 0b1..SDRAM/NOR/SRAM read clock source is from DLL delay chain in synchronous mode.
30980 */
30981#define SEMC_MCR_DQSSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSSEL_SHIFT)) & SEMC_MCR_DQSSEL_MASK)
30982#define SEMC_MCR_DLLSEL_MASK (0x800U)
30983#define SEMC_MCR_DLLSEL_SHIFT (11U)
30984/* DLLSEL - Select DLL delay chain clock input.
30985 * 0b0..DLL delay chain clock input is from NAND device's DQS pad. For NAND synchronous mode only.
30986 * 0b1..DLL delay chain clock input is from internal clock. For SDRAM, NOR and SRAM synchronous mode only.
30987 */
30988#define SEMC_MCR_DLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DLLSEL_SHIFT)) & SEMC_MCR_DLLSEL_MASK)
30989#define SEMC_MCR_CTO_MASK (0xFF0000U)
30990#define SEMC_MCR_CTO_SHIFT (16U)
30991#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
30992#define SEMC_MCR_BTO_MASK (0x1F000000U)
30993#define SEMC_MCR_BTO_SHIFT (24U)
30994/* BTO - Bus timeout cycles
30995 * 0b00000..255*1
30996 * 0b00001-0b11110..255*2 - 255*2^30
30997 * 0b11111..255*2^31
30998 */
30999#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
31000/* @} */
31001
31002/* @name IOCR - IO Mux Control Register */
31003/* @{ */
31004#define SEMC_IOCR_MUX_A8_MASK (0x7U)
31005#define SEMC_IOCR_MUX_A8_SHIFT (0U)
31006/* MUX_A8 - SEMC_A8 output selection
31007 * 0b000..SDRAM Address bit (A8)
31008 * 0b001..NAND CE#
31009 * 0b010..NOR CE#
31010 * 0b011..PSRAM CE#
31011 * 0b100..DBI CSX
31012 * 0b101..SDRAM Address bit (A8)
31013 * 0b110..SDRAM Address bit (A8)
31014 * 0b111..SDRAM Address bit (A8)
31015 */
31016#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
31017#define SEMC_IOCR_MUX_CSX0_MASK (0x38U)
31018#define SEMC_IOCR_MUX_CSX0_SHIFT (3U)
31019/* MUX_CSX0 - SEMC_CSX0 output selection
31020 * 0b000..NOR/PSRAM Address bit 24 (A24)
31021 * 0b001..SDRAM CS1
31022 * 0b010..SDRAM CS2
31023 * 0b011..SDRAM CS3
31024 * 0b100..NAND CE#
31025 * 0b101..NOR CE#
31026 * 0b110..PSRAM CE#
31027 * 0b111..DBI CSX
31028 */
31029#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
31030#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U)
31031#define SEMC_IOCR_MUX_CSX1_SHIFT (6U)
31032/* MUX_CSX1 - SEMC_CSX1 output selection
31033 * 0b000..NOR/PSRAM Address bit 25 (A25)
31034 * 0b001..SDRAM CS1
31035 * 0b010..SDRAM CS2
31036 * 0b011..SDRAM CS3
31037 * 0b100..NAND CE#
31038 * 0b101..NOR CE#
31039 * 0b110..PSRAM CE#
31040 * 0b111..DBI CSX
31041 */
31042#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
31043#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U)
31044#define SEMC_IOCR_MUX_CSX2_SHIFT (9U)
31045/* MUX_CSX2 - SEMC_CSX2 output selection
31046 * 0b000..NOR/PSRAM Address bit 26 (A26)
31047 * 0b001..SDRAM CS1
31048 * 0b010..SDRAM CS2
31049 * 0b011..SDRAM CS3
31050 * 0b100..NAND CE#
31051 * 0b101..NOR CE#
31052 * 0b110..PSRAM CE#
31053 * 0b111..DBI CSX
31054 */
31055#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
31056#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U)
31057#define SEMC_IOCR_MUX_CSX3_SHIFT (12U)
31058/* MUX_CSX3 - SEMC_CSX3 output selection
31059 * 0b000..NOR/PSRAM Address bit 27 (A27)
31060 * 0b001..SDRAM CS1
31061 * 0b010..SDRAM CS2
31062 * 0b011..SDRAM CS3
31063 * 0b100..NAND CE#
31064 * 0b101..NOR CE#
31065 * 0b110..PSRAM CE#
31066 * 0b111..DBI CSX
31067 */
31068#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
31069#define SEMC_IOCR_MUX_RDY_MASK (0x38000U)
31070#define SEMC_IOCR_MUX_RDY_SHIFT (15U)
31071/* MUX_RDY - SEMC_RDY function selection
31072 * 0b000..NAND Ready/Wait# input
31073 * 0b001..SDRAM CS1
31074 * 0b010..SDRAM CS2
31075 * 0b011..SDRAM CS3
31076 * 0b100..NOR CE#
31077 * 0b101..PSRAM CE#
31078 * 0b110..DBI CSX
31079 * 0b111..NOR/PSRAM Address bit 27
31080 */
31081#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
31082#define SEMC_IOCR_MUX_CLKX0_MASK (0x1000000U)
31083#define SEMC_IOCR_MUX_CLKX0_SHIFT (24U)
31084/* MUX_CLKX0 - SEMC_CLKX0 function selection
31085 * 0b0..NOR clock
31086 * 0b1..SRAM clock
31087 */
31088#define SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
31089#define SEMC_IOCR_MUX_CLKX1_MASK (0x2000000U)
31090#define SEMC_IOCR_MUX_CLKX1_SHIFT (25U)
31091/* MUX_CLKX1 - SEMC_CLKX1 function selection
31092 * 0b0..NOR clock
31093 * 0b1..SRAM clock
31094 */
31095#define SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)
31096/* @} */
31097
31098/* @name BMCR0 - Master Bus (AXI) Control Register 0 */
31099/* @{ */
31100#define SEMC_BMCR0_WQOS_MASK (0xFU)
31101#define SEMC_BMCR0_WQOS_SHIFT (0U)
31102#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
31103#define SEMC_BMCR0_WAGE_MASK (0xF0U)
31104#define SEMC_BMCR0_WAGE_SHIFT (4U)
31105#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
31106#define SEMC_BMCR0_WSH_MASK (0xFF00U)
31107#define SEMC_BMCR0_WSH_SHIFT (8U)
31108#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
31109#define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
31110#define SEMC_BMCR0_WRWS_SHIFT (16U)
31111#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
31112/* @} */
31113
31114/* @name BMCR1 - Master Bus (AXI) Control Register 1 */
31115/* @{ */
31116#define SEMC_BMCR1_WQOS_MASK (0xFU)
31117#define SEMC_BMCR1_WQOS_SHIFT (0U)
31118#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
31119#define SEMC_BMCR1_WAGE_MASK (0xF0U)
31120#define SEMC_BMCR1_WAGE_SHIFT (4U)
31121#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
31122#define SEMC_BMCR1_WPH_MASK (0xFF00U)
31123#define SEMC_BMCR1_WPH_SHIFT (8U)
31124#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
31125#define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
31126#define SEMC_BMCR1_WRWS_SHIFT (16U)
31127#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
31128#define SEMC_BMCR1_WBR_MASK (0xFF000000U)
31129#define SEMC_BMCR1_WBR_SHIFT (24U)
31130#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
31131/* @} */
31132
31133/* @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */
31134/* @{ */
31135#define SEMC_BR_VLD_MASK (0x1U)
31136#define SEMC_BR_VLD_SHIFT (0U)
31137#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
31138#define SEMC_BR_MS_MASK (0x3EU)
31139#define SEMC_BR_MS_SHIFT (1U)
31140/* MS - Memory size
31141 * 0b00000..4KB
31142 * 0b00001..8KB
31143 * 0b00010..16KB
31144 * 0b00011..32KB
31145 * 0b00100..64KB
31146 * 0b00101..128KB
31147 * 0b00110..256KB
31148 * 0b00111..512KB
31149 * 0b01000..1MB
31150 * 0b01001..2MB
31151 * 0b01010..4MB
31152 * 0b01011..8MB
31153 * 0b01100..16MB
31154 * 0b01101..32MB
31155 * 0b01110..64MB
31156 * 0b01111..128MB
31157 * 0b10000..256MB
31158 * 0b10001..512MB
31159 * 0b10010..1GB
31160 * 0b10011..2GB
31161 * 0b10100..4GB
31162 * 0b10101..4GB
31163 * 0b10110..4GB
31164 * 0b10111..4GB
31165 * 0b11000..4GB
31166 * 0b11001..4GB
31167 * 0b11010..4GB
31168 * 0b11011..4GB
31169 * 0b11100..4GB
31170 * 0b11101..4GB
31171 * 0b11110..4GB
31172 * 0b11111..4GB
31173 */
31174#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
31175#define SEMC_BR_BA_MASK (0xFFFFF000U)
31176#define SEMC_BR_BA_SHIFT (12U)
31177#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
31178/* @} */
31179
31180/* The count of SEMC_BR */
31181#define SEMC_BR_COUNT (9U)
31182
31183/* @name DLLCR - DLL Control Register */
31184/* @{ */
31185#define SEMC_DLLCR_DLLEN_MASK (0x1U)
31186#define SEMC_DLLCR_DLLEN_SHIFT (0U)
31187#define SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
31188#define SEMC_DLLCR_DLLRESET_MASK (0x2U)
31189#define SEMC_DLLCR_DLLRESET_SHIFT (1U)
31190#define SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
31191#define SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U)
31192#define SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U)
31193#define SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
31194#define SEMC_DLLCR_OVRDEN_MASK (0x100U)
31195#define SEMC_DLLCR_OVRDEN_SHIFT (8U)
31196#define SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
31197#define SEMC_DLLCR_OVRDVAL_MASK (0x7E00U)
31198#define SEMC_DLLCR_OVRDVAL_SHIFT (9U)
31199#define SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)
31200/* @} */
31201
31202/* @name INTEN - Interrupt Enable Register */
31203/* @{ */
31204#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
31205#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
31206#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
31207#define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
31208#define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
31209#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
31210#define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
31211#define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
31212#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
31213#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
31214#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
31215#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
31216#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
31217#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
31218/* NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation.
31219 * 0b0..Disable
31220 * 0b1..Enable
31221 */
31222#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
31223#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
31224#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
31225/* NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation.
31226 * 0b0..Disable
31227 * 0b1..Enable
31228 */
31229#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
31230/* @} */
31231
31232/* @name INTR - Interrupt Enable Register */
31233/* @{ */
31234#define SEMC_INTR_IPCMDDONE_MASK (0x1U)
31235#define SEMC_INTR_IPCMDDONE_SHIFT (0U)
31236#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
31237#define SEMC_INTR_IPCMDERR_MASK (0x2U)
31238#define SEMC_INTR_IPCMDERR_SHIFT (1U)
31239#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
31240#define SEMC_INTR_AXICMDERR_MASK (0x4U)
31241#define SEMC_INTR_AXICMDERR_SHIFT (2U)
31242#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
31243#define SEMC_INTR_AXIBUSERR_MASK (0x8U)
31244#define SEMC_INTR_AXIBUSERR_SHIFT (3U)
31245#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
31246#define SEMC_INTR_NDPAGEEND_MASK (0x10U)
31247#define SEMC_INTR_NDPAGEEND_SHIFT (4U)
31248#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
31249#define SEMC_INTR_NDNOPEND_MASK (0x20U)
31250#define SEMC_INTR_NDNOPEND_SHIFT (5U)
31251#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
31252/* @} */
31253
31254/* @name SDRAMCR0 - SDRAM control register 0 */
31255/* @{ */
31256#define SEMC_SDRAMCR0_PS_MASK (0x1U)
31257#define SEMC_SDRAMCR0_PS_SHIFT (0U)
31258/* PS - Port Size
31259 * 0b0..8bit
31260 * 0b1..16bit
31261 */
31262#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
31263#define SEMC_SDRAMCR0_BL_MASK (0x70U)
31264#define SEMC_SDRAMCR0_BL_SHIFT (4U)
31265/* BL - Burst Length
31266 * 0b000..1
31267 * 0b001..2
31268 * 0b010..4
31269 * 0b011..8
31270 * 0b100..8
31271 * 0b101..8
31272 * 0b110..8
31273 * 0b111..8
31274 */
31275#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
31276#define SEMC_SDRAMCR0_COL8_MASK (0x80U)
31277#define SEMC_SDRAMCR0_COL8_SHIFT (7U)
31278/* COL8 - Column 8 selection bit
31279 * 0b0..Column address bit number is decided by COL field.
31280 * 0b1..Column address bit number is 8. COL field is ignored.
31281 */
31282#define SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
31283#define SEMC_SDRAMCR0_COL_MASK (0x300U)
31284#define SEMC_SDRAMCR0_COL_SHIFT (8U)
31285/* COL - Column address bit number
31286 * 0b00..12 bit
31287 * 0b01..11 bit
31288 * 0b10..10 bit
31289 * 0b11..9 bit
31290 */
31291#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
31292#define SEMC_SDRAMCR0_CL_MASK (0xC00U)
31293#define SEMC_SDRAMCR0_CL_SHIFT (10U)
31294/* CL - CAS Latency
31295 * 0b00..1
31296 * 0b01..1
31297 * 0b10..2
31298 * 0b11..3
31299 */
31300#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
31301#define SEMC_SDRAMCR0_BANK2_MASK (0x4000U)
31302#define SEMC_SDRAMCR0_BANK2_SHIFT (14U)
31303/* BANK2 - 2 Bank selection bit
31304 * 0b0..SDRAM device has 4 banks.
31305 * 0b1..SDRAM device has 2 banks.
31306 */
31307#define SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)
31308/* @} */
31309
31310/* @name SDRAMCR1 - SDRAM control register 1 */
31311/* @{ */
31312#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
31313#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
31314#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
31315#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
31316#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
31317#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
31318#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
31319#define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
31320#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
31321#define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
31322#define SEMC_SDRAMCR1_WRC_SHIFT (13U)
31323#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
31324#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
31325#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
31326#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
31327#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
31328#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
31329#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
31330/* @} */
31331
31332/* @name SDRAMCR2 - SDRAM control register 2 */
31333/* @{ */
31334#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
31335#define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
31336#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
31337#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
31338#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
31339#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
31340#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
31341#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
31342#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
31343#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
31344#define SEMC_SDRAMCR2_ITO_SHIFT (24U)
31345/* ITO - SDRAM Idle timeout
31346 * 0b00000000..IDLE timeout period is 256*Prescale period.
31347 * 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
31348 */
31349#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
31350/* @} */
31351
31352/* @name SDRAMCR3 - SDRAM control register 3 */
31353/* @{ */
31354#define SEMC_SDRAMCR3_REN_MASK (0x1U)
31355#define SEMC_SDRAMCR3_REN_SHIFT (0U)
31356#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
31357#define SEMC_SDRAMCR3_REBL_MASK (0xEU)
31358#define SEMC_SDRAMCR3_REBL_SHIFT (1U)
31359/* REBL - Refresh burst length
31360 * 0b000..1
31361 * 0b001..2
31362 * 0b010..3
31363 * 0b011..4
31364 * 0b100..5
31365 * 0b101..6
31366 * 0b110..7
31367 * 0b111..8
31368 */
31369#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
31370#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
31371#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
31372/* PRESCALE - Prescaler timer period
31373 * 0b00000000..256*16 cycle
31374 * 0b00000001-0b11111111..PRESCALE*16 cycle
31375 */
31376#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
31377#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
31378#define SEMC_SDRAMCR3_RT_SHIFT (16U)
31379/* RT - Refresh timer period
31380 * 0b00000000..256*Prescaler period
31381 * 0b00000001-0b11111111..RT*Prescaler period
31382 */
31383#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
31384#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
31385#define SEMC_SDRAMCR3_UT_SHIFT (24U)
31386/* UT - Refresh urgent threshold
31387 * 0b00000000..256*Prescaler period
31388 * 0b00000001-0b11111111..UT*Prescaler period
31389 */
31390#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
31391/* @} */
31392
31393/* @name NANDCR0 - NAND control register 0 */
31394/* @{ */
31395#define SEMC_NANDCR0_PS_MASK (0x1U)
31396#define SEMC_NANDCR0_PS_SHIFT (0U)
31397/* PS - Port Size
31398 * 0b0..8bit
31399 * 0b1..16bit
31400 */
31401#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
31402#define SEMC_NANDCR0_SYNCEN_MASK (0x2U)
31403#define SEMC_NANDCR0_SYNCEN_SHIFT (1U)
31404/* SYNCEN - Select NAND controller mode.
31405 * 0b0..Asynchronous mode is enabled.
31406 * 0b1..Synchronous mode is enabled.
31407 */
31408#define SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
31409#define SEMC_NANDCR0_BL_MASK (0x70U)
31410#define SEMC_NANDCR0_BL_SHIFT (4U)
31411/* BL - Burst Length
31412 * 0b000..1
31413 * 0b001..2
31414 * 0b010..4
31415 * 0b011..8
31416 * 0b100..16
31417 * 0b101..32
31418 * 0b110..64
31419 * 0b111..64
31420 */
31421#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
31422#define SEMC_NANDCR0_EDO_MASK (0x80U)
31423#define SEMC_NANDCR0_EDO_SHIFT (7U)
31424/* EDO - EDO mode enabled
31425 * 0b0..EDO mode disabled
31426 * 0b1..EDO mode enabled
31427 */
31428#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
31429#define SEMC_NANDCR0_COL_MASK (0x700U)
31430#define SEMC_NANDCR0_COL_SHIFT (8U)
31431/* COL - Column address bit number
31432 * 0b000..16
31433 * 0b001..15
31434 * 0b010..14
31435 * 0b011..13
31436 * 0b100..12
31437 * 0b101..11
31438 * 0b110..10
31439 * 0b111..9
31440 */
31441#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
31442/* @} */
31443
31444/* @name NANDCR1 - NAND control register 1 */
31445/* @{ */
31446#define SEMC_NANDCR1_CES_MASK (0xFU)
31447#define SEMC_NANDCR1_CES_SHIFT (0U)
31448#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
31449#define SEMC_NANDCR1_CEH_MASK (0xF0U)
31450#define SEMC_NANDCR1_CEH_SHIFT (4U)
31451#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
31452#define SEMC_NANDCR1_WEL_MASK (0xF00U)
31453#define SEMC_NANDCR1_WEL_SHIFT (8U)
31454#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
31455#define SEMC_NANDCR1_WEH_MASK (0xF000U)
31456#define SEMC_NANDCR1_WEH_SHIFT (12U)
31457#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
31458#define SEMC_NANDCR1_REL_MASK (0xF0000U)
31459#define SEMC_NANDCR1_REL_SHIFT (16U)
31460#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
31461#define SEMC_NANDCR1_REH_MASK (0xF00000U)
31462#define SEMC_NANDCR1_REH_SHIFT (20U)
31463#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
31464#define SEMC_NANDCR1_TA_MASK (0xF000000U)
31465#define SEMC_NANDCR1_TA_SHIFT (24U)
31466#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
31467#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
31468#define SEMC_NANDCR1_CEITV_SHIFT (28U)
31469#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
31470/* @} */
31471
31472/* @name NANDCR2 - NAND control register 2 */
31473/* @{ */
31474#define SEMC_NANDCR2_TWHR_MASK (0x3FU)
31475#define SEMC_NANDCR2_TWHR_SHIFT (0U)
31476#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
31477#define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
31478#define SEMC_NANDCR2_TRHW_SHIFT (6U)
31479#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
31480#define SEMC_NANDCR2_TADL_MASK (0x3F000U)
31481#define SEMC_NANDCR2_TADL_SHIFT (12U)
31482#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
31483#define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
31484#define SEMC_NANDCR2_TRR_SHIFT (18U)
31485#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
31486#define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
31487#define SEMC_NANDCR2_TWB_SHIFT (24U)
31488#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
31489/* @} */
31490
31491/* @name NANDCR3 - NAND control register 3 */
31492/* @{ */
31493#define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
31494#define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
31495#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
31496#define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
31497#define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
31498#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
31499#define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
31500#define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
31501#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
31502#define SEMC_NANDCR3_CLE_MASK (0x8U)
31503#define SEMC_NANDCR3_CLE_SHIFT (3U)
31504#define SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
31505#define SEMC_NANDCR3_RDS_MASK (0xF0000U)
31506#define SEMC_NANDCR3_RDS_SHIFT (16U)
31507#define SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
31508#define SEMC_NANDCR3_RDH_MASK (0xF00000U)
31509#define SEMC_NANDCR3_RDH_SHIFT (20U)
31510#define SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
31511#define SEMC_NANDCR3_WDS_MASK (0xF000000U)
31512#define SEMC_NANDCR3_WDS_SHIFT (24U)
31513#define SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
31514#define SEMC_NANDCR3_WDH_MASK (0xF0000000U)
31515#define SEMC_NANDCR3_WDH_SHIFT (28U)
31516#define SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)
31517/* @} */
31518
31519/* @name NORCR0 - NOR control register 0 */
31520/* @{ */
31521#define SEMC_NORCR0_PS_MASK (0x1U)
31522#define SEMC_NORCR0_PS_SHIFT (0U)
31523/* PS - Port Size
31524 * 0b0..8bit
31525 * 0b1..16bit
31526 */
31527#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
31528#define SEMC_NORCR0_SYNCEN_MASK (0x2U)
31529#define SEMC_NORCR0_SYNCEN_SHIFT (1U)
31530/* SYNCEN - Select NOR controller mode.
31531 * 0b0..Asynchronous mode is enabled.
31532 * 0b1..Synchronous mode is enabled.
31533 */
31534#define SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
31535#define SEMC_NORCR0_BL_MASK (0x70U)
31536#define SEMC_NORCR0_BL_SHIFT (4U)
31537/* BL - Burst Length
31538 * 0b000..1
31539 * 0b001..2
31540 * 0b010..4
31541 * 0b011..8
31542 * 0b100..16
31543 * 0b101..32
31544 * 0b110..64
31545 * 0b111..64
31546 */
31547#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
31548#define SEMC_NORCR0_AM_MASK (0x300U)
31549#define SEMC_NORCR0_AM_SHIFT (8U)
31550/* AM - Address Mode
31551 * 0b00..Address/Data MUX mode
31552 * 0b01..Advanced Address/Data MUX mode
31553 * 0b10..Address/Data non-MUX mode
31554 * 0b11..Address/Data non-MUX mode
31555 */
31556#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
31557#define SEMC_NORCR0_ADVP_MASK (0x400U)
31558#define SEMC_NORCR0_ADVP_SHIFT (10U)
31559/* ADVP - ADV# polarity
31560 * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW.
31561 * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.
31562 */
31563#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
31564#define SEMC_NORCR0_ADVH_MASK (0x800U)
31565#define SEMC_NORCR0_ADVH_SHIFT (11U)
31566/* ADVH - ADV# level control during address hold state
31567 * 0b0..ADV# is high during address hold state.
31568 * 0b1..ADV# is low during address hold state.
31569 */
31570#define SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
31571#define SEMC_NORCR0_COL_MASK (0xF000U)
31572#define SEMC_NORCR0_COL_SHIFT (12U)
31573/* COL - Column Address bit width
31574 * 0b0000..12 Bits
31575 * 0b0001..11 Bits
31576 * 0b0010..10 Bits
31577 * 0b0011..9 Bits
31578 * 0b0100..8 Bits
31579 * 0b0101..7 Bits
31580 * 0b0110..6 Bits
31581 * 0b0111..5 Bits
31582 * 0b1000..4 Bits
31583 * 0b1001..3 Bits
31584 * 0b1010..2 Bits
31585 * 0b1011..12 Bits
31586 * 0b1100..12 Bits
31587 * 0b1101..12 Bits
31588 * 0b1110..12 Bits
31589 * 0b1111..12 Bits
31590 */
31591#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
31592/* @} */
31593
31594/* @name NORCR1 - NOR control register 1 */
31595/* @{ */
31596#define SEMC_NORCR1_CES_MASK (0xFU)
31597#define SEMC_NORCR1_CES_SHIFT (0U)
31598#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
31599#define SEMC_NORCR1_CEH_MASK (0xF0U)
31600#define SEMC_NORCR1_CEH_SHIFT (4U)
31601#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
31602#define SEMC_NORCR1_AS_MASK (0xF00U)
31603#define SEMC_NORCR1_AS_SHIFT (8U)
31604#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
31605#define SEMC_NORCR1_AH_MASK (0xF000U)
31606#define SEMC_NORCR1_AH_SHIFT (12U)
31607#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
31608#define SEMC_NORCR1_WEL_MASK (0xF0000U)
31609#define SEMC_NORCR1_WEL_SHIFT (16U)
31610#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
31611#define SEMC_NORCR1_WEH_MASK (0xF00000U)
31612#define SEMC_NORCR1_WEH_SHIFT (20U)
31613#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
31614#define SEMC_NORCR1_REL_MASK (0xF000000U)
31615#define SEMC_NORCR1_REL_SHIFT (24U)
31616#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
31617#define SEMC_NORCR1_REH_MASK (0xF0000000U)
31618#define SEMC_NORCR1_REH_SHIFT (28U)
31619#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
31620/* @} */
31621
31622/* @name NORCR2 - NOR control register 2 */
31623/* @{ */
31624#define SEMC_NORCR2_TA_MASK (0xF00U)
31625#define SEMC_NORCR2_TA_SHIFT (8U)
31626#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
31627#define SEMC_NORCR2_AWDH_MASK (0xF000U)
31628#define SEMC_NORCR2_AWDH_SHIFT (12U)
31629#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
31630#define SEMC_NORCR2_LC_MASK (0xF0000U)
31631#define SEMC_NORCR2_LC_SHIFT (16U)
31632#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
31633#define SEMC_NORCR2_RD_MASK (0xF00000U)
31634#define SEMC_NORCR2_RD_SHIFT (20U)
31635#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
31636#define SEMC_NORCR2_CEITV_MASK (0xF000000U)
31637#define SEMC_NORCR2_CEITV_SHIFT (24U)
31638#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
31639#define SEMC_NORCR2_RDH_MASK (0xF0000000U)
31640#define SEMC_NORCR2_RDH_SHIFT (28U)
31641#define SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
31642/* @} */
31643
31644/* @name NORCR3 - NOR control register 3 */
31645/* @{ */
31646#define SEMC_NORCR3_ASSR_MASK (0xFU)
31647#define SEMC_NORCR3_ASSR_SHIFT (0U)
31648#define SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
31649#define SEMC_NORCR3_AHSR_MASK (0xF0U)
31650#define SEMC_NORCR3_AHSR_SHIFT (4U)
31651#define SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)
31652/* @} */
31653
31654/* @name SRAMCR0 - SRAM control register 0 */
31655/* @{ */
31656#define SEMC_SRAMCR0_PS_MASK (0x1U)
31657#define SEMC_SRAMCR0_PS_SHIFT (0U)
31658/* PS - Port Size
31659 * 0b0..8bit
31660 * 0b1..16bit
31661 */
31662#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
31663#define SEMC_SRAMCR0_SYNCEN_MASK (0x2U)
31664#define SEMC_SRAMCR0_SYNCEN_SHIFT (1U)
31665/* SYNCEN - Select SRAM controller mode.
31666 * 0b0..Asynchronous mode is enabled.
31667 * 0b1..Synchronous mode is enabled.
31668 */
31669#define SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
31670#define SEMC_SRAMCR0_BL_MASK (0x70U)
31671#define SEMC_SRAMCR0_BL_SHIFT (4U)
31672/* BL - Burst Length
31673 * 0b000..1
31674 * 0b001..2
31675 * 0b010..4
31676 * 0b011..8
31677 * 0b100..16
31678 * 0b101..32
31679 * 0b110..64
31680 * 0b111..64
31681 */
31682#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
31683#define SEMC_SRAMCR0_AM_MASK (0x300U)
31684#define SEMC_SRAMCR0_AM_SHIFT (8U)
31685/* AM - Address Mode
31686 * 0b00..Address/Data MUX mode
31687 * 0b01..Advanced Address/Data MUX mode
31688 * 0b10..Address/Data non-MUX mode
31689 * 0b11..Address/Data non-MUX mode
31690 */
31691#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
31692#define SEMC_SRAMCR0_ADVP_MASK (0x400U)
31693#define SEMC_SRAMCR0_ADVP_SHIFT (10U)
31694/* ADVP - ADV# polarity
31695 * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW.
31696 * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH.
31697 */
31698#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
31699#define SEMC_SRAMCR0_ADVH_MASK (0x800U)
31700#define SEMC_SRAMCR0_ADVH_SHIFT (11U)
31701/* ADVH - ADV# level control during address hold state
31702 * 0b0..ADV# is high during address hold state.
31703 * 0b1..ADV# is low during address hold state.
31704 */
31705#define SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
31706#define SEMC_SRAMCR0_COL_MASK (0xF000U)
31707#define SEMC_SRAMCR0_COL_SHIFT (12U)
31708/* COL - Column Address bit width
31709 * 0b0000..12 Bits
31710 * 0b0001..11 Bits
31711 * 0b0010..10 Bits
31712 * 0b0011..9 Bits
31713 * 0b0100..8 Bits
31714 * 0b0101..7 Bits
31715 * 0b0110..6 Bits
31716 * 0b0111..5 Bits
31717 * 0b1000..4 Bits
31718 * 0b1001..3 Bits
31719 * 0b1010..2 Bits
31720 * 0b1011..12 Bits
31721 * 0b1100..12 Bits
31722 * 0b1101..12 Bits
31723 * 0b1110..12 Bits
31724 * 0b1111..12 Bits
31725 */
31726#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
31727/* @} */
31728
31729/* @name SRAMCR1 - SRAM control register 1 */
31730/* @{ */
31731#define SEMC_SRAMCR1_CES_MASK (0xFU)
31732#define SEMC_SRAMCR1_CES_SHIFT (0U)
31733#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
31734#define SEMC_SRAMCR1_CEH_MASK (0xF0U)
31735#define SEMC_SRAMCR1_CEH_SHIFT (4U)
31736#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
31737#define SEMC_SRAMCR1_AS_MASK (0xF00U)
31738#define SEMC_SRAMCR1_AS_SHIFT (8U)
31739#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
31740#define SEMC_SRAMCR1_AH_MASK (0xF000U)
31741#define SEMC_SRAMCR1_AH_SHIFT (12U)
31742#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
31743#define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
31744#define SEMC_SRAMCR1_WEL_SHIFT (16U)
31745#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
31746#define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
31747#define SEMC_SRAMCR1_WEH_SHIFT (20U)
31748#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
31749#define SEMC_SRAMCR1_REL_MASK (0xF000000U)
31750#define SEMC_SRAMCR1_REL_SHIFT (24U)
31751#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
31752#define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
31753#define SEMC_SRAMCR1_REH_SHIFT (28U)
31754#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
31755/* @} */
31756
31757/* @name SRAMCR2 - SRAM control register 2 */
31758/* @{ */
31759#define SEMC_SRAMCR2_WDS_MASK (0xFU)
31760#define SEMC_SRAMCR2_WDS_SHIFT (0U)
31761#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
31762#define SEMC_SRAMCR2_WDH_MASK (0xF0U)
31763#define SEMC_SRAMCR2_WDH_SHIFT (4U)
31764#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
31765#define SEMC_SRAMCR2_TA_MASK (0xF00U)
31766#define SEMC_SRAMCR2_TA_SHIFT (8U)
31767#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
31768#define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
31769#define SEMC_SRAMCR2_AWDH_SHIFT (12U)
31770#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
31771#define SEMC_SRAMCR2_LC_MASK (0xF0000U)
31772#define SEMC_SRAMCR2_LC_SHIFT (16U)
31773#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
31774#define SEMC_SRAMCR2_RD_MASK (0xF00000U)
31775#define SEMC_SRAMCR2_RD_SHIFT (20U)
31776#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
31777#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
31778#define SEMC_SRAMCR2_CEITV_SHIFT (24U)
31779#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
31780#define SEMC_SRAMCR2_RDH_MASK (0xF0000000U)
31781#define SEMC_SRAMCR2_RDH_SHIFT (28U)
31782#define SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)
31783/* @} */
31784
31785/* @name DBICR0 - DBI-B control register 0 */
31786/* @{ */
31787#define SEMC_DBICR0_PS_MASK (0x1U)
31788#define SEMC_DBICR0_PS_SHIFT (0U)
31789/* PS - Port Size
31790 * 0b0..8bit
31791 * 0b1..16bit
31792 */
31793#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
31794#define SEMC_DBICR0_BL_MASK (0x70U)
31795#define SEMC_DBICR0_BL_SHIFT (4U)
31796/* BL - Burst Length
31797 * 0b000..1
31798 * 0b001..2
31799 * 0b010..4
31800 * 0b011..8
31801 * 0b100..16
31802 * 0b101..32
31803 * 0b110..64
31804 * 0b111..64
31805 */
31806#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
31807#define SEMC_DBICR0_COL_MASK (0xF000U)
31808#define SEMC_DBICR0_COL_SHIFT (12U)
31809/* COL - Column Address bit width
31810 * 0b0000..12 Bits
31811 * 0b0001..11 Bits
31812 * 0b0010..10 Bits
31813 * 0b0011..9 Bits
31814 * 0b0100..8 Bits
31815 * 0b0101..7 Bits
31816 * 0b0110..6 Bits
31817 * 0b0111..5 Bits
31818 * 0b1000..4 Bits
31819 * 0b1001..3 Bits
31820 * 0b1010..2 Bits
31821 * 0b1011..12 Bits
31822 * 0b1100..12 Bits
31823 * 0b1101..12 Bits
31824 * 0b1110..12 Bits
31825 * 0b1111..12 Bits
31826 */
31827#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
31828/* @} */
31829
31830/* @name DBICR1 - DBI-B control register 1 */
31831/* @{ */
31832#define SEMC_DBICR1_CES_MASK (0xFU)
31833#define SEMC_DBICR1_CES_SHIFT (0U)
31834#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
31835#define SEMC_DBICR1_CEH_MASK (0xF0U)
31836#define SEMC_DBICR1_CEH_SHIFT (4U)
31837#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
31838#define SEMC_DBICR1_WEL_MASK (0xF00U)
31839#define SEMC_DBICR1_WEL_SHIFT (8U)
31840#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
31841#define SEMC_DBICR1_WEH_MASK (0xF000U)
31842#define SEMC_DBICR1_WEH_SHIFT (12U)
31843#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
31844#define SEMC_DBICR1_REL_MASK (0x3F0000U)
31845#define SEMC_DBICR1_REL_SHIFT (16U)
31846#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
31847#define SEMC_DBICR1_REH_MASK (0xFC00000U)
31848#define SEMC_DBICR1_REH_SHIFT (22U)
31849#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
31850#define SEMC_DBICR1_CEITV_MASK (0xF0000000U)
31851#define SEMC_DBICR1_CEITV_SHIFT (28U)
31852#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK)
31853/* @} */
31854
31855/* @name IPCR0 - IP Command control register 0 */
31856/* @{ */
31857#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
31858#define SEMC_IPCR0_SA_SHIFT (0U)
31859#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
31860/* @} */
31861
31862/* @name IPCR1 - IP Command control register 1 */
31863/* @{ */
31864#define SEMC_IPCR1_DATSZ_MASK (0x7U)
31865#define SEMC_IPCR1_DATSZ_SHIFT (0U)
31866/* DATSZ - Data Size in Byte
31867 * 0b000..4
31868 * 0b001..1
31869 * 0b010..2
31870 * 0b011..3
31871 * 0b100..4
31872 * 0b101..4
31873 * 0b110..4
31874 * 0b111..4
31875 */
31876#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
31877#define SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U)
31878#define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U)
31879#define SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)
31880/* @} */
31881
31882/* @name IPCR2 - IP Command control register 2 */
31883/* @{ */
31884#define SEMC_IPCR2_BM0_MASK (0x1U)
31885#define SEMC_IPCR2_BM0_SHIFT (0U)
31886/* BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0)
31887 * 0b0..Byte Unmasked
31888 * 0b1..Byte Masked
31889 */
31890#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
31891#define SEMC_IPCR2_BM1_MASK (0x2U)
31892#define SEMC_IPCR2_BM1_SHIFT (1U)
31893/* BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8)
31894 * 0b0..Byte Unmasked
31895 * 0b1..Byte Masked
31896 */
31897#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
31898#define SEMC_IPCR2_BM2_MASK (0x4U)
31899#define SEMC_IPCR2_BM2_SHIFT (2U)
31900/* BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16)
31901 * 0b0..Byte Unmasked
31902 * 0b1..Byte Masked
31903 */
31904#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
31905#define SEMC_IPCR2_BM3_MASK (0x8U)
31906#define SEMC_IPCR2_BM3_SHIFT (3U)
31907/* BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24)
31908 * 0b0..Byte Unmasked
31909 * 0b1..Byte Masked
31910 */
31911#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
31912/* @} */
31913
31914/* @name IPCMD - IP Command register */
31915/* @{ */
31916#define SEMC_IPCMD_CMD_MASK (0xFFFFU)
31917#define SEMC_IPCMD_CMD_SHIFT (0U)
31918#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
31919#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
31920#define SEMC_IPCMD_KEY_SHIFT (16U)
31921#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
31922/* @} */
31923
31924/* @name IPTXDAT - TX DATA register (for IP Command) */
31925/* @{ */
31926#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
31927#define SEMC_IPTXDAT_DAT_SHIFT (0U)
31928#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
31929/* @} */
31930
31931/* @name IPRXDAT - RX DATA register (for IP Command) */
31932/* @{ */
31933#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
31934#define SEMC_IPRXDAT_DAT_SHIFT (0U)
31935#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
31936/* @} */
31937
31938/* @name STS0 - Status register 0 */
31939/* @{ */
31940#define SEMC_STS0_IDLE_MASK (0x1U)
31941#define SEMC_STS0_IDLE_SHIFT (0U)
31942#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
31943#define SEMC_STS0_NARDY_MASK (0x2U)
31944#define SEMC_STS0_NARDY_SHIFT (1U)
31945/* NARDY - Indicating NAND device Ready/WAIT# pin level.
31946 * 0b0..NAND device is not ready
31947 * 0b1..NAND device is ready
31948 */
31949#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
31950/* @} */
31951
31952/* @name STS2 - Status register 2 */
31953/* @{ */
31954#define SEMC_STS2_NDWRPEND_MASK (0x8U)
31955#define SEMC_STS2_NDWRPEND_SHIFT (3U)
31956/* NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device.
31957 * 0b0..No pending
31958 * 0b1..Pending
31959 */
31960#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
31961/* @} */
31962
31963/* @name STS12 - Status register 12 */
31964/* @{ */
31965#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
31966#define SEMC_STS12_NDADDR_SHIFT (0U)
31967#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
31968/* @} */
31969
31970/* @name STS13 - Status register 13 */
31971/* @{ */
31972#define SEMC_STS13_SLVLOCK_MASK (0x1U)
31973#define SEMC_STS13_SLVLOCK_SHIFT (0U)
31974#define SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
31975#define SEMC_STS13_REFLOCK_MASK (0x2U)
31976#define SEMC_STS13_REFLOCK_SHIFT (1U)
31977#define SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
31978#define SEMC_STS13_SLVSEL_MASK (0xFCU)
31979#define SEMC_STS13_SLVSEL_SHIFT (2U)
31980#define SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
31981#define SEMC_STS13_REFSEL_MASK (0x3F00U)
31982#define SEMC_STS13_REFSEL_SHIFT (8U)
31983#define SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)
31984/* @} */
31985
31986
31987/*
31988 * @}
31989 */ /* end of group SEMC_Register_Masks */
31990
31991
31992/* SEMC - Peripheral instance base addresses */
31993/* Peripheral SEMC base address */
31994#define SEMC_BASE (0x402F0000u)
31995/* Peripheral SEMC base pointer */
31996#define SEMC ((SEMC_Type *)SEMC_BASE)
31997/* Array initializer of SEMC peripheral base addresses */
31998#define SEMC_BASE_ADDRS { SEMC_BASE }
31999/* Array initializer of SEMC peripheral base pointers */
32000#define SEMC_BASE_PTRS { SEMC }
32001/* Interrupt vectors for the SEMC peripheral type */
32002#define SEMC_IRQS { SEMC_IRQn }
32003
32004/*
32005 * @}
32006 */ /* end of group SEMC_Peripheral_Access_Layer */
32007
32008
32009/* ----------------------------------------------------------------------------
32010 -- SNVS Peripheral Access Layer
32011 ---------------------------------------------------------------------------- */
32012
32013/*
32014 * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
32015 * @{
32016 */
32017
32018/* SNVS - Register Layout Typedef */
32019typedef struct {
32020 __IO uint32_t HPLR;
32021 __IO uint32_t HPCOMR;
32022 __IO uint32_t HPCR;
32023 __IO uint32_t HPSICR;
32024 __IO uint32_t HPSVCR;
32025 __IO uint32_t HPSR;
32026 __IO uint32_t HPSVSR;
32027 __IO uint32_t HPHACIVR;
32028 __I uint32_t HPHACR;
32029 __IO uint32_t HPRTCMR;
32030 __IO uint32_t HPRTCLR;
32031 __IO uint32_t HPTAMR;
32032 __IO uint32_t HPTALR;
32033 __IO uint32_t LPLR;
32034 __IO uint32_t LPCR;
32035 __IO uint32_t LPMKCR;
32036 __IO uint32_t LPSVCR;
32037 uint8_t RESERVED_0[4];
32038 __IO uint32_t LPTDCR;
32039 __IO uint32_t LPSR;
32040 __IO uint32_t LPSRTCMR;
32041 __IO uint32_t LPSRTCLR;
32042 __IO uint32_t LPTAR;
32043 __I uint32_t LPSMCMR;
32044 __I uint32_t LPSMCLR;
32045 __IO uint32_t LPPGDR;
32046 __IO uint32_t LPGPR0_LEGACY_ALIAS;
32047 __IO uint32_t LPZMKR[8];
32048 uint8_t RESERVED_1[4];
32049 __IO uint32_t LPGPR_ALIAS[4];
32050 uint8_t RESERVED_2[96];
32051 __IO uint32_t LPGPR[8];
32052 uint8_t RESERVED_3[2776];
32053 __I uint32_t HPVIDR1;
32054 __I uint32_t HPVIDR2;
32055} SNVS_Type;
32056
32057/* ----------------------------------------------------------------------------
32058 -- SNVS Register Masks
32059 ---------------------------------------------------------------------------- */
32060
32061/*
32062 * @addtogroup SNVS_Register_Masks SNVS Register Masks
32063 * @{
32064 */
32065
32066/* @name HPLR - SNVS_HP Lock Register */
32067/* @{ */
32068#define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
32069#define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
32070/* ZMK_WSL
32071 * 0b0..Write access is allowed
32072 * 0b1..Write access is not allowed
32073 */
32074#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
32075#define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
32076#define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
32077/* ZMK_RSL
32078 * 0b0..Read access is allowed (only in software Programming mode)
32079 * 0b1..Read access is not allowed
32080 */
32081#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
32082#define SNVS_HPLR_SRTC_SL_MASK (0x4U)
32083#define SNVS_HPLR_SRTC_SL_SHIFT (2U)
32084/* SRTC_SL
32085 * 0b0..Write access is allowed
32086 * 0b1..Write access is not allowed
32087 */
32088#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
32089#define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
32090#define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
32091/* LPCALB_SL
32092 * 0b0..Write access is allowed
32093 * 0b1..Write access is not allowed
32094 */
32095#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
32096#define SNVS_HPLR_MC_SL_MASK (0x10U)
32097#define SNVS_HPLR_MC_SL_SHIFT (4U)
32098/* MC_SL
32099 * 0b0..Write access (increment) is allowed
32100 * 0b1..Write access (increment) is not allowed
32101 */
32102#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
32103#define SNVS_HPLR_GPR_SL_MASK (0x20U)
32104#define SNVS_HPLR_GPR_SL_SHIFT (5U)
32105/* GPR_SL
32106 * 0b0..Write access is allowed
32107 * 0b1..Write access is not allowed
32108 */
32109#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
32110#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
32111#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
32112/* LPSVCR_SL
32113 * 0b0..Write access is allowed
32114 * 0b1..Write access is not allowed
32115 */
32116#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
32117#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U)
32118#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U)
32119/* LPTDCR_SL
32120 * 0b0..Write access is allowed
32121 * 0b1..Write access is not allowed
32122 */
32123#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK)
32124#define SNVS_HPLR_MKS_SL_MASK (0x200U)
32125#define SNVS_HPLR_MKS_SL_SHIFT (9U)
32126/* MKS_SL
32127 * 0b0..Write access is allowed
32128 * 0b1..Write access is not allowed
32129 */
32130#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
32131#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
32132#define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
32133/* HPSVCR_L
32134 * 0b0..Write access is allowed
32135 * 0b1..Write access is not allowed
32136 */
32137#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
32138#define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
32139#define SNVS_HPLR_HPSICR_L_SHIFT (17U)
32140/* HPSICR_L
32141 * 0b0..Write access is allowed
32142 * 0b1..Write access is not allowed
32143 */
32144#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
32145#define SNVS_HPLR_HAC_L_MASK (0x40000U)
32146#define SNVS_HPLR_HAC_L_SHIFT (18U)
32147/* HAC_L
32148 * 0b0..Write access is allowed
32149 * 0b1..Write access is not allowed
32150 */
32151#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
32152/* @} */
32153
32154/* @name HPCOMR - SNVS_HP Command Register */
32155/* @{ */
32156#define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
32157#define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
32158#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
32159#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
32160#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
32161/* SSM_ST_DIS
32162 * 0b0..Secure to Trusted State transition is enabled
32163 * 0b1..Secure to Trusted State transition is disabled
32164 */
32165#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
32166#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
32167#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
32168/* SSM_SFNS_DIS
32169 * 0b0..Soft Fail to Non-Secure State transition is enabled
32170 * 0b1..Soft Fail to Non-Secure State transition is disabled
32171 */
32172#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
32173#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
32174#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
32175/* LP_SWR
32176 * 0b0..No Action
32177 * 0b1..Reset LP section
32178 */
32179#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
32180#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
32181#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
32182/* LP_SWR_DIS
32183 * 0b0..LP software reset is enabled
32184 * 0b1..LP software reset is disabled
32185 */
32186#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
32187#define SNVS_HPCOMR_SW_SV_MASK (0x100U)
32188#define SNVS_HPCOMR_SW_SV_SHIFT (8U)
32189#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
32190#define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
32191#define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
32192#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
32193#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
32194#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
32195#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
32196#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
32197#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
32198/* PROG_ZMK
32199 * 0b0..No Action
32200 * 0b1..Activate hardware key programming mechanism
32201 */
32202#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
32203#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
32204#define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
32205/* MKS_EN
32206 * 0b0..OTP master key is selected as an SNVS master key
32207 * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
32208 */
32209#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
32210#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
32211#define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
32212/* HAC_EN
32213 * 0b0..High Assurance Counter is disabled
32214 * 0b1..High Assurance Counter is enabled
32215 */
32216#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
32217#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
32218#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
32219/* HAC_LOAD
32220 * 0b0..No Action
32221 * 0b1..Load the HAC
32222 */
32223#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
32224#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
32225#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
32226/* HAC_CLEAR
32227 * 0b0..No Action
32228 * 0b1..Clear the HAC
32229 */
32230#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
32231#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
32232#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
32233#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
32234#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
32235#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
32236#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
32237/* @} */
32238
32239/* @name HPCR - SNVS_HP Control Register */
32240/* @{ */
32241#define SNVS_HPCR_RTC_EN_MASK (0x1U)
32242#define SNVS_HPCR_RTC_EN_SHIFT (0U)
32243/* RTC_EN
32244 * 0b0..RTC is disabled
32245 * 0b1..RTC is enabled
32246 */
32247#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
32248#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
32249#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
32250/* HPTA_EN
32251 * 0b0..HP Time Alarm Interrupt is disabled
32252 * 0b1..HP Time Alarm Interrupt is enabled
32253 */
32254#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
32255#define SNVS_HPCR_DIS_PI_MASK (0x4U)
32256#define SNVS_HPCR_DIS_PI_SHIFT (2U)
32257/* DIS_PI
32258 * 0b0..Periodic interrupt will trigger a functional interrupt
32259 * 0b1..Disable periodic interrupt in the function interrupt
32260 */
32261#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
32262#define SNVS_HPCR_PI_EN_MASK (0x8U)
32263#define SNVS_HPCR_PI_EN_SHIFT (3U)
32264/* PI_EN
32265 * 0b0..HP Periodic Interrupt is disabled
32266 * 0b1..HP Periodic Interrupt is enabled
32267 */
32268#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
32269#define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
32270#define SNVS_HPCR_PI_FREQ_SHIFT (4U)
32271/* PI_FREQ
32272 * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
32273 * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
32274 * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
32275 * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
32276 * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
32277 * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
32278 * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
32279 * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
32280 * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
32281 * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
32282 * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
32283 * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
32284 * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
32285 * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
32286 * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
32287 * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
32288 */
32289#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
32290#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
32291#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
32292/* HPCALB_EN
32293 * 0b0..HP Timer calibration disabled
32294 * 0b1..HP Timer calibration enabled
32295 */
32296#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
32297#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
32298#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
32299/* HPCALB_VAL
32300 * 0b00000..+0 counts per each 32768 ticks of the counter
32301 * 0b00001..+1 counts per each 32768 ticks of the counter
32302 * 0b00010..+2 counts per each 32768 ticks of the counter
32303 * 0b01111..+15 counts per each 32768 ticks of the counter
32304 * 0b10000..-16 counts per each 32768 ticks of the counter
32305 * 0b10001..-15 counts per each 32768 ticks of the counter
32306 * 0b11110..-2 counts per each 32768 ticks of the counter
32307 * 0b11111..-1 counts per each 32768 ticks of the counter
32308 */
32309#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
32310#define SNVS_HPCR_HP_TS_MASK (0x10000U)
32311#define SNVS_HPCR_HP_TS_SHIFT (16U)
32312/* HP_TS
32313 * 0b0..No Action
32314 * 0b1..Synchronize the HP Time Counter to the LP Time Counter
32315 */
32316#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
32317#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
32318#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
32319#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
32320#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
32321#define SNVS_HPCR_BTN_MASK_SHIFT (27U)
32322#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
32323/* @} */
32324
32325/* @name HPSICR - SNVS_HP Security Interrupt Control Register */
32326/* @{ */
32327#define SNVS_HPSICR_SV0_EN_MASK (0x1U)
32328#define SNVS_HPSICR_SV0_EN_SHIFT (0U)
32329/* SV0_EN
32330 * 0b0..Security Violation 0 Interrupt is Disabled
32331 * 0b1..Security Violation 0 Interrupt is Enabled
32332 */
32333#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK)
32334#define SNVS_HPSICR_SV1_EN_MASK (0x2U)
32335#define SNVS_HPSICR_SV1_EN_SHIFT (1U)
32336/* SV1_EN
32337 * 0b0..Security Violation 1 Interrupt is Disabled
32338 * 0b1..Security Violation 1 Interrupt is Enabled
32339 */
32340#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK)
32341#define SNVS_HPSICR_SV2_EN_MASK (0x4U)
32342#define SNVS_HPSICR_SV2_EN_SHIFT (2U)
32343/* SV2_EN
32344 * 0b0..Security Violation 2 Interrupt is Disabled
32345 * 0b1..Security Violation 2 Interrupt is Enabled
32346 */
32347#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK)
32348#define SNVS_HPSICR_SV3_EN_MASK (0x8U)
32349#define SNVS_HPSICR_SV3_EN_SHIFT (3U)
32350/* SV3_EN
32351 * 0b0..Security Violation 3 Interrupt is Disabled
32352 * 0b1..Security Violation 3 Interrupt is Enabled
32353 */
32354#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK)
32355#define SNVS_HPSICR_SV4_EN_MASK (0x10U)
32356#define SNVS_HPSICR_SV4_EN_SHIFT (4U)
32357/* SV4_EN
32358 * 0b0..Security Violation 4 Interrupt is Disabled
32359 * 0b1..Security Violation 4 Interrupt is Enabled
32360 */
32361#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK)
32362#define SNVS_HPSICR_SV5_EN_MASK (0x20U)
32363#define SNVS_HPSICR_SV5_EN_SHIFT (5U)
32364/* SV5_EN
32365 * 0b0..Security Violation 5 Interrupt is Disabled
32366 * 0b1..Security Violation 5 Interrupt is Enabled
32367 */
32368#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK)
32369#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
32370#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
32371/* LPSVI_EN
32372 * 0b0..LP Security Violation Interrupt is Disabled
32373 * 0b1..LP Security Violation Interrupt is Enabled
32374 */
32375#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
32376/* @} */
32377
32378/* @name HPSVCR - SNVS_HP Security Violation Control Register */
32379/* @{ */
32380#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U)
32381#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U)
32382/* SV0_CFG
32383 * 0b0..Security Violation 0 is a non-fatal violation
32384 * 0b1..Security Violation 0 is a fatal violation
32385 */
32386#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK)
32387#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U)
32388#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U)
32389/* SV1_CFG
32390 * 0b0..Security Violation 1 is a non-fatal violation
32391 * 0b1..Security Violation 1 is a fatal violation
32392 */
32393#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK)
32394#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U)
32395#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U)
32396/* SV2_CFG
32397 * 0b0..Security Violation 2 is a non-fatal violation
32398 * 0b1..Security Violation 2 is a fatal violation
32399 */
32400#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK)
32401#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U)
32402#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U)
32403/* SV3_CFG
32404 * 0b0..Security Violation 3 is a non-fatal violation
32405 * 0b1..Security Violation 3 is a fatal violation
32406 */
32407#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK)
32408#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U)
32409#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U)
32410/* SV4_CFG
32411 * 0b0..Security Violation 4 is a non-fatal violation
32412 * 0b1..Security Violation 4 is a fatal violation
32413 */
32414#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK)
32415#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U)
32416#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U)
32417/* SV5_CFG
32418 * 0b00..Security Violation 5 is disabled
32419 * 0b01..Security Violation 5 is a non-fatal violation
32420 * 0b1x..Security Violation 5 is a fatal violation
32421 */
32422#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK)
32423#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
32424#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
32425/* LPSV_CFG
32426 * 0b00..LP security violation is disabled
32427 * 0b01..LP security violation is a non-fatal violation
32428 * 0b1x..LP security violation is a fatal violation
32429 */
32430#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
32431/* @} */
32432
32433/* @name HPSR - SNVS_HP Status Register */
32434/* @{ */
32435#define SNVS_HPSR_HPTA_MASK (0x1U)
32436#define SNVS_HPSR_HPTA_SHIFT (0U)
32437/* HPTA
32438 * 0b0..No time alarm interrupt occurred.
32439 * 0b1..A time alarm interrupt occurred.
32440 */
32441#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
32442#define SNVS_HPSR_PI_MASK (0x2U)
32443#define SNVS_HPSR_PI_SHIFT (1U)
32444/* PI
32445 * 0b0..No periodic interrupt occurred.
32446 * 0b1..A periodic interrupt occurred.
32447 */
32448#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
32449#define SNVS_HPSR_LPDIS_MASK (0x10U)
32450#define SNVS_HPSR_LPDIS_SHIFT (4U)
32451#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
32452#define SNVS_HPSR_BTN_MASK (0x40U)
32453#define SNVS_HPSR_BTN_SHIFT (6U)
32454#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
32455#define SNVS_HPSR_BI_MASK (0x80U)
32456#define SNVS_HPSR_BI_SHIFT (7U)
32457#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
32458#define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
32459#define SNVS_HPSR_SSM_STATE_SHIFT (8U)
32460/* SSM_STATE
32461 * 0b0000..Init
32462 * 0b0001..Hard Fail
32463 * 0b0011..Soft Fail
32464 * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
32465 * 0b1001..Check
32466 * 0b1011..Non-Secure
32467 * 0b1101..Trusted
32468 * 0b1111..Secure
32469 */
32470#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
32471#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U)
32472#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U)
32473/* SECURITY_CONFIG
32474 * 0b0000, 0b1000..FAB configuration
32475 * 0b0001, 0b0010, 0b0011..OPEN configuration
32476 * 0b1010, 0b1001, 0b1011..CLOSED configuration
32477 * 0bx1xx..FIELD RETURN configuration
32478 */
32479#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK)
32480#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U)
32481#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U)
32482#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK)
32483#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
32484#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
32485/* OTPMK_ZERO
32486 * 0b0..The OTPMK is not zero.
32487 * 0b1..The OTPMK is zero.
32488 */
32489#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
32490#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
32491#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
32492/* ZMK_ZERO
32493 * 0b0..The ZMK is not zero.
32494 * 0b1..The ZMK is zero.
32495 */
32496#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
32497/* @} */
32498
32499/* @name HPSVSR - SNVS_HP Security Violation Status Register */
32500/* @{ */
32501#define SNVS_HPSVSR_SV0_MASK (0x1U)
32502#define SNVS_HPSVSR_SV0_SHIFT (0U)
32503/* SV0
32504 * 0b0..No Security Violation 0 security violation was detected.
32505 * 0b1..Security Violation 0 security violation was detected.
32506 */
32507#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK)
32508#define SNVS_HPSVSR_SV1_MASK (0x2U)
32509#define SNVS_HPSVSR_SV1_SHIFT (1U)
32510/* SV1
32511 * 0b0..No Security Violation 1 security violation was detected.
32512 * 0b1..Security Violation 1 security violation was detected.
32513 */
32514#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK)
32515#define SNVS_HPSVSR_SV2_MASK (0x4U)
32516#define SNVS_HPSVSR_SV2_SHIFT (2U)
32517/* SV2
32518 * 0b0..No Security Violation 2 security violation was detected.
32519 * 0b1..Security Violation 2 security violation was detected.
32520 */
32521#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK)
32522#define SNVS_HPSVSR_SV3_MASK (0x8U)
32523#define SNVS_HPSVSR_SV3_SHIFT (3U)
32524/* SV3
32525 * 0b0..No Security Violation 3 security violation was detected.
32526 * 0b1..Security Violation 3 security violation was detected.
32527 */
32528#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK)
32529#define SNVS_HPSVSR_SV4_MASK (0x10U)
32530#define SNVS_HPSVSR_SV4_SHIFT (4U)
32531/* SV4
32532 * 0b0..No Security Violation 4 security violation was detected.
32533 * 0b1..Security Violation 4 security violation was detected.
32534 */
32535#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK)
32536#define SNVS_HPSVSR_SV5_MASK (0x20U)
32537#define SNVS_HPSVSR_SV5_SHIFT (5U)
32538/* SV5
32539 * 0b0..No Security Violation 5 security violation was detected.
32540 * 0b1..Security Violation 5 security violation was detected.
32541 */
32542#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
32543#define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
32544#define SNVS_HPSVSR_SW_SV_SHIFT (13U)
32545#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
32546#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
32547#define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
32548#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
32549#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
32550#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
32551#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
32552#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
32553#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
32554#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
32555#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
32556#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
32557/* ZMK_ECC_FAIL
32558 * 0b0..ZMK ECC Failure was not detected.
32559 * 0b1..ZMK ECC Failure was detected.
32560 */
32561#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
32562#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
32563#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
32564#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
32565/* @} */
32566
32567/* @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
32568/* @{ */
32569#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
32570#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
32571#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
32572/* @} */
32573
32574/* @name HPHACR - SNVS_HP High Assurance Counter Register */
32575/* @{ */
32576#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
32577#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
32578#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
32579/* @} */
32580
32581/* @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
32582/* @{ */
32583#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
32584#define SNVS_HPRTCMR_RTC_SHIFT (0U)
32585#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
32586/* @} */
32587
32588/* @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
32589/* @{ */
32590#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
32591#define SNVS_HPRTCLR_RTC_SHIFT (0U)
32592#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
32593/* @} */
32594
32595/* @name HPTAMR - SNVS_HP Time Alarm MSB Register */
32596/* @{ */
32597#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
32598#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
32599#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
32600/* @} */
32601
32602/* @name HPTALR - SNVS_HP Time Alarm LSB Register */
32603/* @{ */
32604#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
32605#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
32606#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
32607/* @} */
32608
32609/* @name LPLR - SNVS_LP Lock Register */
32610/* @{ */
32611#define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
32612#define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
32613/* ZMK_WHL
32614 * 0b0..Write access is allowed.
32615 * 0b1..Write access is not allowed.
32616 */
32617#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
32618#define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
32619#define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
32620/* ZMK_RHL
32621 * 0b0..Read access is allowed (only in software programming mode).
32622 * 0b1..Read access is not allowed.
32623 */
32624#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
32625#define SNVS_LPLR_SRTC_HL_MASK (0x4U)
32626#define SNVS_LPLR_SRTC_HL_SHIFT (2U)
32627/* SRTC_HL
32628 * 0b0..Write access is allowed.
32629 * 0b1..Write access is not allowed.
32630 */
32631#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
32632#define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
32633#define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
32634/* LPCALB_HL
32635 * 0b0..Write access is allowed.
32636 * 0b1..Write access is not allowed.
32637 */
32638#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
32639#define SNVS_LPLR_MC_HL_MASK (0x10U)
32640#define SNVS_LPLR_MC_HL_SHIFT (4U)
32641/* MC_HL
32642 * 0b0..Write access (increment) is allowed.
32643 * 0b1..Write access (increment) is not allowed.
32644 */
32645#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
32646#define SNVS_LPLR_GPR_HL_MASK (0x20U)
32647#define SNVS_LPLR_GPR_HL_SHIFT (5U)
32648/* GPR_HL
32649 * 0b0..Write access is allowed.
32650 * 0b1..Write access is not allowed.
32651 */
32652#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
32653#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
32654#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
32655/* LPSVCR_HL
32656 * 0b0..Write access is allowed.
32657 * 0b1..Write access is not allowed.
32658 */
32659#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
32660#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U)
32661#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U)
32662/* LPTDCR_HL
32663 * 0b0..Write access is allowed.
32664 * 0b1..Write access is not allowed.
32665 */
32666#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK)
32667#define SNVS_LPLR_MKS_HL_MASK (0x200U)
32668#define SNVS_LPLR_MKS_HL_SHIFT (9U)
32669/* MKS_HL
32670 * 0b0..Write access is allowed.
32671 * 0b1..Write access is not allowed.
32672 */
32673#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
32674/* @} */
32675
32676/* @name LPCR - SNVS_LP Control Register */
32677/* @{ */
32678#define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
32679#define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
32680/* SRTC_ENV
32681 * 0b0..SRTC is disabled or invalid.
32682 * 0b1..SRTC is enabled and valid.
32683 */
32684#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
32685#define SNVS_LPCR_LPTA_EN_MASK (0x2U)
32686#define SNVS_LPCR_LPTA_EN_SHIFT (1U)
32687/* LPTA_EN
32688 * 0b0..LP time alarm interrupt is disabled.
32689 * 0b1..LP time alarm interrupt is enabled.
32690 */
32691#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
32692#define SNVS_LPCR_MC_ENV_MASK (0x4U)
32693#define SNVS_LPCR_MC_ENV_SHIFT (2U)
32694/* MC_ENV
32695 * 0b0..MC is disabled or invalid.
32696 * 0b1..MC is enabled and valid.
32697 */
32698#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
32699#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
32700#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
32701#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
32702#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
32703#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
32704/* SRTC_INV_EN
32705 * 0b0..SRTC stays valid in the case of security violation.
32706 * 0b1..SRTC is invalidated in the case of security violation.
32707 */
32708#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
32709#define SNVS_LPCR_DP_EN_MASK (0x20U)
32710#define SNVS_LPCR_DP_EN_SHIFT (5U)
32711/* DP_EN
32712 * 0b0..Smart PMIC enabled.
32713 * 0b1..Dumb PMIC enabled.
32714 */
32715#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
32716#define SNVS_LPCR_TOP_MASK (0x40U)
32717#define SNVS_LPCR_TOP_SHIFT (6U)
32718/* TOP
32719 * 0b0..Leave system power on.
32720 * 0b1..Turn off system power.
32721 */
32722#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
32723#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U)
32724#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U)
32725#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK)
32726#define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
32727#define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
32728/* LPCALB_EN
32729 * 0b0..SRTC Time calibration is disabled.
32730 * 0b1..SRTC Time calibration is enabled.
32731 */
32732#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
32733#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
32734#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
32735/* LPCALB_VAL
32736 * 0b00000..+0 counts per each 32768 ticks of the counter clock
32737 * 0b00001..+1 counts per each 32768 ticks of the counter clock
32738 * 0b00010..+2 counts per each 32768 ticks of the counter clock
32739 * 0b01111..+15 counts per each 32768 ticks of the counter clock
32740 * 0b10000..-16 counts per each 32768 ticks of the counter clock
32741 * 0b10001..-15 counts per each 32768 ticks of the counter clock
32742 * 0b11110..-2 counts per each 32768 ticks of the counter clock
32743 * 0b11111..-1 counts per each 32768 ticks of the counter clock
32744 */
32745#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
32746#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
32747#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
32748#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
32749#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
32750#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
32751#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
32752#define SNVS_LPCR_ON_TIME_MASK (0x300000U)
32753#define SNVS_LPCR_ON_TIME_SHIFT (20U)
32754#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
32755#define SNVS_LPCR_PK_EN_MASK (0x400000U)
32756#define SNVS_LPCR_PK_EN_SHIFT (22U)
32757#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
32758#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
32759#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
32760#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
32761#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
32762#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
32763#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
32764/* @} */
32765
32766/* @name LPMKCR - SNVS_LP Master Key Control Register */
32767/* @{ */
32768#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
32769#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
32770/* MASTER_KEY_SEL
32771 * 0b0x..Select one time programmable master key.
32772 * 0b10..Select zeroizable master key when MKS_EN bit is set .
32773 * 0b11..Select combined master key when MKS_EN bit is set .
32774 */
32775#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
32776#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
32777#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
32778/* ZMK_HWP
32779 * 0b0..ZMK is in the software programming mode.
32780 * 0b1..ZMK is in the hardware programming mode.
32781 */
32782#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
32783#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
32784#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
32785/* ZMK_VAL
32786 * 0b0..ZMK is not valid.
32787 * 0b1..ZMK is valid.
32788 */
32789#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
32790#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
32791#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
32792/* ZMK_ECC_EN
32793 * 0b0..ZMK ECC check is disabled.
32794 * 0b1..ZMK ECC check is enabled.
32795 */
32796#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
32797#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
32798#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
32799#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
32800/* @} */
32801
32802/* @name LPSVCR - SNVS_LP Security Violation Control Register */
32803/* @{ */
32804#define SNVS_LPSVCR_SV0_EN_MASK (0x1U)
32805#define SNVS_LPSVCR_SV0_EN_SHIFT (0U)
32806/* SV0_EN
32807 * 0b0..Security Violation 0 is disabled in the LP domain.
32808 * 0b1..Security Violation 0 is enabled in the LP domain.
32809 */
32810#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK)
32811#define SNVS_LPSVCR_SV1_EN_MASK (0x2U)
32812#define SNVS_LPSVCR_SV1_EN_SHIFT (1U)
32813/* SV1_EN
32814 * 0b0..Security Violation 1 is disabled in the LP domain.
32815 * 0b1..Security Violation 1 is enabled in the LP domain.
32816 */
32817#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK)
32818#define SNVS_LPSVCR_SV2_EN_MASK (0x4U)
32819#define SNVS_LPSVCR_SV2_EN_SHIFT (2U)
32820/* SV2_EN
32821 * 0b0..Security Violation 2 is disabled in the LP domain.
32822 * 0b1..Security Violation 2 is enabled in the LP domain.
32823 */
32824#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK)
32825#define SNVS_LPSVCR_SV3_EN_MASK (0x8U)
32826#define SNVS_LPSVCR_SV3_EN_SHIFT (3U)
32827/* SV3_EN
32828 * 0b0..Security Violation 3 is disabled in the LP domain.
32829 * 0b1..Security Violation 3 is enabled in the LP domain.
32830 */
32831#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK)
32832#define SNVS_LPSVCR_SV4_EN_MASK (0x10U)
32833#define SNVS_LPSVCR_SV4_EN_SHIFT (4U)
32834/* SV4_EN
32835 * 0b0..Security Violation 4 is disabled in the LP domain.
32836 * 0b1..Security Violation 4 is enabled in the LP domain.
32837 */
32838#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK)
32839#define SNVS_LPSVCR_SV5_EN_MASK (0x20U)
32840#define SNVS_LPSVCR_SV5_EN_SHIFT (5U)
32841/* SV5_EN
32842 * 0b0..Security Violation 5 is disabled in the LP domain.
32843 * 0b1..Security Violation 5 is enabled in the LP domain.
32844 */
32845#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK)
32846/* @} */
32847
32848/* @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */
32849/* @{ */
32850#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
32851#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
32852/* SRTCR_EN
32853 * 0b0..SRTC rollover is disabled.
32854 * 0b1..SRTC rollover is enabled.
32855 */
32856#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
32857#define SNVS_LPTDCR_MCR_EN_MASK (0x4U)
32858#define SNVS_LPTDCR_MCR_EN_SHIFT (2U)
32859/* MCR_EN
32860 * 0b0..MC rollover is disabled.
32861 * 0b1..MC rollover is enabled.
32862 */
32863#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
32864#define SNVS_LPTDCR_ET1_EN_MASK (0x200U)
32865#define SNVS_LPTDCR_ET1_EN_SHIFT (9U)
32866/* ET1_EN
32867 * 0b0..External tamper 1 is disabled.
32868 * 0b1..External tamper 1 is enabled.
32869 */
32870#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
32871#define SNVS_LPTDCR_ET1P_MASK (0x800U)
32872#define SNVS_LPTDCR_ET1P_SHIFT (11U)
32873/* ET1P
32874 * 0b0..External tamper 1 is active low.
32875 * 0b1..External tamper 1 is active high.
32876 */
32877#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
32878#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
32879#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
32880#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
32881#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
32882#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
32883#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
32884#define SNVS_LPTDCR_OSCB_MASK (0x10000000U)
32885#define SNVS_LPTDCR_OSCB_SHIFT (28U)
32886/* OSCB
32887 * 0b0..Normal SRTC clock oscillator not bypassed.
32888 * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
32889 */
32890#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
32891/* @} */
32892
32893/* @name LPSR - SNVS_LP Status Register */
32894/* @{ */
32895#define SNVS_LPSR_LPTA_MASK (0x1U)
32896#define SNVS_LPSR_LPTA_SHIFT (0U)
32897/* LPTA
32898 * 0b0..No time alarm interrupt occurred.
32899 * 0b1..A time alarm interrupt occurred.
32900 */
32901#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
32902#define SNVS_LPSR_SRTCR_MASK (0x2U)
32903#define SNVS_LPSR_SRTCR_SHIFT (1U)
32904/* SRTCR
32905 * 0b0..SRTC has not reached its maximum value.
32906 * 0b1..SRTC has reached its maximum value.
32907 */
32908#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
32909#define SNVS_LPSR_MCR_MASK (0x4U)
32910#define SNVS_LPSR_MCR_SHIFT (2U)
32911/* MCR
32912 * 0b0..MC has not reached its maximum value.
32913 * 0b1..MC has reached its maximum value.
32914 */
32915#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
32916#define SNVS_LPSR_PGD_MASK (0x8U)
32917#define SNVS_LPSR_PGD_SHIFT (3U)
32918#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK)
32919#define SNVS_LPSR_ET1D_MASK (0x200U)
32920#define SNVS_LPSR_ET1D_SHIFT (9U)
32921/* ET1D
32922 * 0b0..External tampering 1 not detected.
32923 * 0b1..External tampering 1 detected.
32924 */
32925#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
32926#define SNVS_LPSR_ESVD_MASK (0x10000U)
32927#define SNVS_LPSR_ESVD_SHIFT (16U)
32928/* ESVD
32929 * 0b0..No external security violation.
32930 * 0b1..External security violation is detected.
32931 */
32932#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
32933#define SNVS_LPSR_EO_MASK (0x20000U)
32934#define SNVS_LPSR_EO_SHIFT (17U)
32935/* EO
32936 * 0b0..Emergency off was not detected.
32937 * 0b1..Emergency off was detected.
32938 */
32939#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
32940#define SNVS_LPSR_SPO_MASK (0x40000U)
32941#define SNVS_LPSR_SPO_SHIFT (18U)
32942/* SPO
32943 * 0b0..Set Power Off was not detected.
32944 * 0b1..Set Power Off was detected.
32945 */
32946#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK)
32947#define SNVS_LPSR_SED_MASK (0x100000U)
32948#define SNVS_LPSR_SED_SHIFT (20U)
32949/* SED
32950 * 0b0..Scan exit was not detected.
32951 * 0b1..Scan exit was detected.
32952 */
32953#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK)
32954#define SNVS_LPSR_LPNS_MASK (0x40000000U)
32955#define SNVS_LPSR_LPNS_SHIFT (30U)
32956/* LPNS
32957 * 0b0..LP section was not programmed in the non-secure state.
32958 * 0b1..LP section was programmed in the non-secure state.
32959 */
32960#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
32961#define SNVS_LPSR_LPS_MASK (0x80000000U)
32962#define SNVS_LPSR_LPS_SHIFT (31U)
32963/* LPS
32964 * 0b0..LP section was not programmed in secure or trusted state.
32965 * 0b1..LP section was programmed in secure or trusted state.
32966 */
32967#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
32968/* @} */
32969
32970/* @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
32971/* @{ */
32972#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
32973#define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
32974#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
32975/* @} */
32976
32977/* @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
32978/* @{ */
32979#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
32980#define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
32981#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
32982/* @} */
32983
32984/* @name LPTAR - SNVS_LP Time Alarm Register */
32985/* @{ */
32986#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
32987#define SNVS_LPTAR_LPTA_SHIFT (0U)
32988#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
32989/* @} */
32990
32991/* @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
32992/* @{ */
32993#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
32994#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
32995#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
32996#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
32997#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
32998#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
32999/* @} */
33000
33001/* @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
33002/* @{ */
33003#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
33004#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
33005#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
33006/* @} */
33007
33008/* @name LPPGDR - SNVS_LP Power Glitch Detector Register */
33009/* @{ */
33010#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
33011#define SNVS_LPPGDR_PGD_SHIFT (0U)
33012#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
33013/* @} */
33014
33015/* @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
33016/* @{ */
33017#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
33018#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
33019#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
33020/* @} */
33021
33022/* @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
33023/* @{ */
33024#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
33025#define SNVS_LPZMKR_ZMK_SHIFT (0U)
33026#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
33027/* @} */
33028
33029/* The count of SNVS_LPZMKR */
33030#define SNVS_LPZMKR_COUNT (8U)
33031
33032/* @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
33033/* @{ */
33034#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
33035#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
33036#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
33037/* @} */
33038
33039/* The count of SNVS_LPGPR_ALIAS */
33040#define SNVS_LPGPR_ALIAS_COUNT (4U)
33041
33042/* @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */
33043/* @{ */
33044#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
33045#define SNVS_LPGPR_GPR_SHIFT (0U)
33046#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
33047/* @} */
33048
33049/* The count of SNVS_LPGPR */
33050#define SNVS_LPGPR_COUNT (8U)
33051
33052/* @name HPVIDR1 - SNVS_HP Version ID Register 1 */
33053/* @{ */
33054#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
33055#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
33056#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
33057#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
33058#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
33059#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
33060#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
33061#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
33062#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
33063/* @} */
33064
33065/* @name HPVIDR2 - SNVS_HP Version ID Register 2 */
33066/* @{ */
33067#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
33068#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
33069#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
33070#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
33071#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
33072#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
33073#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
33074#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
33075#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
33076#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
33077#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
33078#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
33079/* @} */
33080
33081
33082/*
33083 * @}
33084 */ /* end of group SNVS_Register_Masks */
33085
33086
33087/* SNVS - Peripheral instance base addresses */
33088/* Peripheral SNVS base address */
33089#define SNVS_BASE (0x400D4000u)
33090/* Peripheral SNVS base pointer */
33091#define SNVS ((SNVS_Type *)SNVS_BASE)
33092/* Array initializer of SNVS peripheral base addresses */
33093#define SNVS_BASE_ADDRS { SNVS_BASE }
33094/* Array initializer of SNVS peripheral base pointers */
33095#define SNVS_BASE_PTRS { SNVS }
33096/* Interrupt vectors for the SNVS peripheral type */
33097#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn }
33098#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn }
33099#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn }
33100
33101/*
33102 * @}
33103 */ /* end of group SNVS_Peripheral_Access_Layer */
33104
33105
33106/* ----------------------------------------------------------------------------
33107 -- SPDIF Peripheral Access Layer
33108 ---------------------------------------------------------------------------- */
33109
33110/*
33111 * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
33112 * @{
33113 */
33114
33115/* SPDIF - Register Layout Typedef */
33116typedef struct {
33117 __IO uint32_t SCR;
33118 __IO uint32_t SRCD;
33119 __IO uint32_t SRPC;
33120 __IO uint32_t SIE;
33121 union { /* offset: 0x10 */
33122 __O uint32_t SIC;
33123 __I uint32_t SIS;
33124 };
33125 __I uint32_t SRL;
33126 __I uint32_t SRR;
33127 __I uint32_t SRCSH;
33128 __I uint32_t SRCSL;
33129 __I uint32_t SRU;
33130 __I uint32_t SRQ;
33131 __O uint32_t STL;
33132 __O uint32_t STR;
33133 __IO uint32_t STCSCH;
33134 __IO uint32_t STCSCL;
33135 uint8_t RESERVED_0[8];
33136 __I uint32_t SRFM;
33137 uint8_t RESERVED_1[8];
33138 __IO uint32_t STC;
33139} SPDIF_Type;
33140
33141/* ----------------------------------------------------------------------------
33142 -- SPDIF Register Masks
33143 ---------------------------------------------------------------------------- */
33144
33145/*
33146 * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
33147 * @{
33148 */
33149
33150/* @name SCR - SPDIF Configuration Register */
33151/* @{ */
33152#define SPDIF_SCR_USRC_SEL_MASK (0x3U)
33153#define SPDIF_SCR_USRC_SEL_SHIFT (0U)
33154/* USrc_Sel
33155 * 0b00..No embedded U channel
33156 * 0b01..U channel from SPDIF receive block (CD mode)
33157 * 0b10..Reserved
33158 * 0b11..U channel from on chip transmitter
33159 */
33160#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
33161#define SPDIF_SCR_TXSEL_MASK (0x1CU)
33162#define SPDIF_SCR_TXSEL_SHIFT (2U)
33163/* TxSel
33164 * 0b000..Off and output 0
33165 * 0b001..Feed-through SPDIFIN
33166 * 0b101..Tx Normal operation
33167 */
33168#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
33169#define SPDIF_SCR_VALCTRL_MASK (0x20U)
33170#define SPDIF_SCR_VALCTRL_SHIFT (5U)
33171/* ValCtrl
33172 * 0b0..Outgoing Validity always set
33173 * 0b1..Outgoing Validity always clear
33174 */
33175#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
33176#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
33177#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
33178#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
33179#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
33180#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
33181#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
33182#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
33183#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
33184/* TxFIFO_Ctrl
33185 * 0b00..Send out digital zero on SPDIF Tx
33186 * 0b01..Tx Normal operation
33187 * 0b10..Reset to 1 sample remaining
33188 * 0b11..Reserved
33189 */
33190#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
33191#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
33192#define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
33193#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
33194#define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
33195#define SPDIF_SCR_LOW_POWER_SHIFT (13U)
33196#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
33197#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
33198#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
33199/* TxFIFOEmpty_Sel
33200 * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
33201 * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
33202 * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
33203 * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
33204 */
33205#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
33206#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
33207#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
33208/* TxAutoSync
33209 * 0b0..Tx FIFO auto sync off
33210 * 0b1..Tx FIFO auto sync on
33211 */
33212#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
33213#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
33214#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
33215/* RxAutoSync
33216 * 0b0..Rx FIFO auto sync off
33217 * 0b1..RxFIFO auto sync on
33218 */
33219#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
33220#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
33221#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
33222/* RxFIFOFull_Sel
33223 * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
33224 * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
33225 * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
33226 * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
33227 */
33228#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
33229#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
33230#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
33231/* RxFIFO_Rst
33232 * 0b0..Normal operation
33233 * 0b1..Reset register to 1 sample remaining
33234 */
33235#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
33236#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
33237#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
33238/* RxFIFO_Off_On
33239 * 0b0..SPDIF Rx FIFO is on
33240 * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface
33241 */
33242#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
33243#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
33244#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
33245/* RxFIFO_Ctrl
33246 * 0b0..Normal operation
33247 * 0b1..Always read zero from Rx data register
33248 */
33249#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
33250/* @} */
33251
33252/* @name SRCD - CDText Control Register */
33253/* @{ */
33254#define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
33255#define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
33256/* USyncMode
33257 * 0b0..Non-CD data
33258 * 0b1..CD user channel subcode
33259 */
33260#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
33261/* @} */
33262
33263/* @name SRPC - PhaseConfig Register */
33264/* @{ */
33265#define SPDIF_SRPC_GAINSEL_MASK (0x38U)
33266#define SPDIF_SRPC_GAINSEL_SHIFT (3U)
33267/* GainSel
33268 * 0b000..24*(2**10)
33269 * 0b001..16*(2**10)
33270 * 0b010..12*(2**10)
33271 * 0b011..8*(2**10)
33272 * 0b100..6*(2**10)
33273 * 0b101..4*(2**10)
33274 * 0b110..3*(2**10)
33275 */
33276#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
33277#define SPDIF_SRPC_LOCK_MASK (0x40U)
33278#define SPDIF_SRPC_LOCK_SHIFT (6U)
33279#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
33280#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
33281#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
33282/* ClkSrc_Sel
33283 * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
33284 * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
33285 * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
33286 * 0b0101..REF_CLK_32K (XTALOSC)
33287 * 0b0110..tx_clk (SPDIF0_CLK_ROOT)
33288 * 0b1000..SPDIF_EXT_CLK
33289 */
33290#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
33291/* @} */
33292
33293/* @name SIE - InterruptEn Register */
33294/* @{ */
33295#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
33296#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
33297#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
33298#define SPDIF_SIE_TXEM_MASK (0x2U)
33299#define SPDIF_SIE_TXEM_SHIFT (1U)
33300#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
33301#define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
33302#define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
33303#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
33304#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
33305#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
33306#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
33307#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
33308#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
33309#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
33310#define SPDIF_SIE_UQERR_MASK (0x20U)
33311#define SPDIF_SIE_UQERR_SHIFT (5U)
33312#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
33313#define SPDIF_SIE_UQSYNC_MASK (0x40U)
33314#define SPDIF_SIE_UQSYNC_SHIFT (6U)
33315#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
33316#define SPDIF_SIE_QRXOV_MASK (0x80U)
33317#define SPDIF_SIE_QRXOV_SHIFT (7U)
33318#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
33319#define SPDIF_SIE_QRXFUL_MASK (0x100U)
33320#define SPDIF_SIE_QRXFUL_SHIFT (8U)
33321#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
33322#define SPDIF_SIE_URXOV_MASK (0x200U)
33323#define SPDIF_SIE_URXOV_SHIFT (9U)
33324#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
33325#define SPDIF_SIE_URXFUL_MASK (0x400U)
33326#define SPDIF_SIE_URXFUL_SHIFT (10U)
33327#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
33328#define SPDIF_SIE_BITERR_MASK (0x4000U)
33329#define SPDIF_SIE_BITERR_SHIFT (14U)
33330#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
33331#define SPDIF_SIE_SYMERR_MASK (0x8000U)
33332#define SPDIF_SIE_SYMERR_SHIFT (15U)
33333#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
33334#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
33335#define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
33336#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
33337#define SPDIF_SIE_CNEW_MASK (0x20000U)
33338#define SPDIF_SIE_CNEW_SHIFT (17U)
33339#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
33340#define SPDIF_SIE_TXRESYN_MASK (0x40000U)
33341#define SPDIF_SIE_TXRESYN_SHIFT (18U)
33342#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
33343#define SPDIF_SIE_TXUNOV_MASK (0x80000U)
33344#define SPDIF_SIE_TXUNOV_SHIFT (19U)
33345#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
33346#define SPDIF_SIE_LOCK_MASK (0x100000U)
33347#define SPDIF_SIE_LOCK_SHIFT (20U)
33348#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
33349/* @} */
33350
33351/* @name SIC - InterruptClear Register */
33352/* @{ */
33353#define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
33354#define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
33355#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
33356#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
33357#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
33358#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
33359#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
33360#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
33361#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
33362#define SPDIF_SIC_UQERR_MASK (0x20U)
33363#define SPDIF_SIC_UQERR_SHIFT (5U)
33364#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
33365#define SPDIF_SIC_UQSYNC_MASK (0x40U)
33366#define SPDIF_SIC_UQSYNC_SHIFT (6U)
33367#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
33368#define SPDIF_SIC_QRXOV_MASK (0x80U)
33369#define SPDIF_SIC_QRXOV_SHIFT (7U)
33370#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
33371#define SPDIF_SIC_URXOV_MASK (0x200U)
33372#define SPDIF_SIC_URXOV_SHIFT (9U)
33373#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
33374#define SPDIF_SIC_BITERR_MASK (0x4000U)
33375#define SPDIF_SIC_BITERR_SHIFT (14U)
33376#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
33377#define SPDIF_SIC_SYMERR_MASK (0x8000U)
33378#define SPDIF_SIC_SYMERR_SHIFT (15U)
33379#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
33380#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
33381#define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
33382#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
33383#define SPDIF_SIC_CNEW_MASK (0x20000U)
33384#define SPDIF_SIC_CNEW_SHIFT (17U)
33385#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
33386#define SPDIF_SIC_TXRESYN_MASK (0x40000U)
33387#define SPDIF_SIC_TXRESYN_SHIFT (18U)
33388#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
33389#define SPDIF_SIC_TXUNOV_MASK (0x80000U)
33390#define SPDIF_SIC_TXUNOV_SHIFT (19U)
33391#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
33392#define SPDIF_SIC_LOCK_MASK (0x100000U)
33393#define SPDIF_SIC_LOCK_SHIFT (20U)
33394#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
33395/* @} */
33396
33397/* @name SIS - InterruptStat Register */
33398/* @{ */
33399#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
33400#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
33401#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
33402#define SPDIF_SIS_TXEM_MASK (0x2U)
33403#define SPDIF_SIS_TXEM_SHIFT (1U)
33404#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
33405#define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
33406#define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
33407#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
33408#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
33409#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
33410#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
33411#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
33412#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
33413#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
33414#define SPDIF_SIS_UQERR_MASK (0x20U)
33415#define SPDIF_SIS_UQERR_SHIFT (5U)
33416#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
33417#define SPDIF_SIS_UQSYNC_MASK (0x40U)
33418#define SPDIF_SIS_UQSYNC_SHIFT (6U)
33419#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
33420#define SPDIF_SIS_QRXOV_MASK (0x80U)
33421#define SPDIF_SIS_QRXOV_SHIFT (7U)
33422#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
33423#define SPDIF_SIS_QRXFUL_MASK (0x100U)
33424#define SPDIF_SIS_QRXFUL_SHIFT (8U)
33425#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
33426#define SPDIF_SIS_URXOV_MASK (0x200U)
33427#define SPDIF_SIS_URXOV_SHIFT (9U)
33428#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
33429#define SPDIF_SIS_URXFUL_MASK (0x400U)
33430#define SPDIF_SIS_URXFUL_SHIFT (10U)
33431#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
33432#define SPDIF_SIS_BITERR_MASK (0x4000U)
33433#define SPDIF_SIS_BITERR_SHIFT (14U)
33434#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
33435#define SPDIF_SIS_SYMERR_MASK (0x8000U)
33436#define SPDIF_SIS_SYMERR_SHIFT (15U)
33437#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
33438#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
33439#define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
33440#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
33441#define SPDIF_SIS_CNEW_MASK (0x20000U)
33442#define SPDIF_SIS_CNEW_SHIFT (17U)
33443#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
33444#define SPDIF_SIS_TXRESYN_MASK (0x40000U)
33445#define SPDIF_SIS_TXRESYN_SHIFT (18U)
33446#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
33447#define SPDIF_SIS_TXUNOV_MASK (0x80000U)
33448#define SPDIF_SIS_TXUNOV_SHIFT (19U)
33449#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
33450#define SPDIF_SIS_LOCK_MASK (0x100000U)
33451#define SPDIF_SIS_LOCK_SHIFT (20U)
33452#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
33453/* @} */
33454
33455/* @name SRL - SPDIFRxLeft Register */
33456/* @{ */
33457#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
33458#define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
33459#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
33460/* @} */
33461
33462/* @name SRR - SPDIFRxRight Register */
33463/* @{ */
33464#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
33465#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
33466#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
33467/* @} */
33468
33469/* @name SRCSH - SPDIFRxCChannel_h Register */
33470/* @{ */
33471#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
33472#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
33473#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
33474/* @} */
33475
33476/* @name SRCSL - SPDIFRxCChannel_l Register */
33477/* @{ */
33478#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
33479#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
33480#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
33481/* @} */
33482
33483/* @name SRU - UchannelRx Register */
33484/* @{ */
33485#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
33486#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
33487#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
33488/* @} */
33489
33490/* @name SRQ - QchannelRx Register */
33491/* @{ */
33492#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
33493#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
33494#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
33495/* @} */
33496
33497/* @name STL - SPDIFTxLeft Register */
33498/* @{ */
33499#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
33500#define SPDIF_STL_TXDATALEFT_SHIFT (0U)
33501#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
33502/* @} */
33503
33504/* @name STR - SPDIFTxRight Register */
33505/* @{ */
33506#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
33507#define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
33508#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
33509/* @} */
33510
33511/* @name STCSCH - SPDIFTxCChannelCons_h Register */
33512/* @{ */
33513#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
33514#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
33515#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
33516/* @} */
33517
33518/* @name STCSCL - SPDIFTxCChannelCons_l Register */
33519/* @{ */
33520#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
33521#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
33522#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
33523/* @} */
33524
33525/* @name SRFM - FreqMeas Register */
33526/* @{ */
33527#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
33528#define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
33529#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
33530/* @} */
33531
33532/* @name STC - SPDIFTxClk Register */
33533/* @{ */
33534#define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
33535#define SPDIF_STC_TXCLK_DF_SHIFT (0U)
33536/* TxClk_DF
33537 * 0b0000000..divider factor is 1
33538 * 0b0000001..divider factor is 2
33539 * 0b1111111..divider factor is 128
33540 */
33541#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
33542#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
33543#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
33544/* tx_all_clk_en
33545 * 0b0..disable transfer clock.
33546 * 0b1..enable transfer clock.
33547 */
33548#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
33549#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
33550#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
33551/* TxClk_Source
33552 * 0b000..XTALOSC input (XTALOSC clock)
33553 * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.)
33554 * 0b010..tx_clk1 (from SAI1)
33555 * 0b011..tx_clk2 SPDIF_EXT_CLK, from pads
33556 * 0b100..tx_clk3 (from SAI2)
33557 * 0b101..ipg_clk input (frequency divided)
33558 * 0b110..tx_clk4 (from SAI3)
33559 */
33560#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
33561#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
33562#define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
33563/* SYSCLK_DF
33564 * 0b000000000..no clock signal
33565 * 0b000000001..divider factor is 2
33566 * 0b111111111..divider factor is 512
33567 */
33568#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
33569/* @} */
33570
33571
33572/*
33573 * @}
33574 */ /* end of group SPDIF_Register_Masks */
33575
33576
33577/* SPDIF - Peripheral instance base addresses */
33578/* Peripheral SPDIF base address */
33579#define SPDIF_BASE (0x40380000u)
33580/* Peripheral SPDIF base pointer */
33581#define SPDIF ((SPDIF_Type *)SPDIF_BASE)
33582/* Array initializer of SPDIF peripheral base addresses */
33583#define SPDIF_BASE_ADDRS { SPDIF_BASE }
33584/* Array initializer of SPDIF peripheral base pointers */
33585#define SPDIF_BASE_PTRS { SPDIF }
33586/* Interrupt vectors for the SPDIF peripheral type */
33587#define SPDIF_IRQS { SPDIF_IRQn }
33588
33589/*
33590 * @}
33591 */ /* end of group SPDIF_Peripheral_Access_Layer */
33592
33593
33594/* ----------------------------------------------------------------------------
33595 -- SRC Peripheral Access Layer
33596 ---------------------------------------------------------------------------- */
33597
33598/*
33599 * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
33600 * @{
33601 */
33602
33603/* SRC - Register Layout Typedef */
33604typedef struct {
33605 __IO uint32_t SCR;
33606 __I uint32_t SBMR1;
33607 __IO uint32_t SRSR;
33608 uint8_t RESERVED_0[16];
33609 __I uint32_t SBMR2;
33610 __IO uint32_t GPR[10];
33611} SRC_Type;
33612
33613/* ----------------------------------------------------------------------------
33614 -- SRC Register Masks
33615 ---------------------------------------------------------------------------- */
33616
33617/*
33618 * @addtogroup SRC_Register_Masks SRC Register Masks
33619 * @{
33620 */
33621
33622/* @name SCR - SRC Control Register */
33623/* @{ */
33624#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U)
33625#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U)
33626/* mask_wdog_rst
33627 * 0b0101..wdog_rst_b is masked
33628 * 0b1010..wdog_rst_b is not masked (default)
33629 */
33630#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK)
33631#define SRC_SCR_CORE0_RST_MASK (0x2000U)
33632#define SRC_SCR_CORE0_RST_SHIFT (13U)
33633/* core0_rst
33634 * 0b0..do not assert core0 reset
33635 * 0b1..assert core0 reset
33636 */
33637#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK)
33638#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U)
33639#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U)
33640/* core0_dbg_rst
33641 * 0b0..do not assert core0 debug reset
33642 * 0b1..assert core0 debug reset
33643 */
33644#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK)
33645#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U)
33646#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U)
33647/* dbg_rst_msk_pg
33648 * 0b0..do not mask core debug resets (debug resets will be asserted after power gating event)
33649 * 0b1..mask core debug resets (debug resets won't be asserted after power gating event)
33650 */
33651#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK)
33652#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U)
33653#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U)
33654/* mask_wdog3_rst
33655 * 0b0101..wdog3_rst_b is masked
33656 * 0b1010..wdog3_rst_b is not masked
33657 */
33658#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK)
33659/* @} */
33660
33661/* @name SBMR1 - SRC Boot Mode Register 1 */
33662/* @{ */
33663#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
33664#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
33665#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
33666#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
33667#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
33668#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
33669#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
33670#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
33671#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
33672#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
33673#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
33674#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
33675/* @} */
33676
33677/* @name SRSR - SRC Reset Status Register */
33678/* @{ */
33679#define SRC_SRSR_IPP_RESET_B_MASK (0x1U)
33680#define SRC_SRSR_IPP_RESET_B_SHIFT (0U)
33681/* ipp_reset_b
33682 * 0b0..Reset is not a result of ipp_reset_b pin.
33683 * 0b1..Reset is a result of ipp_reset_b pin.
33684 */
33685#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK)
33686#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U)
33687#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U)
33688/* lockup_sysresetreq
33689 * 0b0..Reset is not a result of the mentioned case.
33690 * 0b1..Reset is a result of the mentioned case.
33691 */
33692#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK)
33693#define SRC_SRSR_CSU_RESET_B_MASK (0x4U)
33694#define SRC_SRSR_CSU_RESET_B_SHIFT (2U)
33695/* csu_reset_b
33696 * 0b0..Reset is not a result of the csu_reset_b event.
33697 * 0b1..Reset is a result of the csu_reset_b event.
33698 */
33699#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK)
33700#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U)
33701#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U)
33702/* ipp_user_reset_b
33703 * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
33704 * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
33705 */
33706#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK)
33707#define SRC_SRSR_WDOG_RST_B_MASK (0x10U)
33708#define SRC_SRSR_WDOG_RST_B_SHIFT (4U)
33709/* wdog_rst_b
33710 * 0b0..Reset is not a result of the watchdog time-out event.
33711 * 0b1..Reset is a result of the watchdog time-out event.
33712 */
33713#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK)
33714#define SRC_SRSR_JTAG_RST_B_MASK (0x20U)
33715#define SRC_SRSR_JTAG_RST_B_SHIFT (5U)
33716/* jtag_rst_b
33717 * 0b0..Reset is not a result of HIGH-Z reset from JTAG.
33718 * 0b1..Reset is a result of HIGH-Z reset from JTAG.
33719 */
33720#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK)
33721#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U)
33722#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U)
33723/* jtag_sw_rst
33724 * 0b0..Reset is not a result of software reset from JTAG.
33725 * 0b1..Reset is a result of software reset from JTAG.
33726 */
33727#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK)
33728#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U)
33729#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U)
33730/* wdog3_rst_b
33731 * 0b0..Reset is not a result of the watchdog3 time-out event.
33732 * 0b1..Reset is a result of the watchdog3 time-out event.
33733 */
33734#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK)
33735#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U)
33736#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U)
33737/* tempsense_rst_b
33738 * 0b0..Reset is not a result of software reset from Temperature Sensor.
33739 * 0b1..Reset is a result of software reset from Temperature Sensor.
33740 */
33741#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK)
33742/* @} */
33743
33744/* @name SBMR2 - SRC Boot Mode Register 2 */
33745/* @{ */
33746#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
33747#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
33748#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
33749#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
33750#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
33751#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
33752#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
33753#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
33754#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
33755#define SRC_SBMR2_BMOD_MASK (0x3000000U)
33756#define SRC_SBMR2_BMOD_SHIFT (24U)
33757#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
33758/* @} */
33759
33760/* @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */
33761/* @{ */
33762#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU)
33763#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U)
33764#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK)
33765#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU)
33766#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U)
33767#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK)
33768/* @} */
33769
33770/* The count of SRC_GPR */
33771#define SRC_GPR_COUNT (10U)
33772
33773
33774/*
33775 * @}
33776 */ /* end of group SRC_Register_Masks */
33777
33778
33779/* SRC - Peripheral instance base addresses */
33780/* Peripheral SRC base address */
33781#define SRC_BASE (0x400F8000u)
33782/* Peripheral SRC base pointer */
33783#define SRC ((SRC_Type *)SRC_BASE)
33784/* Array initializer of SRC peripheral base addresses */
33785#define SRC_BASE_ADDRS { SRC_BASE }
33786/* Array initializer of SRC peripheral base pointers */
33787#define SRC_BASE_PTRS { SRC }
33788/* Interrupt vectors for the SRC peripheral type */
33789#define SRC_IRQS { SRC_IRQn }
33790/* Backward compatibility */
33791#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK
33792#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT
33793#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x)
33794#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK
33795#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT
33796#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x)
33797#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK
33798#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT
33799#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x)
33800#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK
33801#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT
33802#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x)
33803#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK
33804#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT
33805#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x)
33806/* Extra definition */
33807#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \
33808 | SRC_SRSR_JTAG_SW_RST_MASK \
33809 | SRC_SRSR_JTAG_RST_B_MASK \
33810 | SRC_SRSR_WDOG_RST_B_MASK \
33811 | SRC_SRSR_IPP_USER_RESET_B_MASK \
33812 | SRC_SRSR_CSU_RESET_B_MASK \
33813 | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \
33814 | SRC_SRSR_IPP_RESET_B_MASK)
33815
33816
33817/*
33818 * @}
33819 */ /* end of group SRC_Peripheral_Access_Layer */
33820
33821
33822/* ----------------------------------------------------------------------------
33823 -- TEMPMON Peripheral Access Layer
33824 ---------------------------------------------------------------------------- */
33825
33826/*
33827 * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer
33828 * @{
33829 */
33830
33831/* TEMPMON - Register Layout Typedef */
33832typedef struct {
33833 uint8_t RESERVED_0[384];
33834 __IO uint32_t TEMPSENSE0;
33835 __IO uint32_t TEMPSENSE0_SET;
33836 __IO uint32_t TEMPSENSE0_CLR;
33837 __IO uint32_t TEMPSENSE0_TOG;
33838 __IO uint32_t TEMPSENSE1;
33839 __IO uint32_t TEMPSENSE1_SET;
33840 __IO uint32_t TEMPSENSE1_CLR;
33841 __IO uint32_t TEMPSENSE1_TOG;
33842 uint8_t RESERVED_1[240];
33843 __IO uint32_t TEMPSENSE2;
33844 __IO uint32_t TEMPSENSE2_SET;
33845 __IO uint32_t TEMPSENSE2_CLR;
33846 __IO uint32_t TEMPSENSE2_TOG;
33847} TEMPMON_Type;
33848
33849/* ----------------------------------------------------------------------------
33850 -- TEMPMON Register Masks
33851 ---------------------------------------------------------------------------- */
33852
33853/*
33854 * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks
33855 * @{
33856 */
33857
33858/* @name TEMPSENSE0 - Tempsensor Control Register 0 */
33859/* @{ */
33860#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U)
33861#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U)
33862/* POWER_DOWN
33863 * 0b0..Enable power to the temperature sensor.
33864 * 0b1..Power down the temperature sensor.
33865 */
33866#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK)
33867#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U)
33868#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U)
33869/* MEASURE_TEMP
33870 * 0b0..Do not start the measurement process.
33871 * 0b1..Start the measurement process.
33872 */
33873#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK)
33874#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U)
33875#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U)
33876/* FINISHED
33877 * 0b0..Last measurement is not ready yet.
33878 * 0b1..Last measurement is valid.
33879 */
33880#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK)
33881#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U)
33882#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U)
33883#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK)
33884#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U)
33885#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U)
33886#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK)
33887/* @} */
33888
33889/* @name TEMPSENSE0_SET - Tempsensor Control Register 0 */
33890/* @{ */
33891#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U)
33892#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U)
33893/* POWER_DOWN
33894 * 0b0..Enable power to the temperature sensor.
33895 * 0b1..Power down the temperature sensor.
33896 */
33897#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK)
33898#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U)
33899#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U)
33900/* MEASURE_TEMP
33901 * 0b0..Do not start the measurement process.
33902 * 0b1..Start the measurement process.
33903 */
33904#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK)
33905#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U)
33906#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U)
33907/* FINISHED
33908 * 0b0..Last measurement is not ready yet.
33909 * 0b1..Last measurement is valid.
33910 */
33911#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
33912#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U)
33913#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U)
33914#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK)
33915#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U)
33916#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U)
33917#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK)
33918/* @} */
33919
33920/* @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */
33921/* @{ */
33922#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U)
33923#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U)
33924/* POWER_DOWN
33925 * 0b0..Enable power to the temperature sensor.
33926 * 0b1..Power down the temperature sensor.
33927 */
33928#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK)
33929#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U)
33930#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U)
33931/* MEASURE_TEMP
33932 * 0b0..Do not start the measurement process.
33933 * 0b1..Start the measurement process.
33934 */
33935#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK)
33936#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U)
33937#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U)
33938/* FINISHED
33939 * 0b0..Last measurement is not ready yet.
33940 * 0b1..Last measurement is valid.
33941 */
33942#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
33943#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U)
33944#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U)
33945#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK)
33946#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U)
33947#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U)
33948#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK)
33949/* @} */
33950
33951/* @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */
33952/* @{ */
33953#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U)
33954#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U)
33955/* POWER_DOWN
33956 * 0b0..Enable power to the temperature sensor.
33957 * 0b1..Power down the temperature sensor.
33958 */
33959#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK)
33960#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U)
33961#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U)
33962/* MEASURE_TEMP
33963 * 0b0..Do not start the measurement process.
33964 * 0b1..Start the measurement process.
33965 */
33966#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK)
33967#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U)
33968#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U)
33969/* FINISHED
33970 * 0b0..Last measurement is not ready yet.
33971 * 0b1..Last measurement is valid.
33972 */
33973#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK)
33974#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U)
33975#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U)
33976#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK)
33977#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U)
33978#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U)
33979#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK)
33980/* @} */
33981
33982/* @name TEMPSENSE1 - Tempsensor Control Register 1 */
33983/* @{ */
33984#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU)
33985#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U)
33986#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK)
33987/* @} */
33988
33989/* @name TEMPSENSE1_SET - Tempsensor Control Register 1 */
33990/* @{ */
33991#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU)
33992#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U)
33993#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
33994/* @} */
33995
33996/* @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */
33997/* @{ */
33998#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU)
33999#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U)
34000#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
34001/* @} */
34002
34003/* @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */
34004/* @{ */
34005#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU)
34006#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U)
34007#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
34008/* @} */
34009
34010/* @name TEMPSENSE2 - Tempsensor Control Register 2 */
34011/* @{ */
34012#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU)
34013#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U)
34014#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK)
34015#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
34016#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U)
34017#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK)
34018/* @} */
34019
34020/* @name TEMPSENSE2_SET - Tempsensor Control Register 2 */
34021/* @{ */
34022#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU)
34023#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U)
34024#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK)
34025#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
34026#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U)
34027#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK)
34028/* @} */
34029
34030/* @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */
34031/* @{ */
34032#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU)
34033#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U)
34034#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK)
34035#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
34036#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U)
34037#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK)
34038/* @} */
34039
34040/* @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */
34041/* @{ */
34042#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU)
34043#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U)
34044#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK)
34045#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U)
34046#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U)
34047#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK)
34048/* @} */
34049
34050
34051/*
34052 * @}
34053 */ /* end of group TEMPMON_Register_Masks */
34054
34055
34056/* TEMPMON - Peripheral instance base addresses */
34057/* Peripheral TEMPMON base address */
34058#define TEMPMON_BASE (0x400D8000u)
34059/* Peripheral TEMPMON base pointer */
34060#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE)
34061/* Array initializer of TEMPMON peripheral base addresses */
34062#define TEMPMON_BASE_ADDRS { TEMPMON_BASE }
34063/* Array initializer of TEMPMON peripheral base pointers */
34064#define TEMPMON_BASE_PTRS { TEMPMON }
34065
34066/*
34067 * @}
34068 */ /* end of group TEMPMON_Peripheral_Access_Layer */
34069
34070
34071/* ----------------------------------------------------------------------------
34072 -- TMR Peripheral Access Layer
34073 ---------------------------------------------------------------------------- */
34074
34075/*
34076 * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
34077 * @{
34078 */
34079
34080typedef struct { /* offset: 0x0, array step: 0x20 */
34081 __IO uint16_t COMP1;
34082 __IO uint16_t COMP2;
34083 __IO uint16_t CAPT;
34084 __IO uint16_t LOAD;
34085 __IO uint16_t HOLD;
34086 __IO uint16_t CNTR;
34087 __IO uint16_t CTRL;
34088 __IO uint16_t SCTRL;
34089 __IO uint16_t CMPLD1;
34090 __IO uint16_t CMPLD2;
34091 __IO uint16_t CSCTRL;
34092 __IO uint16_t FILT;
34093 __IO uint16_t DMA;
34094 uint8_t RESERVED_0[4];
34095 __IO uint16_t ENBL;
34096} TMR_Channel_Type;
34097
34098/* TMR - Register Layout Typedef */
34099typedef struct {
34100 TMR_Channel_Type CHANNEL[4];
34101 uint32_t __padd[0xfe0];
34102} TMR_Type;
34103
34104/* ----------------------------------------------------------------------------
34105 -- TMR Register Masks
34106 ---------------------------------------------------------------------------- */
34107
34108/*
34109 * @addtogroup TMR_Register_Masks TMR Register Masks
34110 * @{
34111 */
34112
34113/* @name COMP1 - Timer Channel Compare Register 1 */
34114/* @{ */
34115#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
34116#define TMR_COMP1_COMPARISON_1_SHIFT (0U)
34117#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
34118/* @} */
34119
34120/* The count of TMR_COMP1 */
34121#define TMR_COMP1_COUNT (4U)
34122
34123/* @name COMP2 - Timer Channel Compare Register 2 */
34124/* @{ */
34125#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
34126#define TMR_COMP2_COMPARISON_2_SHIFT (0U)
34127#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
34128/* @} */
34129
34130/* The count of TMR_COMP2 */
34131#define TMR_COMP2_COUNT (4U)
34132
34133/* @name CAPT - Timer Channel Capture Register */
34134/* @{ */
34135#define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
34136#define TMR_CAPT_CAPTURE_SHIFT (0U)
34137#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
34138/* @} */
34139
34140/* The count of TMR_CAPT */
34141#define TMR_CAPT_COUNT (4U)
34142
34143/* @name LOAD - Timer Channel Load Register */
34144/* @{ */
34145#define TMR_LOAD_LOAD_MASK (0xFFFFU)
34146#define TMR_LOAD_LOAD_SHIFT (0U)
34147#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
34148/* @} */
34149
34150/* The count of TMR_LOAD */
34151#define TMR_LOAD_COUNT (4U)
34152
34153/* @name HOLD - Timer Channel Hold Register */
34154/* @{ */
34155#define TMR_HOLD_HOLD_MASK (0xFFFFU)
34156#define TMR_HOLD_HOLD_SHIFT (0U)
34157#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
34158/* @} */
34159
34160/* The count of TMR_HOLD */
34161#define TMR_HOLD_COUNT (4U)
34162
34163/* @name CNTR - Timer Channel Counter Register */
34164/* @{ */
34165#define TMR_CNTR_COUNTER_MASK (0xFFFFU)
34166#define TMR_CNTR_COUNTER_SHIFT (0U)
34167#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
34168/* @} */
34169
34170/* The count of TMR_CNTR */
34171#define TMR_CNTR_COUNT (4U)
34172
34173/* @name CTRL - Timer Channel Control Register */
34174/* @{ */
34175#define TMR_CTRL_OUTMODE_MASK (0x7U)
34176#define TMR_CTRL_OUTMODE_SHIFT (0U)
34177/* OUTMODE - Output Mode
34178 * 0b000..Asserted while counter is active
34179 * 0b001..Clear OFLAG output on successful compare
34180 * 0b010..Set OFLAG output on successful compare
34181 * 0b011..Toggle OFLAG output on successful compare
34182 * 0b100..Toggle OFLAG output using alternating compare registers
34183 * 0b101..Set on compare, cleared on secondary source input edge
34184 * 0b110..Set on compare, cleared on counter rollover
34185 * 0b111..Enable gated clock output while counter is active
34186 */
34187#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
34188#define TMR_CTRL_COINIT_MASK (0x8U)
34189#define TMR_CTRL_COINIT_SHIFT (3U)
34190/* COINIT - Co-Channel Initialization
34191 * 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
34192 * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
34193 */
34194#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
34195#define TMR_CTRL_DIR_MASK (0x10U)
34196#define TMR_CTRL_DIR_SHIFT (4U)
34197/* DIR - Count Direction
34198 * 0b0..Count up.
34199 * 0b1..Count down.
34200 */
34201#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
34202#define TMR_CTRL_LENGTH_MASK (0x20U)
34203#define TMR_CTRL_LENGTH_SHIFT (5U)
34204/* LENGTH - Count Length
34205 * 0b0..Count until roll over at $FFFF and continue from $0000.
34206 * 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter
34207 * reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value.
34208 * When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful
34209 * comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2
34210 * value is reached, re-initializes, counts until COMP1 value is reached, and so on.
34211 */
34212#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
34213#define TMR_CTRL_ONCE_MASK (0x40U)
34214#define TMR_CTRL_ONCE_SHIFT (6U)
34215/* ONCE - Count Once
34216 * 0b0..Count repeatedly.
34217 * 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a
34218 * COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When
34219 * output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to
34220 * the COMP2 value, and then stops.
34221 */
34222#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
34223#define TMR_CTRL_SCS_MASK (0x180U)
34224#define TMR_CTRL_SCS_SHIFT (7U)
34225/* SCS - Secondary Count Source
34226 * 0b00..Counter 0 input pin
34227 * 0b01..Counter 1 input pin
34228 * 0b10..Counter 2 input pin
34229 * 0b11..Counter 3 input pin
34230 */
34231#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
34232#define TMR_CTRL_PCS_MASK (0x1E00U)
34233#define TMR_CTRL_PCS_SHIFT (9U)
34234/* PCS - Primary Count Source
34235 * 0b0000..Counter 0 input pin
34236 * 0b0001..Counter 1 input pin
34237 * 0b0010..Counter 2 input pin
34238 * 0b0011..Counter 3 input pin
34239 * 0b0100..Counter 0 output
34240 * 0b0101..Counter 1 output
34241 * 0b0110..Counter 2 output
34242 * 0b0111..Counter 3 output
34243 * 0b1000..IP bus clock divide by 1 prescaler
34244 * 0b1001..IP bus clock divide by 2 prescaler
34245 * 0b1010..IP bus clock divide by 4 prescaler
34246 * 0b1011..IP bus clock divide by 8 prescaler
34247 * 0b1100..IP bus clock divide by 16 prescaler
34248 * 0b1101..IP bus clock divide by 32 prescaler
34249 * 0b1110..IP bus clock divide by 64 prescaler
34250 * 0b1111..IP bus clock divide by 128 prescaler
34251 */
34252#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
34253#define TMR_CTRL_CM_MASK (0xE000U)
34254#define TMR_CTRL_CM_SHIFT (13U)
34255/* CM - Count Mode
34256 * 0b000..No operation
34257 * 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges
34258 * are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising
34259 * edges are counted regardless of the value of SCTRL[IPS].
34260 * 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
34261 * 0b011..Count rising edges of primary source while secondary input high active
34262 * 0b100..Quadrature count mode, uses primary and secondary sources
34263 * 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only
34264 * when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
34265 * 0b110..Edge of secondary source triggers primary count until compare
34266 * 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
34267 */
34268#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
34269/* @} */
34270
34271/* The count of TMR_CTRL */
34272#define TMR_CTRL_COUNT (4U)
34273
34274/* @name SCTRL - Timer Channel Status and Control Register */
34275/* @{ */
34276#define TMR_SCTRL_OEN_MASK (0x1U)
34277#define TMR_SCTRL_OEN_SHIFT (0U)
34278/* OEN - Output Enable
34279 * 0b0..The external pin is configured as an input.
34280 * 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as
34281 * their input see the driven value. The polarity of the signal is determined by OPS.
34282 */
34283#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
34284#define TMR_SCTRL_OPS_MASK (0x2U)
34285#define TMR_SCTRL_OPS_SHIFT (1U)
34286/* OPS - Output Polarity Select
34287 * 0b0..True polarity.
34288 * 0b1..Inverted polarity.
34289 */
34290#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
34291#define TMR_SCTRL_FORCE_MASK (0x4U)
34292#define TMR_SCTRL_FORCE_SHIFT (2U)
34293#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
34294#define TMR_SCTRL_VAL_MASK (0x8U)
34295#define TMR_SCTRL_VAL_SHIFT (3U)
34296#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
34297#define TMR_SCTRL_EEOF_MASK (0x10U)
34298#define TMR_SCTRL_EEOF_SHIFT (4U)
34299#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
34300#define TMR_SCTRL_MSTR_MASK (0x20U)
34301#define TMR_SCTRL_MSTR_SHIFT (5U)
34302#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
34303#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
34304#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
34305/* CAPTURE_MODE - Input Capture Mode
34306 * 0b00..Capture function is disabled
34307 * 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
34308 * 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
34309 * 0b11..Load capture register on both edges of input
34310 */
34311#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
34312#define TMR_SCTRL_INPUT_MASK (0x100U)
34313#define TMR_SCTRL_INPUT_SHIFT (8U)
34314#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
34315#define TMR_SCTRL_IPS_MASK (0x200U)
34316#define TMR_SCTRL_IPS_SHIFT (9U)
34317#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
34318#define TMR_SCTRL_IEFIE_MASK (0x400U)
34319#define TMR_SCTRL_IEFIE_SHIFT (10U)
34320#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
34321#define TMR_SCTRL_IEF_MASK (0x800U)
34322#define TMR_SCTRL_IEF_SHIFT (11U)
34323#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
34324#define TMR_SCTRL_TOFIE_MASK (0x1000U)
34325#define TMR_SCTRL_TOFIE_SHIFT (12U)
34326#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
34327#define TMR_SCTRL_TOF_MASK (0x2000U)
34328#define TMR_SCTRL_TOF_SHIFT (13U)
34329#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
34330#define TMR_SCTRL_TCFIE_MASK (0x4000U)
34331#define TMR_SCTRL_TCFIE_SHIFT (14U)
34332#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
34333#define TMR_SCTRL_TCF_MASK (0x8000U)
34334#define TMR_SCTRL_TCF_SHIFT (15U)
34335#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
34336/* @} */
34337
34338/* The count of TMR_SCTRL */
34339#define TMR_SCTRL_COUNT (4U)
34340
34341/* @name CMPLD1 - Timer Channel Comparator Load Register 1 */
34342/* @{ */
34343#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
34344#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
34345#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
34346/* @} */
34347
34348/* The count of TMR_CMPLD1 */
34349#define TMR_CMPLD1_COUNT (4U)
34350
34351/* @name CMPLD2 - Timer Channel Comparator Load Register 2 */
34352/* @{ */
34353#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
34354#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
34355#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
34356/* @} */
34357
34358/* The count of TMR_CMPLD2 */
34359#define TMR_CMPLD2_COUNT (4U)
34360
34361/* @name CSCTRL - Timer Channel Comparator Status and Control Register */
34362/* @{ */
34363#define TMR_CSCTRL_CL1_MASK (0x3U)
34364#define TMR_CSCTRL_CL1_SHIFT (0U)
34365/* CL1 - Compare Load Control 1
34366 * 0b00..Never preload
34367 * 0b01..Load upon successful compare with the value in COMP1
34368 * 0b10..Load upon successful compare with the value in COMP2
34369 * 0b11..Reserved
34370 */
34371#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
34372#define TMR_CSCTRL_CL2_MASK (0xCU)
34373#define TMR_CSCTRL_CL2_SHIFT (2U)
34374/* CL2 - Compare Load Control 2
34375 * 0b00..Never preload
34376 * 0b01..Load upon successful compare with the value in COMP1
34377 * 0b10..Load upon successful compare with the value in COMP2
34378 * 0b11..Reserved
34379 */
34380#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
34381#define TMR_CSCTRL_TCF1_MASK (0x10U)
34382#define TMR_CSCTRL_TCF1_SHIFT (4U)
34383#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
34384#define TMR_CSCTRL_TCF2_MASK (0x20U)
34385#define TMR_CSCTRL_TCF2_SHIFT (5U)
34386#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
34387#define TMR_CSCTRL_TCF1EN_MASK (0x40U)
34388#define TMR_CSCTRL_TCF1EN_SHIFT (6U)
34389#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
34390#define TMR_CSCTRL_TCF2EN_MASK (0x80U)
34391#define TMR_CSCTRL_TCF2EN_SHIFT (7U)
34392#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
34393#define TMR_CSCTRL_UP_MASK (0x200U)
34394#define TMR_CSCTRL_UP_SHIFT (9U)
34395/* UP - Counting Direction Indicator
34396 * 0b0..The last count was in the DOWN direction.
34397 * 0b1..The last count was in the UP direction.
34398 */
34399#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
34400#define TMR_CSCTRL_TCI_MASK (0x400U)
34401#define TMR_CSCTRL_TCI_SHIFT (10U)
34402/* TCI - Triggered Count Initialization Control
34403 * 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event.
34404 * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
34405 */
34406#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
34407#define TMR_CSCTRL_ROC_MASK (0x800U)
34408#define TMR_CSCTRL_ROC_SHIFT (11U)
34409/* ROC - Reload on Capture
34410 * 0b0..Do not reload the counter on a capture event.
34411 * 0b1..Reload the counter on a capture event.
34412 */
34413#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
34414#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
34415#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
34416/* ALT_LOAD - Alternative Load Enable
34417 * 0b0..Counter can be re-initialized only with the LOAD register.
34418 * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
34419 */
34420#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
34421#define TMR_CSCTRL_FAULT_MASK (0x2000U)
34422#define TMR_CSCTRL_FAULT_SHIFT (13U)
34423/* FAULT - Fault Enable
34424 * 0b0..Fault function disabled.
34425 * 0b1..Fault function enabled.
34426 */
34427#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
34428#define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
34429#define TMR_CSCTRL_DBG_EN_SHIFT (14U)
34430/* DBG_EN - Debug Actions Enable
34431 * 0b00..Continue with normal operation during debug mode. (default)
34432 * 0b01..Halt TMR counter during debug mode.
34433 * 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
34434 * 0b11..Both halt counter and force output to 0 during debug mode.
34435 */
34436#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
34437/* @} */
34438
34439/* The count of TMR_CSCTRL */
34440#define TMR_CSCTRL_COUNT (4U)
34441
34442/* @name FILT - Timer Channel Input Filter Register */
34443/* @{ */
34444#define TMR_FILT_FILT_PER_MASK (0xFFU)
34445#define TMR_FILT_FILT_PER_SHIFT (0U)
34446#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
34447#define TMR_FILT_FILT_CNT_MASK (0x700U)
34448#define TMR_FILT_FILT_CNT_SHIFT (8U)
34449#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
34450/* @} */
34451
34452/* The count of TMR_FILT */
34453#define TMR_FILT_COUNT (4U)
34454
34455/* @name DMA - Timer Channel DMA Enable Register */
34456/* @{ */
34457#define TMR_DMA_IEFDE_MASK (0x1U)
34458#define TMR_DMA_IEFDE_SHIFT (0U)
34459#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
34460#define TMR_DMA_CMPLD1DE_MASK (0x2U)
34461#define TMR_DMA_CMPLD1DE_SHIFT (1U)
34462#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
34463#define TMR_DMA_CMPLD2DE_MASK (0x4U)
34464#define TMR_DMA_CMPLD2DE_SHIFT (2U)
34465#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
34466/* @} */
34467
34468/* The count of TMR_DMA */
34469#define TMR_DMA_COUNT (4U)
34470
34471/* @name ENBL - Timer Channel Enable Register */
34472/* @{ */
34473#define TMR_ENBL_ENBL_MASK (0xFU)
34474#define TMR_ENBL_ENBL_SHIFT (0U)
34475/* ENBL - Timer Channel Enable
34476 * 0b0000..Timer channel is disabled.
34477 * 0b0001..Timer channel is enabled. (default)
34478 */
34479#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
34480/* @} */
34481
34482/* The count of TMR_ENBL */
34483#define TMR_ENBL_COUNT (4U)
34484
34485
34486/*
34487 * @}
34488 */ /* end of group TMR_Register_Masks */
34489
34490
34491/* TMR - Peripheral instance base addresses */
34492/* Peripheral TMR1 base address */
34493#define TMR1_BASE (0x401DC000u)
34494/* Peripheral TMR1 base pointer */
34495#define TMR1 ((TMR_Type *)TMR1_BASE)
34496/* Peripheral TMR2 base address */
34497#define TMR2_BASE (0x401E0000u)
34498/* Peripheral TMR2 base pointer */
34499#define TMR2 ((TMR_Type *)TMR2_BASE)
34500/* Peripheral TMR3 base address */
34501#define TMR3_BASE (0x401E4000u)
34502/* Peripheral TMR3 base pointer */
34503#define TMR3 ((TMR_Type *)TMR3_BASE)
34504/* Peripheral TMR4 base address */
34505#define TMR4_BASE (0x401E8000u)
34506/* Peripheral TMR4 base pointer */
34507#define TMR4 ((TMR_Type *)TMR4_BASE)
34508/* Array initializer of TMR peripheral base addresses */
34509#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
34510/* Array initializer of TMR peripheral base pointers */
34511#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
34512/* Interrupt vectors for the TMR peripheral type */
34513#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
34514
34515/*
34516 * @}
34517 */ /* end of group TMR_Peripheral_Access_Layer */
34518
34519
34520/* ----------------------------------------------------------------------------
34521 -- TRNG Peripheral Access Layer
34522 ---------------------------------------------------------------------------- */
34523
34524/*
34525 * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
34526 * @{
34527 */
34528
34529/* TRNG - Register Layout Typedef */
34530typedef struct {
34531 __IO uint32_t MCTL;
34532 __IO uint32_t SCMISC;
34533 __IO uint32_t PKRRNG;
34534 union { /* offset: 0xC */
34535 __IO uint32_t PKRMAX;
34536 __I uint32_t PKRSQ;
34537 };
34538 __IO uint32_t SDCTL;
34539 union { /* offset: 0x14 */
34540 __IO uint32_t SBLIM;
34541 __I uint32_t TOTSAM;
34542 };
34543 __IO uint32_t FRQMIN;
34544 union { /* offset: 0x1C */
34545 __I uint32_t FRQCNT;
34546 __IO uint32_t FRQMAX;
34547 };
34548 union { /* offset: 0x20 */
34549 __I uint32_t SCMC;
34550 __IO uint32_t SCML;
34551 };
34552 union { /* offset: 0x24 */
34553 __I uint32_t SCR1C;
34554 __IO uint32_t SCR1L;
34555 };
34556 union { /* offset: 0x28 */
34557 __I uint32_t SCR2C;
34558 __IO uint32_t SCR2L;
34559 };
34560 union { /* offset: 0x2C */
34561 __I uint32_t SCR3C;
34562 __IO uint32_t SCR3L;
34563 };
34564 union { /* offset: 0x30 */
34565 __I uint32_t SCR4C;
34566 __IO uint32_t SCR4L;
34567 };
34568 union { /* offset: 0x34 */
34569 __I uint32_t SCR5C;
34570 __IO uint32_t SCR5L;
34571 };
34572 union { /* offset: 0x38 */
34573 __I uint32_t SCR6PC;
34574 __IO uint32_t SCR6PL;
34575 };
34576 __I uint32_t STATUS;
34577 __I uint32_t ENT[16];
34578 __I uint32_t PKRCNT10;
34579 __I uint32_t PKRCNT32;
34580 __I uint32_t PKRCNT54;
34581 __I uint32_t PKRCNT76;
34582 __I uint32_t PKRCNT98;
34583 __I uint32_t PKRCNTBA;
34584 __I uint32_t PKRCNTDC;
34585 __I uint32_t PKRCNTFE;
34586 __IO uint32_t SEC_CFG;
34587 __IO uint32_t INT_CTRL;
34588 __IO uint32_t INT_MASK;
34589 __I uint32_t INT_STATUS;
34590 uint8_t RESERVED_0[64];
34591 __I uint32_t VID1;
34592 __I uint32_t VID2;
34593} TRNG_Type;
34594
34595/* ----------------------------------------------------------------------------
34596 -- TRNG Register Masks
34597 ---------------------------------------------------------------------------- */
34598
34599/*
34600 * @addtogroup TRNG_Register_Masks TRNG Register Masks
34601 * @{
34602 */
34603
34604/* @name MCTL - Miscellaneous Control Register */
34605/* @{ */
34606#define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
34607#define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
34608/* SAMP_MODE
34609 * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
34610 * 0b01..use raw data into both Entropy shifter and Statistical Checker
34611 * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
34612 * 0b11..undefined/reserved.
34613 */
34614#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
34615#define TRNG_MCTL_OSC_DIV_MASK (0xCU)
34616#define TRNG_MCTL_OSC_DIV_SHIFT (2U)
34617/* OSC_DIV
34618 * 0b00..use ring oscillator with no divide
34619 * 0b01..use ring oscillator divided-by-2
34620 * 0b10..use ring oscillator divided-by-4
34621 * 0b11..use ring oscillator divided-by-8
34622 */
34623#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
34624#define TRNG_MCTL_UNUSED4_MASK (0x10U)
34625#define TRNG_MCTL_UNUSED4_SHIFT (4U)
34626#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK)
34627#define TRNG_MCTL_UNUSED5_MASK (0x20U)
34628#define TRNG_MCTL_UNUSED5_SHIFT (5U)
34629#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK)
34630#define TRNG_MCTL_RST_DEF_MASK (0x40U)
34631#define TRNG_MCTL_RST_DEF_SHIFT (6U)
34632#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
34633#define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
34634#define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
34635#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
34636#define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
34637#define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
34638#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
34639#define TRNG_MCTL_FCT_VAL_MASK (0x200U)
34640#define TRNG_MCTL_FCT_VAL_SHIFT (9U)
34641#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
34642#define TRNG_MCTL_ENT_VAL_MASK (0x400U)
34643#define TRNG_MCTL_ENT_VAL_SHIFT (10U)
34644#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
34645#define TRNG_MCTL_TST_OUT_MASK (0x800U)
34646#define TRNG_MCTL_TST_OUT_SHIFT (11U)
34647#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
34648#define TRNG_MCTL_ERR_MASK (0x1000U)
34649#define TRNG_MCTL_ERR_SHIFT (12U)
34650#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
34651#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
34652#define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
34653#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
34654#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U)
34655#define TRNG_MCTL_LRUN_CONT_SHIFT (14U)
34656#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK)
34657#define TRNG_MCTL_PRGM_MASK (0x10000U)
34658#define TRNG_MCTL_PRGM_SHIFT (16U)
34659#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
34660/* @} */
34661
34662/* @name SCMISC - Statistical Check Miscellaneous Register */
34663/* @{ */
34664#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
34665#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
34666#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
34667#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
34668#define TRNG_SCMISC_RTY_CT_SHIFT (16U)
34669#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
34670/* @} */
34671
34672/* @name PKRRNG - Poker Range Register */
34673/* @{ */
34674#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
34675#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
34676#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
34677/* @} */
34678
34679/* @name PKRMAX - Poker Maximum Limit Register */
34680/* @{ */
34681#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
34682#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
34683#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
34684/* @} */
34685
34686/* @name PKRSQ - Poker Square Calculation Result Register */
34687/* @{ */
34688#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
34689#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
34690#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
34691/* @} */
34692
34693/* @name SDCTL - Seed Control Register */
34694/* @{ */
34695#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
34696#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
34697#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
34698#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
34699#define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
34700#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
34701/* @} */
34702
34703/* @name SBLIM - Sparse Bit Limit Register */
34704/* @{ */
34705#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
34706#define TRNG_SBLIM_SB_LIM_SHIFT (0U)
34707#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
34708/* @} */
34709
34710/* @name TOTSAM - Total Samples Register */
34711/* @{ */
34712#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
34713#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
34714#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
34715/* @} */
34716
34717/* @name FRQMIN - Frequency Count Minimum Limit Register */
34718/* @{ */
34719#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
34720#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
34721#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
34722/* @} */
34723
34724/* @name FRQCNT - Frequency Count Register */
34725/* @{ */
34726#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
34727#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
34728#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
34729/* @} */
34730
34731/* @name FRQMAX - Frequency Count Maximum Limit Register */
34732/* @{ */
34733#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
34734#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
34735#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
34736/* @} */
34737
34738/* @name SCMC - Statistical Check Monobit Count Register */
34739/* @{ */
34740#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
34741#define TRNG_SCMC_MONO_CT_SHIFT (0U)
34742#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
34743/* @} */
34744
34745/* @name SCML - Statistical Check Monobit Limit Register */
34746/* @{ */
34747#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
34748#define TRNG_SCML_MONO_MAX_SHIFT (0U)
34749#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
34750#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
34751#define TRNG_SCML_MONO_RNG_SHIFT (16U)
34752#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
34753/* @} */
34754
34755/* @name SCR1C - Statistical Check Run Length 1 Count Register */
34756/* @{ */
34757#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
34758#define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
34759#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
34760#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
34761#define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
34762#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
34763/* @} */
34764
34765/* @name SCR1L - Statistical Check Run Length 1 Limit Register */
34766/* @{ */
34767#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
34768#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
34769#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
34770#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
34771#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
34772#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
34773/* @} */
34774
34775/* @name SCR2C - Statistical Check Run Length 2 Count Register */
34776/* @{ */
34777#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
34778#define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
34779#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
34780#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
34781#define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
34782#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
34783/* @} */
34784
34785/* @name SCR2L - Statistical Check Run Length 2 Limit Register */
34786/* @{ */
34787#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
34788#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
34789#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
34790#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
34791#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
34792#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
34793/* @} */
34794
34795/* @name SCR3C - Statistical Check Run Length 3 Count Register */
34796/* @{ */
34797#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
34798#define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
34799#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
34800#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
34801#define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
34802#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
34803/* @} */
34804
34805/* @name SCR3L - Statistical Check Run Length 3 Limit Register */
34806/* @{ */
34807#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
34808#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
34809#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
34810#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
34811#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
34812#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
34813/* @} */
34814
34815/* @name SCR4C - Statistical Check Run Length 4 Count Register */
34816/* @{ */
34817#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
34818#define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
34819#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
34820#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
34821#define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
34822#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
34823/* @} */
34824
34825/* @name SCR4L - Statistical Check Run Length 4 Limit Register */
34826/* @{ */
34827#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
34828#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
34829#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
34830#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
34831#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
34832#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
34833/* @} */
34834
34835/* @name SCR5C - Statistical Check Run Length 5 Count Register */
34836/* @{ */
34837#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
34838#define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
34839#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
34840#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
34841#define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
34842#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
34843/* @} */
34844
34845/* @name SCR5L - Statistical Check Run Length 5 Limit Register */
34846/* @{ */
34847#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
34848#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
34849#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
34850#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
34851#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
34852#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
34853/* @} */
34854
34855/* @name SCR6PC - Statistical Check Run Length 6+ Count Register */
34856/* @{ */
34857#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
34858#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
34859#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
34860#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
34861#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
34862#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
34863/* @} */
34864
34865/* @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
34866/* @{ */
34867#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
34868#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
34869#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
34870#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
34871#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
34872#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
34873/* @} */
34874
34875/* @name STATUS - Status Register */
34876/* @{ */
34877#define TRNG_STATUS_TF1BR0_MASK (0x1U)
34878#define TRNG_STATUS_TF1BR0_SHIFT (0U)
34879#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
34880#define TRNG_STATUS_TF1BR1_MASK (0x2U)
34881#define TRNG_STATUS_TF1BR1_SHIFT (1U)
34882#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
34883#define TRNG_STATUS_TF2BR0_MASK (0x4U)
34884#define TRNG_STATUS_TF2BR0_SHIFT (2U)
34885#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
34886#define TRNG_STATUS_TF2BR1_MASK (0x8U)
34887#define TRNG_STATUS_TF2BR1_SHIFT (3U)
34888#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
34889#define TRNG_STATUS_TF3BR0_MASK (0x10U)
34890#define TRNG_STATUS_TF3BR0_SHIFT (4U)
34891#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
34892#define TRNG_STATUS_TF3BR1_MASK (0x20U)
34893#define TRNG_STATUS_TF3BR1_SHIFT (5U)
34894#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
34895#define TRNG_STATUS_TF4BR0_MASK (0x40U)
34896#define TRNG_STATUS_TF4BR0_SHIFT (6U)
34897#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
34898#define TRNG_STATUS_TF4BR1_MASK (0x80U)
34899#define TRNG_STATUS_TF4BR1_SHIFT (7U)
34900#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
34901#define TRNG_STATUS_TF5BR0_MASK (0x100U)
34902#define TRNG_STATUS_TF5BR0_SHIFT (8U)
34903#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
34904#define TRNG_STATUS_TF5BR1_MASK (0x200U)
34905#define TRNG_STATUS_TF5BR1_SHIFT (9U)
34906#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
34907#define TRNG_STATUS_TF6PBR0_MASK (0x400U)
34908#define TRNG_STATUS_TF6PBR0_SHIFT (10U)
34909#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
34910#define TRNG_STATUS_TF6PBR1_MASK (0x800U)
34911#define TRNG_STATUS_TF6PBR1_SHIFT (11U)
34912#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
34913#define TRNG_STATUS_TFSB_MASK (0x1000U)
34914#define TRNG_STATUS_TFSB_SHIFT (12U)
34915#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
34916#define TRNG_STATUS_TFLR_MASK (0x2000U)
34917#define TRNG_STATUS_TFLR_SHIFT (13U)
34918#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
34919#define TRNG_STATUS_TFP_MASK (0x4000U)
34920#define TRNG_STATUS_TFP_SHIFT (14U)
34921#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
34922#define TRNG_STATUS_TFMB_MASK (0x8000U)
34923#define TRNG_STATUS_TFMB_SHIFT (15U)
34924#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
34925#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
34926#define TRNG_STATUS_RETRY_CT_SHIFT (16U)
34927#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
34928/* @} */
34929
34930/* @name ENT - Entropy Read Register */
34931/* @{ */
34932#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
34933#define TRNG_ENT_ENT_SHIFT (0U)
34934#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
34935/* @} */
34936
34937/* The count of TRNG_ENT */
34938#define TRNG_ENT_COUNT (16U)
34939
34940/* @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
34941/* @{ */
34942#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
34943#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
34944#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
34945#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
34946#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
34947#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
34948/* @} */
34949
34950/* @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
34951/* @{ */
34952#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
34953#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
34954#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
34955#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
34956#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
34957#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
34958/* @} */
34959
34960/* @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
34961/* @{ */
34962#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
34963#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
34964#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
34965#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
34966#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
34967#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
34968/* @} */
34969
34970/* @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
34971/* @{ */
34972#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
34973#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
34974#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
34975#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
34976#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
34977#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
34978/* @} */
34979
34980/* @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
34981/* @{ */
34982#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
34983#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
34984#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
34985#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
34986#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
34987#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
34988/* @} */
34989
34990/* @name PKRCNTBA - Statistical Check Poker Count B and A Register */
34991/* @{ */
34992#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
34993#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
34994#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
34995#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
34996#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
34997#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
34998/* @} */
34999
35000/* @name PKRCNTDC - Statistical Check Poker Count D and C Register */
35001/* @{ */
35002#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
35003#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
35004#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
35005#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
35006#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
35007#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
35008/* @} */
35009
35010/* @name PKRCNTFE - Statistical Check Poker Count F and E Register */
35011/* @{ */
35012#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
35013#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
35014#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
35015#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
35016#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
35017#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
35018/* @} */
35019
35020/* @name SEC_CFG - Security Configuration Register */
35021/* @{ */
35022#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U)
35023#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U)
35024#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK)
35025#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
35026#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
35027/* NO_PRGM
35028 * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit.
35029 * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming.
35030 */
35031#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
35032#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U)
35033#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U)
35034#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK)
35035/* @} */
35036
35037/* @name INT_CTRL - Interrupt Control Register */
35038/* @{ */
35039#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
35040#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
35041/* HW_ERR
35042 * 0b0..Corresponding bit of INT_STATUS register cleared.
35043 * 0b1..Corresponding bit of INT_STATUS register active.
35044 */
35045#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
35046#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
35047#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
35048/* ENT_VAL
35049 * 0b0..Same behavior as bit 0 of this register.
35050 * 0b1..Same behavior as bit 0 of this register.
35051 */
35052#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
35053#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
35054#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
35055/* FRQ_CT_FAIL
35056 * 0b0..Same behavior as bit 0 of this register.
35057 * 0b1..Same behavior as bit 0 of this register.
35058 */
35059#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
35060#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
35061#define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
35062#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
35063/* @} */
35064
35065/* @name INT_MASK - Mask Register */
35066/* @{ */
35067#define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
35068#define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
35069/* HW_ERR
35070 * 0b0..Corresponding interrupt of INT_STATUS is masked.
35071 * 0b1..Corresponding bit of INT_STATUS is active.
35072 */
35073#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
35074#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
35075#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
35076/* ENT_VAL
35077 * 0b0..Same behavior as bit 0 of this register.
35078 * 0b1..Same behavior as bit 0 of this register.
35079 */
35080#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
35081#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
35082#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
35083/* FRQ_CT_FAIL
35084 * 0b0..Same behavior as bit 0 of this register.
35085 * 0b1..Same behavior as bit 0 of this register.
35086 */
35087#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
35088/* @} */
35089
35090/* @name INT_STATUS - Interrupt Status Register */
35091/* @{ */
35092#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
35093#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
35094/* HW_ERR
35095 * 0b0..no error
35096 * 0b1..error detected.
35097 */
35098#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
35099#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
35100#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
35101/* ENT_VAL
35102 * 0b0..Busy generation entropy. Any value read is invalid.
35103 * 0b1..TRNG can be stopped and entropy is valid if read.
35104 */
35105#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
35106#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
35107#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
35108/* FRQ_CT_FAIL
35109 * 0b0..No hardware nor self test frequency errors.
35110 * 0b1..The frequency counter has detected a failure.
35111 */
35112#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
35113/* @} */
35114
35115/* @name VID1 - Version ID Register (MS) */
35116/* @{ */
35117#define TRNG_VID1_MIN_REV_MASK (0xFFU)
35118#define TRNG_VID1_MIN_REV_SHIFT (0U)
35119/* MIN_REV
35120 * 0b00000000..Minor revision number for TRNG.
35121 */
35122#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
35123#define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
35124#define TRNG_VID1_MAJ_REV_SHIFT (8U)
35125/* MAJ_REV
35126 * 0b00000001..Major revision number for TRNG.
35127 */
35128#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
35129#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
35130#define TRNG_VID1_IP_ID_SHIFT (16U)
35131/* IP_ID
35132 * 0b0000000000110000..ID for TRNG.
35133 */
35134#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
35135/* @} */
35136
35137/* @name VID2 - Version ID Register (LS) */
35138/* @{ */
35139#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
35140#define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
35141/* CONFIG_OPT
35142 * 0b00000000..TRNG_CONFIG_OPT for TRNG.
35143 */
35144#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
35145#define TRNG_VID2_ECO_REV_MASK (0xFF00U)
35146#define TRNG_VID2_ECO_REV_SHIFT (8U)
35147/* ECO_REV
35148 * 0b00000000..TRNG_ECO_REV for TRNG.
35149 */
35150#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
35151#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
35152#define TRNG_VID2_INTG_OPT_SHIFT (16U)
35153/* INTG_OPT
35154 * 0b00000000..INTG_OPT for TRNG.
35155 */
35156#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
35157#define TRNG_VID2_ERA_MASK (0xFF000000U)
35158#define TRNG_VID2_ERA_SHIFT (24U)
35159/* ERA
35160 * 0b00000000..COMPILE_OPT for TRNG.
35161 */
35162#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
35163/* @} */
35164
35165
35166/*
35167 * @}
35168 */ /* end of group TRNG_Register_Masks */
35169
35170
35171/* TRNG - Peripheral instance base addresses */
35172/* Peripheral TRNG base address */
35173#define TRNG_BASE (0x400CC000u)
35174/* Peripheral TRNG base pointer */
35175#define TRNG ((TRNG_Type *)TRNG_BASE)
35176/* Array initializer of TRNG peripheral base addresses */
35177#define TRNG_BASE_ADDRS { TRNG_BASE }
35178/* Array initializer of TRNG peripheral base pointers */
35179#define TRNG_BASE_PTRS { TRNG }
35180/* Interrupt vectors for the TRNG peripheral type */
35181#define TRNG_IRQS { TRNG_IRQn }
35182
35183/*
35184 * @}
35185 */ /* end of group TRNG_Peripheral_Access_Layer */
35186
35187
35188/* ----------------------------------------------------------------------------
35189 -- TSC Peripheral Access Layer
35190 ---------------------------------------------------------------------------- */
35191
35192/*
35193 * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer
35194 * @{
35195 */
35196
35197/* TSC - Register Layout Typedef */
35198typedef struct {
35199 __IO uint32_t BASIC_SETTING;
35200 uint8_t RESERVED_0[12];
35201 __IO uint32_t PRE_CHARGE_TIME;
35202 uint8_t RESERVED_1[12];
35203 __IO uint32_t FLOW_CONTROL;
35204 uint8_t RESERVED_2[12];
35205 __I uint32_t MEASEURE_VALUE;
35206 uint8_t RESERVED_3[12];
35207 __IO uint32_t INT_EN;
35208 uint8_t RESERVED_4[12];
35209 __IO uint32_t INT_SIG_EN;
35210 uint8_t RESERVED_5[12];
35211 __IO uint32_t INT_STATUS;
35212 uint8_t RESERVED_6[12];
35213 __IO uint32_t DEBUG_MODE;
35214 uint8_t RESERVED_7[12];
35215 __IO uint32_t DEBUG_MODE2;
35216} TSC_Type;
35217
35218/* ----------------------------------------------------------------------------
35219 -- TSC Register Masks
35220 ---------------------------------------------------------------------------- */
35221
35222/*
35223 * @addtogroup TSC_Register_Masks TSC Register Masks
35224 * @{
35225 */
35226
35227/* @name BASIC_SETTING - */
35228/* @{ */
35229#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U)
35230#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U)
35231/* AUTO_MEASURE - Auto Measure
35232 * 0b0..Disable Auto Measure
35233 * 0b1..Auto Measure
35234 */
35235#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK)
35236#define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U)
35237#define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U)
35238/* 4_5_WIRE - 4/5 Wire detection
35239 * 0b0..4-Wire Detection Mode
35240 * 0b1..5-Wire Detection Mode
35241 */
35242#define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK)
35243#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U)
35244#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U)
35245#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK)
35246/* @} */
35247
35248/* @name PRE_CHARGE_TIME - */
35249/* @{ */
35250#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU)
35251#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U)
35252#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK)
35253/* @} */
35254
35255/* @name FLOW_CONTROL - Flow Control */
35256/* @{ */
35257#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U)
35258#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U)
35259#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK)
35260#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U)
35261#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U)
35262/* START_MEASURE - Start Measure
35263 * 0b0..Do not start measure for now
35264 * 0b1..Start measure the X/Y coordinate value
35265 */
35266#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK)
35267#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U)
35268#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U)
35269/* DROP_MEASURE - Drop Measure
35270 * 0b0..Do not drop measure for now
35271 * 0b1..Drop the measure and controller return to idle status
35272 */
35273#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK)
35274#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U)
35275#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U)
35276/* START_SENSE - Start Sense
35277 * 0b0..Stay at idle status
35278 * 0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch
35279 */
35280#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK)
35281#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U)
35282#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U)
35283/* DISABLE
35284 * 0b0..Leave HW state machine control
35285 * 0b1..SW set to idle status
35286 */
35287#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK)
35288/* @} */
35289
35290/* @name MEASEURE_VALUE - Measure Value */
35291/* @{ */
35292#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU)
35293#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U)
35294#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK)
35295#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U)
35296#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U)
35297#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK)
35298/* @} */
35299
35300/* @name INT_EN - Interrupt Enable */
35301/* @{ */
35302#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U)
35303#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U)
35304/* MEASURE_INT_EN - Measure Interrupt Enable
35305 * 0b0..Disable measure interrupt
35306 * 0b1..Enable measure interrupt
35307 */
35308#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK)
35309#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U)
35310#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U)
35311/* DETECT_INT_EN - Detect Interrupt Enable
35312 * 0b0..Disable detect interrupt
35313 * 0b1..Enable detect interrupt
35314 */
35315#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK)
35316#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U)
35317#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U)
35318/* IDLE_SW_INT_EN - Idle Software Interrupt Enable
35319 * 0b0..Disable idle software interrupt
35320 * 0b1..Enable idle software interrupt
35321 */
35322#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK)
35323/* @} */
35324
35325/* @name INT_SIG_EN - Interrupt Signal Enable */
35326/* @{ */
35327#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U)
35328#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U)
35329#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK)
35330#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U)
35331#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U)
35332/* DETECT_SIG_EN - Detect Signal Enable
35333 * 0b0..Disable detect signal
35334 * 0b1..Enable detect signal
35335 */
35336#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK)
35337#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U)
35338#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U)
35339/* VALID_SIG_EN - Valid Signal Enable
35340 * 0b0..Disable valid signal
35341 * 0b1..Enable valid signal
35342 */
35343#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK)
35344#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U)
35345#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U)
35346/* IDLE_SW_SIG_EN - Idle Software Signal Enable
35347 * 0b0..Disable idle software signal
35348 * 0b1..Enable idle software signal
35349 */
35350#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK)
35351/* @} */
35352
35353/* @name INT_STATUS - Intterrupt Status */
35354/* @{ */
35355#define TSC_INT_STATUS_MEASURE_MASK (0x1U)
35356#define TSC_INT_STATUS_MEASURE_SHIFT (0U)
35357/* MEASURE - Measure Signal
35358 * 0b0..Does not exist a measure signal
35359 * 0b1..Exist a measure signal
35360 */
35361#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK)
35362#define TSC_INT_STATUS_DETECT_MASK (0x10U)
35363#define TSC_INT_STATUS_DETECT_SHIFT (4U)
35364/* DETECT - Detect Signal
35365 * 0b0..Does not exist a detect signal
35366 * 0b1..Exist detect signal
35367 */
35368#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK)
35369#define TSC_INT_STATUS_VALID_MASK (0x100U)
35370#define TSC_INT_STATUS_VALID_SHIFT (8U)
35371/* VALID - Valid Signal
35372 * 0b0..There is no touch detected after measurement, indicates that the measured value is not valid
35373 * 0b1..There is touch detection after measurement, indicates that the measure is valid
35374 */
35375#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK)
35376#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U)
35377#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U)
35378/* IDLE_SW - Idle Software
35379 * 0b0..Haven't return to idle status
35380 * 0b1..Already return to idle status
35381 */
35382#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK)
35383/* @} */
35384
35385/* @name DEBUG_MODE - */
35386/* @{ */
35387#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU)
35388#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U)
35389#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK)
35390#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U)
35391#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U)
35392#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK)
35393#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U)
35394#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U)
35395#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK)
35396#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U)
35397#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U)
35398/* TRIGGER - Trigger
35399 * 0b0..No hardware trigger signal
35400 * 0b1..Hardware trigger signal, the signal must last at least 1 ips clock period
35401 */
35402#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK)
35403#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U)
35404#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U)
35405/* ADC_COCO_CLEAR - ADC Coco Clear
35406 * 0b0..No ADC COCO clear
35407 * 0b1..Set ADC COCO clear
35408 */
35409#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK)
35410#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U)
35411#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U)
35412/* ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable
35413 * 0b0..Allow TSC hardware generates ADC COCO clear
35414 * 0b1..Prevent TSC from generate ADC COCO clear signal
35415 */
35416#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK)
35417#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U)
35418#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U)
35419/* DEBUG_EN - Debug Enable
35420 * 0b0..Enable debug mode
35421 * 0b1..Disable debug mode
35422 */
35423#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK)
35424/* @} */
35425
35426/* @name DEBUG_MODE2 - */
35427/* @{ */
35428#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U)
35429#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U)
35430/* XPUL_PULL_DOWN - XPUL Wire Pull Down Switch
35431 * 0b0..Close the switch
35432 * 0b1..Open up the switch
35433 */
35434#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK)
35435#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U)
35436#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U)
35437/* XPUL_PULL_UP - XPUL Wire Pull Up Switch
35438 * 0b0..Close the switch
35439 * 0b1..Open up the switch
35440 */
35441#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK)
35442#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U)
35443#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U)
35444/* XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch
35445 * 0b0..Close the switch
35446 * 0b1..Open up the switch
35447 */
35448#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK)
35449#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U)
35450#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U)
35451/* XNUR_PULL_DOWN - XNUR Wire Pull Down Switch
35452 * 0b0..Close the switch
35453 * 0b1..Open up the switch
35454 */
35455#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK)
35456#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U)
35457#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U)
35458/* XNUR_PULL_UP - XNUR Wire Pull Up Switch
35459 * 0b0..Close the switch
35460 * 0b1..Open up the switch
35461 */
35462#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK)
35463#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U)
35464#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U)
35465/* XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch
35466 * 0b0..Close the switch
35467 * 0b1..Open up the switch
35468 */
35469#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK)
35470#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U)
35471#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U)
35472/* YPLL_PULL_DOWN - YPLL Wire Pull Down Switch
35473 * 0b0..Close the switch
35474 * 0b1..Open up the switch
35475 */
35476#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK)
35477#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U)
35478#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U)
35479/* YPLL_PULL_UP - YPLL Wire Pull Up Switch
35480 * 0b0..Close the switch
35481 * 0b1..Open the switch
35482 */
35483#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK)
35484#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U)
35485#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U)
35486/* YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch
35487 * 0b0..Close the switch
35488 * 0b1..Open up the switch
35489 */
35490#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK)
35491#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U)
35492#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U)
35493/* YNLR_PULL_DOWN - YNLR Wire Pull Down Switch
35494 * 0b0..Close the switch
35495 * 0b1..Open up the switch
35496 */
35497#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK)
35498#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U)
35499#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U)
35500/* YNLR_PULL_UP - YNLR Wire Pull Up Switch
35501 * 0b0..Close the switch
35502 * 0b1..Open up the switch
35503 */
35504#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK)
35505#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U)
35506#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U)
35507/* YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch
35508 * 0b0..Close the switch
35509 * 0b1..Open up the switch
35510 */
35511#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK)
35512#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U)
35513#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U)
35514/* WIPER_PULL_DOWN - Wiper Wire Pull Down Switch
35515 * 0b0..Close the switch
35516 * 0b1..Open up the switch
35517 */
35518#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK)
35519#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U)
35520#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U)
35521/* WIPER_PULL_UP - Wiper Wire Pull Up Switch
35522 * 0b0..Close the switch
35523 * 0b1..Open up the switch
35524 */
35525#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK)
35526#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U)
35527#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U)
35528/* WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch
35529 * 0b0..Close the switch
35530 * 0b1..Open up the switch
35531 */
35532#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK)
35533#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U)
35534#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U)
35535/* DETECT_FOUR_WIRE - Detect Four Wire
35536 * 0b0..No detect signal
35537 * 0b1..Yes, there is a detect on the touch screen.
35538 */
35539#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK)
35540#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U)
35541#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U)
35542/* DETECT_FIVE_WIRE - Detect Five Wire
35543 * 0b0..No detect signal
35544 * 0b1..Yes, there is a detect on the touch screen.
35545 */
35546#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK)
35547#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U)
35548#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U)
35549/* STATE_MACHINE - State Machine
35550 * 0b000..Idle
35551 * 0b001..Pre-charge
35552 * 0b010..Detect
35553 * 0b011..X-measure
35554 * 0b100..Y-measure
35555 * 0b101..Pre-charge
35556 * 0b110..Detect
35557 */
35558#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK)
35559#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U)
35560#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U)
35561/* INTERMEDIATE - Intermediate State
35562 * 0b0..Not in intermedia
35563 * 0b1..Intermedia
35564 */
35565#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK)
35566#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U)
35567#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U)
35568/* DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire
35569 * 0b0..Do not read four wire detect value, read default value from analogue
35570 * 0b1..Read four wire detect status from analogue
35571 */
35572#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK)
35573#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U)
35574#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U)
35575/* DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire
35576 * 0b0..Do not read five wire detect value, read default value from analogue
35577 * 0b1..Read five wire detect status from analogue
35578 */
35579#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK)
35580#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U)
35581#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U)
35582/* DE_GLITCH
35583 * 0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles
35584 * 0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles
35585 * 0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles
35586 * 0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles
35587 */
35588#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK)
35589/* @} */
35590
35591
35592/*
35593 * @}
35594 */ /* end of group TSC_Register_Masks */
35595
35596
35597/* TSC - Peripheral instance base addresses */
35598/* Peripheral TSC base address */
35599#define TSC_BASE (0x400E0000u)
35600/* Peripheral TSC base pointer */
35601#define TSC ((TSC_Type *)TSC_BASE)
35602/* Array initializer of TSC peripheral base addresses */
35603#define TSC_BASE_ADDRS { TSC_BASE }
35604/* Array initializer of TSC peripheral base pointers */
35605#define TSC_BASE_PTRS { TSC }
35606/* Interrupt vectors for the TSC peripheral type */
35607#define TSC_IRQS { TSC_DIG_IRQn }
35608/* Backward compatibility */
35609#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASK
35610#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFT
35611#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x)
35612
35613
35614/*
35615 * @}
35616 */ /* end of group TSC_Peripheral_Access_Layer */
35617
35618
35619/* ----------------------------------------------------------------------------
35620 -- USB Peripheral Access Layer
35621 ---------------------------------------------------------------------------- */
35622
35623/*
35624 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
35625 * @{
35626 */
35627
35628/* USB - Register Layout Typedef */
35629typedef struct {
35630 __I uint32_t ID;
35631 __I uint32_t HWGENERAL;
35632 __I uint32_t HWHOST;
35633 __I uint32_t HWDEVICE;
35634 __I uint32_t HWTXBUF;
35635 __I uint32_t HWRXBUF;
35636 uint8_t RESERVED_0[104];
35637 __IO uint32_t GPTIMER0LD;
35638 __IO uint32_t GPTIMER0CTRL;
35639 __IO uint32_t GPTIMER1LD;
35640 __IO uint32_t GPTIMER1CTRL;
35641 __IO uint32_t SBUSCFG;
35642 uint8_t RESERVED_1[108];
35643 __I uint8_t CAPLENGTH;
35644 uint8_t RESERVED_2[1];
35645 __I uint16_t HCIVERSION;
35646 __I uint32_t HCSPARAMS;
35647 __I uint32_t HCCPARAMS;
35648 uint8_t RESERVED_3[20];
35649 __I uint16_t DCIVERSION;
35650 uint8_t RESERVED_4[2];
35651 __I uint32_t DCCPARAMS;
35652 uint8_t RESERVED_5[24];
35653 __IO uint32_t USBCMD;
35654 __IO uint32_t USBSTS;
35655 __IO uint32_t USBINTR;
35656 __IO uint32_t FRINDEX;
35657 uint8_t RESERVED_6[4];
35658 union { /* offset: 0x154 */
35659 __IO uint32_t DEVICEADDR;
35660 __IO uint32_t PERIODICLISTBASE;
35661 };
35662 union { /* offset: 0x158 */
35663 __IO uint32_t ASYNCLISTADDR;
35664 __IO uint32_t ENDPTLISTADDR;
35665 };
35666 uint8_t RESERVED_7[4];
35667 __IO uint32_t BURSTSIZE;
35668 __IO uint32_t TXFILLTUNING;
35669 uint8_t RESERVED_8[16];
35670 __IO uint32_t ENDPTNAK;
35671 __IO uint32_t ENDPTNAKEN;
35672 __I uint32_t CONFIGFLAG;
35673 __IO uint32_t PORTSC1;
35674 uint8_t RESERVED_9[28];
35675 __IO uint32_t OTGSC;
35676 __IO uint32_t USBMODE;
35677 __IO uint32_t ENDPTSETUPSTAT;
35678 __IO uint32_t ENDPTPRIME;
35679 __IO uint32_t ENDPTFLUSH;
35680 __I uint32_t ENDPTSTAT;
35681 __IO uint32_t ENDPTCOMPLETE;
35682// __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */
35683 __IO uint32_t ENDPTCTRL[8];
35684} USB_Type;
35685
35686/* ----------------------------------------------------------------------------
35687 -- USB Register Masks
35688 ---------------------------------------------------------------------------- */
35689
35690/*
35691 * @addtogroup USB_Register_Masks USB Register Masks
35692 * @{
35693 */
35694
35695/* @name ID - Identification register */
35696/* @{ */
35697#define USB_ID_ID_MASK (0x3FU)
35698#define USB_ID_ID_SHIFT (0U)
35699#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
35700#define USB_ID_NID_MASK (0x3F00U)
35701#define USB_ID_NID_SHIFT (8U)
35702#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
35703#define USB_ID_REVISION_MASK (0xFF0000U)
35704#define USB_ID_REVISION_SHIFT (16U)
35705#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
35706/* @} */
35707
35708/* @name HWGENERAL - Hardware General */
35709/* @{ */
35710#define USB_HWGENERAL_PHYW_MASK (0x30U)
35711#define USB_HWGENERAL_PHYW_SHIFT (4U)
35712/* PHYW
35713 * 0b00..8 bit wide data bus Software non-programmable
35714 * 0b01..16 bit wide data bus Software non-programmable
35715 * 0b10..Reset to 8 bit wide data bus Software programmable
35716 * 0b11..Reset to 16 bit wide data bus Software programmable
35717 */
35718#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
35719#define USB_HWGENERAL_PHYM_MASK (0x1C0U)
35720#define USB_HWGENERAL_PHYM_SHIFT (6U)
35721/* PHYM
35722 * 0b000..UTMI/UMTI+
35723 * 0b001..ULPI DDR
35724 * 0b010..ULPI
35725 * 0b011..Serial Only
35726 * 0b100..Software programmable - reset to UTMI/UTMI+
35727 * 0b101..Software programmable - reset to ULPI DDR
35728 * 0b110..Software programmable - reset to ULPI
35729 * 0b111..Software programmable - reset to Serial
35730 */
35731#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
35732#define USB_HWGENERAL_SM_MASK (0x600U)
35733#define USB_HWGENERAL_SM_SHIFT (9U)
35734/* SM
35735 * 0b00..No Serial Engine, always use parallel signalling.
35736 * 0b01..Serial Engine present, always use serial signalling for FS/LS.
35737 * 0b10..Software programmable - Reset to use parallel signalling for FS/LS
35738 * 0b11..Software programmable - Reset to use serial signalling for FS/LS
35739 */
35740#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
35741/* @} */
35742
35743/* @name HWHOST - Host Hardware Parameters */
35744/* @{ */
35745#define USB_HWHOST_HC_MASK (0x1U)
35746#define USB_HWHOST_HC_SHIFT (0U)
35747/* HC
35748 * 0b1..Supported
35749 * 0b0..Not supported
35750 */
35751#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
35752#define USB_HWHOST_NPORT_MASK (0xEU)
35753#define USB_HWHOST_NPORT_SHIFT (1U)
35754#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
35755/* @} */
35756
35757/* @name HWDEVICE - Device Hardware Parameters */
35758/* @{ */
35759#define USB_HWDEVICE_DC_MASK (0x1U)
35760#define USB_HWDEVICE_DC_SHIFT (0U)
35761/* DC
35762 * 0b1..Supported
35763 * 0b0..Not supported
35764 */
35765#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
35766#define USB_HWDEVICE_DEVEP_MASK (0x3EU)
35767#define USB_HWDEVICE_DEVEP_SHIFT (1U)
35768#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
35769/* @} */
35770
35771/* @name HWTXBUF - TX Buffer Hardware Parameters */
35772/* @{ */
35773#define USB_HWTXBUF_TXBURST_MASK (0xFFU)
35774#define USB_HWTXBUF_TXBURST_SHIFT (0U)
35775#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
35776#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
35777#define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
35778#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
35779/* @} */
35780
35781/* @name HWRXBUF - RX Buffer Hardware Parameters */
35782/* @{ */
35783#define USB_HWRXBUF_RXBURST_MASK (0xFFU)
35784#define USB_HWRXBUF_RXBURST_SHIFT (0U)
35785#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
35786#define USB_HWRXBUF_RXADD_MASK (0xFF00U)
35787#define USB_HWRXBUF_RXADD_SHIFT (8U)
35788#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
35789/* @} */
35790
35791/* @name GPTIMER0LD - General Purpose Timer #0 Load */
35792/* @{ */
35793#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
35794#define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
35795#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
35796/* @} */
35797
35798/* @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
35799/* @{ */
35800#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
35801#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
35802#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
35803#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
35804#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
35805/* GPTMODE
35806 * 0b0..One Shot Mode
35807 * 0b1..Repeat Mode
35808 */
35809#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
35810#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
35811#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
35812/* GPTRST
35813 * 0b0..No action
35814 * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
35815 */
35816#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
35817#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
35818#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
35819/* GPTRUN
35820 * 0b0..Stop counting
35821 * 0b1..Run
35822 */
35823#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
35824/* @} */
35825
35826/* @name GPTIMER1LD - General Purpose Timer #1 Load */
35827/* @{ */
35828#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
35829#define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
35830#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
35831/* @} */
35832
35833/* @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
35834/* @{ */
35835#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
35836#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
35837#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
35838#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
35839#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
35840/* GPTMODE
35841 * 0b0..One Shot Mode
35842 * 0b1..Repeat Mode
35843 */
35844#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
35845#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
35846#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
35847/* GPTRST
35848 * 0b0..No action
35849 * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
35850 */
35851#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
35852#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
35853#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
35854/* GPTRUN
35855 * 0b0..Stop counting
35856 * 0b1..Run
35857 */
35858#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
35859/* @} */
35860
35861/* @name SBUSCFG - System Bus Config */
35862/* @{ */
35863#define USB_SBUSCFG_AHBBRST_MASK (0x7U)
35864#define USB_SBUSCFG_AHBBRST_SHIFT (0U)
35865/* AHBBRST
35866 * 0b000..Incremental burst of unspecified length only
35867 * 0b001..INCR4 burst, then single transfer
35868 * 0b010..INCR8 burst, INCR4 burst, then single transfer
35869 * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
35870 * 0b100..Reserved, don't use
35871 * 0b101..INCR4 burst, then incremental burst of unspecified length
35872 * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
35873 * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
35874 */
35875#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
35876/* @} */
35877
35878/* @name CAPLENGTH - Capability Registers Length */
35879/* @{ */
35880#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
35881#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
35882#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
35883/* @} */
35884
35885/* @name HCIVERSION - Host Controller Interface Version */
35886/* @{ */
35887#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
35888#define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
35889#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
35890/* @} */
35891
35892/* @name HCSPARAMS - Host Controller Structural Parameters */
35893/* @{ */
35894#define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
35895#define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
35896#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
35897#define USB_HCSPARAMS_PPC_MASK (0x10U)
35898#define USB_HCSPARAMS_PPC_SHIFT (4U)
35899#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
35900#define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
35901#define USB_HCSPARAMS_N_PCC_SHIFT (8U)
35902#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
35903#define USB_HCSPARAMS_N_CC_MASK (0xF000U)
35904#define USB_HCSPARAMS_N_CC_SHIFT (12U)
35905/* N_CC
35906 * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
35907 * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
35908 */
35909#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
35910#define USB_HCSPARAMS_PI_MASK (0x10000U)
35911#define USB_HCSPARAMS_PI_SHIFT (16U)
35912#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
35913#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
35914#define USB_HCSPARAMS_N_PTT_SHIFT (20U)
35915#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
35916#define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
35917#define USB_HCSPARAMS_N_TT_SHIFT (24U)
35918#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
35919/* @} */
35920
35921/* @name HCCPARAMS - Host Controller Capability Parameters */
35922/* @{ */
35923#define USB_HCCPARAMS_ADC_MASK (0x1U)
35924#define USB_HCCPARAMS_ADC_SHIFT (0U)
35925#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
35926#define USB_HCCPARAMS_PFL_MASK (0x2U)
35927#define USB_HCCPARAMS_PFL_SHIFT (1U)
35928#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
35929#define USB_HCCPARAMS_ASP_MASK (0x4U)
35930#define USB_HCCPARAMS_ASP_SHIFT (2U)
35931#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
35932#define USB_HCCPARAMS_IST_MASK (0xF0U)
35933#define USB_HCCPARAMS_IST_SHIFT (4U)
35934#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
35935#define USB_HCCPARAMS_EECP_MASK (0xFF00U)
35936#define USB_HCCPARAMS_EECP_SHIFT (8U)
35937#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
35938/* @} */
35939
35940/* @name DCIVERSION - Device Controller Interface Version */
35941/* @{ */
35942#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
35943#define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
35944#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
35945/* @} */
35946
35947/* @name DCCPARAMS - Device Controller Capability Parameters */
35948/* @{ */
35949#define USB_DCCPARAMS_DEN_MASK (0x1FU)
35950#define USB_DCCPARAMS_DEN_SHIFT (0U)
35951#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
35952#define USB_DCCPARAMS_DC_MASK (0x80U)
35953#define USB_DCCPARAMS_DC_SHIFT (7U)
35954#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
35955#define USB_DCCPARAMS_HC_MASK (0x100U)
35956#define USB_DCCPARAMS_HC_SHIFT (8U)
35957#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
35958/* @} */
35959
35960/* @name USBCMD - USB Command Register */
35961/* @{ */
35962#define USB_USBCMD_RS_MASK (0x1U)
35963#define USB_USBCMD_RS_SHIFT (0U)
35964#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
35965#define USB_USBCMD_RST_MASK (0x2U)
35966#define USB_USBCMD_RST_SHIFT (1U)
35967#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
35968#define USB_USBCMD_FS_1_MASK (0xCU)
35969#define USB_USBCMD_FS_1_SHIFT (2U)
35970#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
35971#define USB_USBCMD_PSE_MASK (0x10U)
35972#define USB_USBCMD_PSE_SHIFT (4U)
35973/* PSE
35974 * 0b0..Do not process the Periodic Schedule
35975 * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
35976 */
35977#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
35978#define USB_USBCMD_ASE_MASK (0x20U)
35979#define USB_USBCMD_ASE_SHIFT (5U)
35980/* ASE
35981 * 0b0..Do not process the Asynchronous Schedule.
35982 * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
35983 */
35984#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
35985#define USB_USBCMD_IAA_MASK (0x40U)
35986#define USB_USBCMD_IAA_SHIFT (6U)
35987#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
35988#define USB_USBCMD_ASP_MASK (0x300U)
35989#define USB_USBCMD_ASP_SHIFT (8U)
35990#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
35991#define USB_USBCMD_ASPE_MASK (0x800U)
35992#define USB_USBCMD_ASPE_SHIFT (11U)
35993#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
35994#define USB_USBCMD_SUTW_MASK (0x2000U)
35995#define USB_USBCMD_SUTW_SHIFT (13U)
35996#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
35997#define USB_USBCMD_ATDTW_MASK (0x4000U)
35998#define USB_USBCMD_ATDTW_SHIFT (14U)
35999#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
36000#define USB_USBCMD_FS_2_MASK (0x8000U)
36001#define USB_USBCMD_FS_2_SHIFT (15U)
36002/* FS_2
36003 * 0b0..1024 elements (4096 bytes) Default value
36004 * 0b1..512 elements (2048 bytes)
36005 */
36006#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
36007#define USB_USBCMD_ITC_MASK (0xFF0000U)
36008#define USB_USBCMD_ITC_SHIFT (16U)
36009/* ITC
36010 * 0b00000000..Immediate (no threshold)
36011 * 0b00000001..1 micro-frame
36012 * 0b00000010..2 micro-frames
36013 * 0b00000100..4 micro-frames
36014 * 0b00001000..8 micro-frames
36015 * 0b00010000..16 micro-frames
36016 * 0b00100000..32 micro-frames
36017 * 0b01000000..64 micro-frames
36018 */
36019#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
36020/* @} */
36021
36022/* @name USBSTS - USB Status Register */
36023/* @{ */
36024#define USB_USBSTS_UI_MASK (0x1U)
36025#define USB_USBSTS_UI_SHIFT (0U)
36026#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
36027#define USB_USBSTS_UEI_MASK (0x2U)
36028#define USB_USBSTS_UEI_SHIFT (1U)
36029#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
36030#define USB_USBSTS_PCI_MASK (0x4U)
36031#define USB_USBSTS_PCI_SHIFT (2U)
36032#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
36033#define USB_USBSTS_FRI_MASK (0x8U)
36034#define USB_USBSTS_FRI_SHIFT (3U)
36035#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
36036#define USB_USBSTS_SEI_MASK (0x10U)
36037#define USB_USBSTS_SEI_SHIFT (4U)
36038#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
36039#define USB_USBSTS_AAI_MASK (0x20U)
36040#define USB_USBSTS_AAI_SHIFT (5U)
36041#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
36042#define USB_USBSTS_URI_MASK (0x40U)
36043#define USB_USBSTS_URI_SHIFT (6U)
36044#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
36045#define USB_USBSTS_SRI_MASK (0x80U)
36046#define USB_USBSTS_SRI_SHIFT (7U)
36047#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
36048#define USB_USBSTS_SLI_MASK (0x100U)
36049#define USB_USBSTS_SLI_SHIFT (8U)
36050#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
36051#define USB_USBSTS_ULPII_MASK (0x400U)
36052#define USB_USBSTS_ULPII_SHIFT (10U)
36053#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
36054#define USB_USBSTS_HCH_MASK (0x1000U)
36055#define USB_USBSTS_HCH_SHIFT (12U)
36056#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
36057#define USB_USBSTS_RCL_MASK (0x2000U)
36058#define USB_USBSTS_RCL_SHIFT (13U)
36059#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
36060#define USB_USBSTS_PS_MASK (0x4000U)
36061#define USB_USBSTS_PS_SHIFT (14U)
36062#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
36063#define USB_USBSTS_AS_MASK (0x8000U)
36064#define USB_USBSTS_AS_SHIFT (15U)
36065#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
36066#define USB_USBSTS_NAKI_MASK (0x10000U)
36067#define USB_USBSTS_NAKI_SHIFT (16U)
36068#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
36069#define USB_USBSTS_TI0_MASK (0x1000000U)
36070#define USB_USBSTS_TI0_SHIFT (24U)
36071#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
36072#define USB_USBSTS_TI1_MASK (0x2000000U)
36073#define USB_USBSTS_TI1_SHIFT (25U)
36074#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
36075/* @} */
36076
36077/* @name USBINTR - Interrupt Enable Register */
36078/* @{ */
36079#define USB_USBINTR_UE_MASK (0x1U)
36080#define USB_USBINTR_UE_SHIFT (0U)
36081#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
36082#define USB_USBINTR_UEE_MASK (0x2U)
36083#define USB_USBINTR_UEE_SHIFT (1U)
36084#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
36085#define USB_USBINTR_PCE_MASK (0x4U)
36086#define USB_USBINTR_PCE_SHIFT (2U)
36087#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
36088#define USB_USBINTR_FRE_MASK (0x8U)
36089#define USB_USBINTR_FRE_SHIFT (3U)
36090#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
36091#define USB_USBINTR_SEE_MASK (0x10U)
36092#define USB_USBINTR_SEE_SHIFT (4U)
36093#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
36094#define USB_USBINTR_AAE_MASK (0x20U)
36095#define USB_USBINTR_AAE_SHIFT (5U)
36096#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
36097#define USB_USBINTR_URE_MASK (0x40U)
36098#define USB_USBINTR_URE_SHIFT (6U)
36099#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
36100#define USB_USBINTR_SRE_MASK (0x80U)
36101#define USB_USBINTR_SRE_SHIFT (7U)
36102#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
36103#define USB_USBINTR_SLE_MASK (0x100U)
36104#define USB_USBINTR_SLE_SHIFT (8U)
36105#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
36106#define USB_USBINTR_ULPIE_MASK (0x400U)
36107#define USB_USBINTR_ULPIE_SHIFT (10U)
36108#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
36109#define USB_USBINTR_NAKE_MASK (0x10000U)
36110#define USB_USBINTR_NAKE_SHIFT (16U)
36111#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
36112#define USB_USBINTR_UAIE_MASK (0x40000U)
36113#define USB_USBINTR_UAIE_SHIFT (18U)
36114#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
36115#define USB_USBINTR_UPIE_MASK (0x80000U)
36116#define USB_USBINTR_UPIE_SHIFT (19U)
36117#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
36118#define USB_USBINTR_TIE0_MASK (0x1000000U)
36119#define USB_USBINTR_TIE0_SHIFT (24U)
36120#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
36121#define USB_USBINTR_TIE1_MASK (0x2000000U)
36122#define USB_USBINTR_TIE1_SHIFT (25U)
36123#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
36124/* @} */
36125
36126/* @name FRINDEX - USB Frame Index */
36127/* @{ */
36128#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
36129#define USB_FRINDEX_FRINDEX_SHIFT (0U)
36130/* FRINDEX
36131 * 0b00000000000000..(1024) 12
36132 * 0b00000000000001..(512) 11
36133 * 0b00000000000010..(256) 10
36134 * 0b00000000000011..(128) 9
36135 * 0b00000000000100..(64) 8
36136 * 0b00000000000101..(32) 7
36137 * 0b00000000000110..(16) 6
36138 * 0b00000000000111..(8) 5
36139 */
36140#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
36141/* @} */
36142
36143/* @name DEVICEADDR - Device Address */
36144/* @{ */
36145#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
36146#define USB_DEVICEADDR_USBADRA_SHIFT (24U)
36147#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
36148#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
36149#define USB_DEVICEADDR_USBADR_SHIFT (25U)
36150#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
36151/* @} */
36152
36153/* @name PERIODICLISTBASE - Frame List Base Address */
36154/* @{ */
36155#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
36156#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
36157#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
36158/* @} */
36159
36160/* @name ASYNCLISTADDR - Next Asynch. Address */
36161/* @{ */
36162#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
36163#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
36164#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
36165/* @} */
36166
36167/* @name ENDPTLISTADDR - Endpoint List Address */
36168/* @{ */
36169#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
36170#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
36171#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
36172/* @} */
36173
36174/* @name BURSTSIZE - Programmable Burst Size */
36175/* @{ */
36176#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
36177#define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
36178#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
36179#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
36180#define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
36181#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
36182/* @} */
36183
36184/* @name TXFILLTUNING - TX FIFO Fill Tuning */
36185/* @{ */
36186#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
36187#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
36188#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
36189#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
36190#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
36191#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
36192#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
36193#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
36194#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
36195/* @} */
36196
36197/* @name ENDPTNAK - Endpoint NAK */
36198/* @{ */
36199#define USB_ENDPTNAK_EPRN_MASK (0xFFU)
36200#define USB_ENDPTNAK_EPRN_SHIFT (0U)
36201#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
36202#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
36203#define USB_ENDPTNAK_EPTN_SHIFT (16U)
36204#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
36205/* @} */
36206
36207/* @name ENDPTNAKEN - Endpoint NAK Enable */
36208/* @{ */
36209#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
36210#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
36211#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
36212#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
36213#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
36214#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
36215/* @} */
36216
36217/* @name CONFIGFLAG - Configure Flag Register */
36218/* @{ */
36219#define USB_CONFIGFLAG_CF_MASK (0x1U)
36220#define USB_CONFIGFLAG_CF_SHIFT (0U)
36221/* CF
36222 * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
36223 * 0b1..Port routing control logic default-routes all ports to this host controller.
36224 */
36225#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
36226/* @} */
36227
36228/* @name PORTSC1 - Port Status & Control */
36229/* @{ */
36230#define USB_PORTSC1_CCS_MASK (0x1U)
36231#define USB_PORTSC1_CCS_SHIFT (0U)
36232#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
36233#define USB_PORTSC1_CSC_MASK (0x2U)
36234#define USB_PORTSC1_CSC_SHIFT (1U)
36235#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
36236#define USB_PORTSC1_PE_MASK (0x4U)
36237#define USB_PORTSC1_PE_SHIFT (2U)
36238#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
36239#define USB_PORTSC1_PEC_MASK (0x8U)
36240#define USB_PORTSC1_PEC_SHIFT (3U)
36241#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
36242#define USB_PORTSC1_OCA_MASK (0x10U)
36243#define USB_PORTSC1_OCA_SHIFT (4U)
36244/* OCA
36245 * 0b1..This port currently has an over-current condition
36246 * 0b0..This port does not have an over-current condition.
36247 */
36248#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
36249#define USB_PORTSC1_OCC_MASK (0x20U)
36250#define USB_PORTSC1_OCC_SHIFT (5U)
36251#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
36252#define USB_PORTSC1_FPR_MASK (0x40U)
36253#define USB_PORTSC1_FPR_SHIFT (6U)
36254#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
36255#define USB_PORTSC1_SUSP_MASK (0x80U)
36256#define USB_PORTSC1_SUSP_SHIFT (7U)
36257#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
36258#define USB_PORTSC1_PR_MASK (0x100U)
36259#define USB_PORTSC1_PR_SHIFT (8U)
36260#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
36261#define USB_PORTSC1_HSP_MASK (0x200U)
36262#define USB_PORTSC1_HSP_SHIFT (9U)
36263#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
36264#define USB_PORTSC1_LS_MASK (0xC00U)
36265#define USB_PORTSC1_LS_SHIFT (10U)
36266/* LS
36267 * 0b00..SE0
36268 * 0b10..J-state
36269 * 0b01..K-state
36270 * 0b11..Undefined
36271 */
36272#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
36273#define USB_PORTSC1_PP_MASK (0x1000U)
36274#define USB_PORTSC1_PP_SHIFT (12U)
36275#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
36276#define USB_PORTSC1_PO_MASK (0x2000U)
36277#define USB_PORTSC1_PO_SHIFT (13U)
36278#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
36279#define USB_PORTSC1_PIC_MASK (0xC000U)
36280#define USB_PORTSC1_PIC_SHIFT (14U)
36281/* PIC
36282 * 0b00..Port indicators are off
36283 * 0b01..Amber
36284 * 0b10..Green
36285 * 0b11..Undefined
36286 */
36287#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
36288#define USB_PORTSC1_PTC_MASK (0xF0000U)
36289#define USB_PORTSC1_PTC_SHIFT (16U)
36290/* PTC
36291 * 0b0000..TEST_MODE_DISABLE
36292 * 0b0001..J_STATE
36293 * 0b0010..K_STATE
36294 * 0b0011..SE0 (host) / NAK (device)
36295 * 0b0100..Packet
36296 * 0b0101..FORCE_ENABLE_HS
36297 * 0b0110..FORCE_ENABLE_FS
36298 * 0b0111..FORCE_ENABLE_LS
36299 */
36300#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
36301#define USB_PORTSC1_WKCN_MASK (0x100000U)
36302#define USB_PORTSC1_WKCN_SHIFT (20U)
36303#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
36304#define USB_PORTSC1_WKDC_MASK (0x200000U)
36305#define USB_PORTSC1_WKDC_SHIFT (21U)
36306#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
36307#define USB_PORTSC1_WKOC_MASK (0x400000U)
36308#define USB_PORTSC1_WKOC_SHIFT (22U)
36309#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
36310#define USB_PORTSC1_PHCD_MASK (0x800000U)
36311#define USB_PORTSC1_PHCD_SHIFT (23U)
36312/* PHCD
36313 * 0b1..Disable PHY clock
36314 * 0b0..Enable PHY clock
36315 */
36316#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
36317#define USB_PORTSC1_PFSC_MASK (0x1000000U)
36318#define USB_PORTSC1_PFSC_SHIFT (24U)
36319/* PFSC
36320 * 0b1..Forced to full speed
36321 * 0b0..Normal operation
36322 */
36323#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
36324#define USB_PORTSC1_PTS_2_MASK (0x2000000U)
36325#define USB_PORTSC1_PTS_2_SHIFT (25U)
36326#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
36327#define USB_PORTSC1_PSPD_MASK (0xC000000U)
36328#define USB_PORTSC1_PSPD_SHIFT (26U)
36329/* PSPD
36330 * 0b00..Full Speed
36331 * 0b01..Low Speed
36332 * 0b10..High Speed
36333 * 0b11..Undefined
36334 */
36335#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
36336#define USB_PORTSC1_PTW_MASK (0x10000000U)
36337#define USB_PORTSC1_PTW_SHIFT (28U)
36338/* PTW
36339 * 0b0..Select the 8-bit UTMI interface [60MHz]
36340 * 0b1..Select the 16-bit UTMI interface [30MHz]
36341 */
36342#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
36343#define USB_PORTSC1_STS_MASK (0x20000000U)
36344#define USB_PORTSC1_STS_SHIFT (29U)
36345#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
36346#define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
36347#define USB_PORTSC1_PTS_1_SHIFT (30U)
36348#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
36349/* @} */
36350
36351/* @name OTGSC - On-The-Go Status & control */
36352/* @{ */
36353#define USB_OTGSC_VD_MASK (0x1U)
36354#define USB_OTGSC_VD_SHIFT (0U)
36355#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
36356#define USB_OTGSC_VC_MASK (0x2U)
36357#define USB_OTGSC_VC_SHIFT (1U)
36358#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
36359#define USB_OTGSC_OT_MASK (0x8U)
36360#define USB_OTGSC_OT_SHIFT (3U)
36361#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
36362#define USB_OTGSC_DP_MASK (0x10U)
36363#define USB_OTGSC_DP_SHIFT (4U)
36364#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
36365#define USB_OTGSC_IDPU_MASK (0x20U)
36366#define USB_OTGSC_IDPU_SHIFT (5U)
36367#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
36368#define USB_OTGSC_ID_MASK (0x100U)
36369#define USB_OTGSC_ID_SHIFT (8U)
36370#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
36371#define USB_OTGSC_AVV_MASK (0x200U)
36372#define USB_OTGSC_AVV_SHIFT (9U)
36373#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
36374#define USB_OTGSC_ASV_MASK (0x400U)
36375#define USB_OTGSC_ASV_SHIFT (10U)
36376#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
36377#define USB_OTGSC_BSV_MASK (0x800U)
36378#define USB_OTGSC_BSV_SHIFT (11U)
36379#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
36380#define USB_OTGSC_BSE_MASK (0x1000U)
36381#define USB_OTGSC_BSE_SHIFT (12U)
36382#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
36383#define USB_OTGSC_TOG_1MS_MASK (0x2000U)
36384#define USB_OTGSC_TOG_1MS_SHIFT (13U)
36385#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
36386#define USB_OTGSC_DPS_MASK (0x4000U)
36387#define USB_OTGSC_DPS_SHIFT (14U)
36388#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
36389#define USB_OTGSC_IDIS_MASK (0x10000U)
36390#define USB_OTGSC_IDIS_SHIFT (16U)
36391#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
36392#define USB_OTGSC_AVVIS_MASK (0x20000U)
36393#define USB_OTGSC_AVVIS_SHIFT (17U)
36394#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
36395#define USB_OTGSC_ASVIS_MASK (0x40000U)
36396#define USB_OTGSC_ASVIS_SHIFT (18U)
36397#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
36398#define USB_OTGSC_BSVIS_MASK (0x80000U)
36399#define USB_OTGSC_BSVIS_SHIFT (19U)
36400#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
36401#define USB_OTGSC_BSEIS_MASK (0x100000U)
36402#define USB_OTGSC_BSEIS_SHIFT (20U)
36403#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
36404#define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
36405#define USB_OTGSC_STATUS_1MS_SHIFT (21U)
36406#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
36407#define USB_OTGSC_DPIS_MASK (0x400000U)
36408#define USB_OTGSC_DPIS_SHIFT (22U)
36409#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
36410#define USB_OTGSC_IDIE_MASK (0x1000000U)
36411#define USB_OTGSC_IDIE_SHIFT (24U)
36412#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
36413#define USB_OTGSC_AVVIE_MASK (0x2000000U)
36414#define USB_OTGSC_AVVIE_SHIFT (25U)
36415#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
36416#define USB_OTGSC_ASVIE_MASK (0x4000000U)
36417#define USB_OTGSC_ASVIE_SHIFT (26U)
36418#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
36419#define USB_OTGSC_BSVIE_MASK (0x8000000U)
36420#define USB_OTGSC_BSVIE_SHIFT (27U)
36421#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
36422#define USB_OTGSC_BSEIE_MASK (0x10000000U)
36423#define USB_OTGSC_BSEIE_SHIFT (28U)
36424#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
36425#define USB_OTGSC_EN_1MS_MASK (0x20000000U)
36426#define USB_OTGSC_EN_1MS_SHIFT (29U)
36427#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
36428#define USB_OTGSC_DPIE_MASK (0x40000000U)
36429#define USB_OTGSC_DPIE_SHIFT (30U)
36430#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
36431/* @} */
36432
36433/* @name USBMODE - USB Device Mode */
36434/* @{ */
36435#define USB_USBMODE_CM_MASK (0x3U)
36436#define USB_USBMODE_CM_SHIFT (0U)
36437/* CM
36438 * 0b00..Idle [Default for combination host/device]
36439 * 0b01..Reserved
36440 * 0b10..Device Controller [Default for device only controller]
36441 * 0b11..Host Controller [Default for host only controller]
36442 */
36443#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
36444#define USB_USBMODE_ES_MASK (0x4U)
36445#define USB_USBMODE_ES_SHIFT (2U)
36446/* ES
36447 * 0b0..Little Endian [Default]
36448 * 0b1..Big Endian
36449 */
36450#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
36451#define USB_USBMODE_SLOM_MASK (0x8U)
36452#define USB_USBMODE_SLOM_SHIFT (3U)
36453/* SLOM
36454 * 0b0..Setup Lockouts On (default);
36455 * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .
36456 */
36457#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
36458#define USB_USBMODE_SDIS_MASK (0x10U)
36459#define USB_USBMODE_SDIS_SHIFT (4U)
36460#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
36461/* @} */
36462
36463/* @name ENDPTSETUPSTAT - Endpoint Setup Status */
36464/* @{ */
36465#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
36466#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
36467#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
36468/* @} */
36469
36470/* @name ENDPTPRIME - Endpoint Prime */
36471/* @{ */
36472#define USB_ENDPTPRIME_PERB_MASK (0xFFU)
36473#define USB_ENDPTPRIME_PERB_SHIFT (0U)
36474#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
36475#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
36476#define USB_ENDPTPRIME_PETB_SHIFT (16U)
36477#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
36478/* @} */
36479
36480/* @name ENDPTFLUSH - Endpoint Flush */
36481/* @{ */
36482#define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
36483#define USB_ENDPTFLUSH_FERB_SHIFT (0U)
36484#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
36485#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
36486#define USB_ENDPTFLUSH_FETB_SHIFT (16U)
36487#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
36488/* @} */
36489
36490/* @name ENDPTSTAT - Endpoint Status */
36491/* @{ */
36492#define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
36493#define USB_ENDPTSTAT_ERBR_SHIFT (0U)
36494#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
36495#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
36496#define USB_ENDPTSTAT_ETBR_SHIFT (16U)
36497#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
36498/* @} */
36499
36500/* @name ENDPTCOMPLETE - Endpoint Complete */
36501/* @{ */
36502#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
36503#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
36504#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
36505#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
36506#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
36507#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
36508/* @} */
36509
36510/* @name ENDPTCTRL0 - Endpoint Control0 */
36511/* @{ */
36512#define USB_ENDPTCTRL0_RXS_MASK (0x1U)
36513#define USB_ENDPTCTRL0_RXS_SHIFT (0U)
36514#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
36515#define USB_ENDPTCTRL0_RXT_MASK (0xCU)
36516#define USB_ENDPTCTRL0_RXT_SHIFT (2U)
36517#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
36518#define USB_ENDPTCTRL0_RXE_MASK (0x80U)
36519#define USB_ENDPTCTRL0_RXE_SHIFT (7U)
36520#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
36521#define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
36522#define USB_ENDPTCTRL0_TXS_SHIFT (16U)
36523#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
36524#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
36525#define USB_ENDPTCTRL0_TXT_SHIFT (18U)
36526#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
36527#define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
36528#define USB_ENDPTCTRL0_TXE_SHIFT (23U)
36529#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
36530/* @} */
36531
36532/* @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
36533/* @{ */
36534#define USB_ENDPTCTRL_RXS_MASK (0x1U)
36535#define USB_ENDPTCTRL_RXS_SHIFT (0U)
36536#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
36537#define USB_ENDPTCTRL_RXD_MASK (0x2U)
36538#define USB_ENDPTCTRL_RXD_SHIFT (1U)
36539#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
36540#define USB_ENDPTCTRL_RXT_MASK (0xCU)
36541#define USB_ENDPTCTRL_RXT_SHIFT (2U)
36542#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
36543#define USB_ENDPTCTRL_RXI_MASK (0x20U)
36544#define USB_ENDPTCTRL_RXI_SHIFT (5U)
36545#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
36546#define USB_ENDPTCTRL_RXR_MASK (0x40U)
36547#define USB_ENDPTCTRL_RXR_SHIFT (6U)
36548#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
36549#define USB_ENDPTCTRL_RXE_MASK (0x80U)
36550#define USB_ENDPTCTRL_RXE_SHIFT (7U)
36551#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
36552#define USB_ENDPTCTRL_TXS_MASK (0x10000U)
36553#define USB_ENDPTCTRL_TXS_SHIFT (16U)
36554#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
36555#define USB_ENDPTCTRL_TXD_MASK (0x20000U)
36556#define USB_ENDPTCTRL_TXD_SHIFT (17U)
36557#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
36558#define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
36559#define USB_ENDPTCTRL_TXT_SHIFT (18U)
36560#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
36561#define USB_ENDPTCTRL_TXI_MASK (0x200000U)
36562#define USB_ENDPTCTRL_TXI_SHIFT (21U)
36563#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
36564#define USB_ENDPTCTRL_TXR_MASK (0x400000U)
36565#define USB_ENDPTCTRL_TXR_SHIFT (22U)
36566#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
36567#define USB_ENDPTCTRL_TXE_MASK (0x800000U)
36568#define USB_ENDPTCTRL_TXE_SHIFT (23U)
36569#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
36570/* @} */
36571
36572/* The count of USB_ENDPTCTRL */
36573#define USB_ENDPTCTRL_COUNT (8U)
36574
36575
36576/*
36577 * @}
36578 */ /* end of group USB_Register_Masks */
36579
36580
36581/* USB - Peripheral instance base addresses */
36582/* Peripheral USB1 base address */
36583#define USB1_BASE (0x402E0000u)
36584/* Peripheral USB1 base pointer */
36585#define USB1 ((USB_Type *)USB1_BASE)
36586/* Peripheral USB2 base address */
36587#define USB2_BASE (0x402E0200u)
36588/* Peripheral USB2 base pointer */
36589#define USB2 ((USB_Type *)USB2_BASE)
36590/* Array initializer of USB peripheral base addresses */
36591#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE }
36592/* Array initializer of USB peripheral base pointers */
36593#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 }
36594/* Interrupt vectors for the USB peripheral type */
36595#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
36596/* Backward compatibility */
36597#define GPTIMER0CTL GPTIMER0CTRL
36598#define GPTIMER1CTL GPTIMER1CTRL
36599#define USB_SBUSCFG SBUSCFG
36600#define EPLISTADDR ENDPTLISTADDR
36601#define EPSETUPSR ENDPTSETUPSTAT
36602#define EPPRIME ENDPTPRIME
36603#define EPFLUSH ENDPTFLUSH
36604#define EPSR ENDPTSTAT
36605#define EPCOMPLETE ENDPTCOMPLETE
36606#define EPCR ENDPTCTRL
36607#define EPCR0 ENDPTCTRL0
36608#define USBHS_ID_ID_MASK USB_ID_ID_MASK
36609#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
36610#define USBHS_ID_ID(x) USB_ID_ID(x)
36611#define USBHS_ID_NID_MASK USB_ID_NID_MASK
36612#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
36613#define USBHS_ID_NID(x) USB_ID_NID(x)
36614#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
36615#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
36616#define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
36617#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
36618#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
36619#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
36620#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
36621#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
36622#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
36623#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
36624#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
36625#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
36626#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
36627#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
36628#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
36629#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
36630#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
36631#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
36632#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
36633#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
36634#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
36635#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
36636#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
36637#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
36638#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
36639#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
36640#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
36641#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
36642#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
36643#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
36644#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
36645#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
36646#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
36647#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
36648#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
36649#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
36650#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
36651#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
36652#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
36653#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
36654#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
36655#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
36656#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
36657#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
36658#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
36659#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
36660#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
36661#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
36662#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
36663#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
36664#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
36665#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
36666#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
36667#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
36668#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
36669#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
36670#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
36671#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
36672#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
36673#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
36674#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
36675#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
36676#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
36677#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
36678#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
36679#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
36680#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
36681#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
36682#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
36683#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
36684#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
36685#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
36686#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
36687#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
36688#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
36689#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
36690#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
36691#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
36692#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
36693#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
36694#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
36695#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
36696#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
36697#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
36698#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
36699#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
36700#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
36701#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
36702#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
36703#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
36704#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
36705#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
36706#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
36707#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
36708#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
36709#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
36710#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
36711#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
36712#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
36713#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
36714#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
36715#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
36716#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
36717#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
36718#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
36719#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
36720#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
36721#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
36722#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
36723#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
36724#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
36725#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
36726#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
36727#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
36728#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
36729#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
36730#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
36731#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
36732#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
36733#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
36734#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
36735#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
36736#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
36737#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
36738#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
36739#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
36740#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
36741#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
36742#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
36743#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
36744#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
36745#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
36746#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
36747#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
36748#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
36749#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
36750#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
36751#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
36752#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
36753#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
36754#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
36755#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
36756#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
36757#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
36758#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
36759#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
36760#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
36761#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
36762#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
36763#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
36764#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
36765#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
36766#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
36767#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
36768#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
36769#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
36770#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
36771#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
36772#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
36773#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
36774#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
36775#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
36776#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
36777#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
36778#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
36779#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
36780#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
36781#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
36782#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
36783#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
36784#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
36785#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
36786#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
36787#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
36788#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
36789#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
36790#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
36791#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
36792#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
36793#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
36794#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
36795#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
36796#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
36797#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
36798#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
36799#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
36800#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
36801#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
36802#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
36803#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
36804#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
36805#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
36806#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
36807#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
36808#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
36809#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
36810#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
36811#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
36812#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
36813#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
36814#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
36815#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
36816#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
36817#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
36818#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
36819#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
36820#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
36821#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
36822#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
36823#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
36824#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
36825#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
36826#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
36827#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
36828#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
36829#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
36830#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
36831#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
36832#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
36833#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
36834#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
36835#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
36836#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
36837#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
36838#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
36839#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
36840#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
36841#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
36842#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
36843#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
36844#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
36845#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
36846#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
36847#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
36848#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
36849#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
36850#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
36851#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
36852#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
36853#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
36854#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
36855#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
36856#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
36857#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
36858#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
36859#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
36860#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
36861#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
36862#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
36863#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
36864#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
36865#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
36866#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
36867#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
36868#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
36869#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
36870#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
36871#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
36872#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
36873#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
36874#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
36875#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
36876#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
36877#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
36878#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
36879#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
36880#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
36881#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
36882#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
36883#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
36884#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
36885#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
36886#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
36887#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
36888#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
36889#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
36890#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
36891#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
36892#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
36893#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
36894#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
36895#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
36896#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
36897#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
36898#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
36899#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
36900#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
36901#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
36902#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
36903#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
36904#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
36905#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
36906#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
36907#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
36908#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
36909#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
36910#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
36911#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
36912#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
36913#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
36914#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
36915#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
36916#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
36917#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
36918#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
36919#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
36920#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
36921#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
36922#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
36923#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
36924#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
36925#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
36926#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
36927#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
36928#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
36929#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
36930#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
36931#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
36932#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
36933#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
36934#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
36935#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
36936#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
36937#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
36938#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
36939#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
36940#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
36941#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
36942#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
36943#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
36944#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
36945#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
36946#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
36947#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
36948#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
36949#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
36950#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
36951#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
36952#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
36953#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
36954#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
36955#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
36956#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
36957#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
36958#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
36959#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
36960#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
36961#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
36962#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
36963#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
36964#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
36965#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
36966#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
36967#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
36968#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
36969#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
36970#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
36971#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
36972#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
36973#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
36974#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
36975#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
36976#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
36977#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
36978#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
36979#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
36980#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
36981#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
36982#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
36983#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
36984#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
36985#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
36986#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
36987#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
36988#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
36989#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
36990#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
36991#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
36992#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
36993#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
36994#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
36995#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
36996#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
36997#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
36998#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
36999#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
37000#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
37001#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
37002#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
37003#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
37004#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
37005#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
37006#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
37007#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
37008#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
37009#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
37010#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
37011#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
37012#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
37013#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
37014#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
37015#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
37016#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
37017#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
37018#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
37019#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
37020#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
37021#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
37022#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
37023#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
37024#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
37025#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
37026#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
37027#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
37028#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
37029#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
37030#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
37031#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
37032#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
37033#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
37034#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
37035#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
37036#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
37037#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
37038#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
37039#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
37040#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
37041#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
37042#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
37043#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
37044#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
37045#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
37046#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
37047#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
37048#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
37049#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
37050#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
37051#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
37052#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
37053#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
37054#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
37055#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
37056#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
37057#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
37058#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
37059#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
37060#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
37061#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
37062#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
37063#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
37064#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
37065#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
37066#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
37067#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
37068#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
37069#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
37070#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
37071#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
37072#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
37073#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
37074#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
37075#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
37076#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
37077#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
37078#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
37079#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
37080#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
37081#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
37082#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
37083#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
37084#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
37085#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
37086#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
37087#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
37088#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
37089#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
37090#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
37091#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
37092#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
37093#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
37094#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
37095#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
37096#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
37097#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
37098#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
37099#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
37100#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
37101#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
37102#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
37103#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
37104#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
37105#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
37106#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
37107#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
37108#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
37109#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
37110#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
37111#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
37112#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
37113#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
37114#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
37115#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
37116#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
37117#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
37118#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
37119#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
37120#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
37121#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
37122#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
37123#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
37124#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
37125#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
37126#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
37127#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
37128#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
37129#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
37130#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
37131#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
37132#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
37133#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
37134#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
37135#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
37136#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
37137#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
37138#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
37139#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
37140#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
37141#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
37142#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
37143#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
37144#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
37145#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
37146#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
37147#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
37148#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
37149#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
37150#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
37151#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
37152#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
37153#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
37154#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
37155#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
37156#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
37157#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
37158#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
37159#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
37160#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
37161#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
37162#define USBHS_Type USB_Type
37163#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE }
37164#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
37165#define USBHS_IRQHandler USB_OTG1_IRQHandler
37166
37167
37168/*
37169 * @}
37170 */ /* end of group USB_Peripheral_Access_Layer */
37171
37172
37173/* ----------------------------------------------------------------------------
37174 -- USBNC Peripheral Access Layer
37175 ---------------------------------------------------------------------------- */
37176
37177/*
37178 * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
37179 * @{
37180 */
37181
37182/* USBNC - Register Layout Typedef */
37183typedef struct {
37184 uint8_t RESERVED_0[2048];
37185 __IO uint32_t USB_OTGn_CTRL;
37186 uint8_t RESERVED_1[20];
37187 __IO uint32_t USB_OTGn_PHY_CTRL_0;
37188} USBNC_Type;
37189
37190/* ----------------------------------------------------------------------------
37191 -- USBNC Register Masks
37192 ---------------------------------------------------------------------------- */
37193
37194/*
37195 * @addtogroup USBNC_Register_Masks USBNC Register Masks
37196 * @{
37197 */
37198
37199/* @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */
37200/* @{ */
37201#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U)
37202#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U)
37203/* OVER_CUR_DIS
37204 * 0b1..Disables overcurrent detection
37205 * 0b0..Enables overcurrent detection
37206 */
37207#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK)
37208#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U)
37209#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U)
37210/* OVER_CUR_POL
37211 * 0b1..Low active (low on this signal represents an overcurrent condition)
37212 * 0b0..High active (high on this signal represents an overcurrent condition)
37213 */
37214#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK)
37215#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U)
37216#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U)
37217/* PWR_POL
37218 * 0b1..PMIC Power Pin is High active.
37219 * 0b0..PMIC Power Pin is Low active.
37220 */
37221#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK)
37222#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U)
37223#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U)
37224/* WIE
37225 * 0b1..Interrupt Enabled
37226 * 0b0..Interrupt Disabled
37227 */
37228#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK)
37229#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U)
37230#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U)
37231/* WKUP_SW_EN
37232 * 0b1..Enable
37233 * 0b0..Disable
37234 */
37235#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK)
37236#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U)
37237#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U)
37238/* WKUP_SW
37239 * 0b1..Force wake-up
37240 * 0b0..Inactive
37241 */
37242#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK)
37243#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U)
37244#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U)
37245/* WKUP_ID_EN
37246 * 0b1..Enable
37247 * 0b0..Disable
37248 */
37249#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK)
37250#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U)
37251#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U)
37252/* WKUP_VBUS_EN
37253 * 0b1..Enable
37254 * 0b0..Disable
37255 */
37256#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK)
37257#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U)
37258#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U)
37259/* WKUP_DPDM_EN
37260 * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
37261 * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
37262 */
37263#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK)
37264#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U)
37265#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U)
37266/* WIR
37267 * 0b1..Wake-up Interrupt Request received
37268 * 0b0..No wake-up interrupt request received
37269 */
37270#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK)
37271/* @} */
37272
37273/* @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */
37274/* @{ */
37275#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U)
37276#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U)
37277/* UTMI_CLK_VLD
37278 * 0b1..Valid
37279 * 0b0..Invalid
37280 */
37281#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK)
37282/* @} */
37283
37284
37285/*
37286 * @}
37287 */ /* end of group USBNC_Register_Masks */
37288
37289
37290/* USBNC - Peripheral instance base addresses */
37291/* Peripheral USBNC1 base address */
37292#define USBNC1_BASE (0x402E0000u)
37293/* Peripheral USBNC1 base pointer */
37294#define USBNC1 ((USBNC_Type *)USBNC1_BASE)
37295/* Peripheral USBNC2 base address */
37296#define USBNC2_BASE (0x402E0004u)
37297/* Peripheral USBNC2 base pointer */
37298#define USBNC2 ((USBNC_Type *)USBNC2_BASE)
37299/* Array initializer of USBNC peripheral base addresses */
37300#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE }
37301/* Array initializer of USBNC peripheral base pointers */
37302#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 }
37303
37304/*
37305 * @}
37306 */ /* end of group USBNC_Peripheral_Access_Layer */
37307
37308
37309/* ----------------------------------------------------------------------------
37310 -- USBPHY Peripheral Access Layer
37311 ---------------------------------------------------------------------------- */
37312
37313/*
37314 * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
37315 * @{
37316 */
37317
37318/* USBPHY - Register Layout Typedef */
37319typedef struct {
37320 __IO uint32_t PWD;
37321 __IO uint32_t PWD_SET;
37322 __IO uint32_t PWD_CLR;
37323 __IO uint32_t PWD_TOG;
37324 __IO uint32_t TX;
37325 __IO uint32_t TX_SET;
37326 __IO uint32_t TX_CLR;
37327 __IO uint32_t TX_TOG;
37328 __IO uint32_t RX;
37329 __IO uint32_t RX_SET;
37330 __IO uint32_t RX_CLR;
37331 __IO uint32_t RX_TOG;
37332 __IO uint32_t CTRL;
37333 __IO uint32_t CTRL_SET;
37334 __IO uint32_t CTRL_CLR;
37335 __IO uint32_t CTRL_TOG;
37336 __IO uint32_t STATUS;
37337 uint8_t RESERVED_0[12];
37338 __IO uint32_t DEBUGr;
37339 __IO uint32_t DEBUG_SET;
37340 __IO uint32_t DEBUG_CLR;
37341 __IO uint32_t DEBUG_TOG;
37342 __I uint32_t DEBUG0_STATUS;
37343 uint8_t RESERVED_1[12];
37344 __IO uint32_t DEBUG1;
37345 __IO uint32_t DEBUG1_SET;
37346 __IO uint32_t DEBUG1_CLR;
37347 __IO uint32_t DEBUG1_TOG;
37348 __I uint32_t VERSION;
37349} USBPHY_Type;
37350
37351/* ----------------------------------------------------------------------------
37352 -- USBPHY Register Masks
37353 ---------------------------------------------------------------------------- */
37354
37355/*
37356 * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
37357 * @{
37358 */
37359
37360/* @name PWD - USB PHY Power-Down Register */
37361/* @{ */
37362#define USBPHY_PWD_RSVD0_MASK (0x3FFU)
37363#define USBPHY_PWD_RSVD0_SHIFT (0U)
37364#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK)
37365#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
37366#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
37367#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
37368#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
37369#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
37370#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
37371#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
37372#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
37373#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
37374#define USBPHY_PWD_RSVD1_MASK (0x1E000U)
37375#define USBPHY_PWD_RSVD1_SHIFT (13U)
37376#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK)
37377#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
37378#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
37379#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
37380#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
37381#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
37382#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
37383#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
37384#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
37385#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
37386#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
37387#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
37388#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
37389#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U)
37390#define USBPHY_PWD_RSVD2_SHIFT (21U)
37391#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK)
37392/* @} */
37393
37394/* @name PWD_SET - USB PHY Power-Down Register */
37395/* @{ */
37396#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU)
37397#define USBPHY_PWD_SET_RSVD0_SHIFT (0U)
37398#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK)
37399#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
37400#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
37401#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
37402#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
37403#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
37404#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
37405#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
37406#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
37407#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
37408#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U)
37409#define USBPHY_PWD_SET_RSVD1_SHIFT (13U)
37410#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK)
37411#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
37412#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
37413#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
37414#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
37415#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
37416#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
37417#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
37418#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
37419#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
37420#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
37421#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
37422#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
37423#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U)
37424#define USBPHY_PWD_SET_RSVD2_SHIFT (21U)
37425#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK)
37426/* @} */
37427
37428/* @name PWD_CLR - USB PHY Power-Down Register */
37429/* @{ */
37430#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU)
37431#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U)
37432#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK)
37433#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
37434#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
37435#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
37436#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
37437#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
37438#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
37439#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
37440#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
37441#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
37442#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U)
37443#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U)
37444#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK)
37445#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
37446#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
37447#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
37448#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
37449#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
37450#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
37451#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
37452#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
37453#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
37454#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
37455#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
37456#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
37457#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U)
37458#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U)
37459#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK)
37460/* @} */
37461
37462/* @name PWD_TOG - USB PHY Power-Down Register */
37463/* @{ */
37464#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU)
37465#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U)
37466#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK)
37467#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
37468#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
37469#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
37470#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
37471#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
37472#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
37473#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
37474#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
37475#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
37476#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U)
37477#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U)
37478#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK)
37479#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
37480#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
37481#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
37482#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
37483#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
37484#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
37485#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
37486#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
37487#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
37488#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
37489#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
37490#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
37491#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U)
37492#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U)
37493#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK)
37494/* @} */
37495
37496/* @name TX - USB PHY Transmitter Control Register */
37497/* @{ */
37498#define USBPHY_TX_D_CAL_MASK (0xFU)
37499#define USBPHY_TX_D_CAL_SHIFT (0U)
37500#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
37501#define USBPHY_TX_RSVD0_MASK (0xF0U)
37502#define USBPHY_TX_RSVD0_SHIFT (4U)
37503#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK)
37504#define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
37505#define USBPHY_TX_TXCAL45DN_SHIFT (8U)
37506#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
37507#define USBPHY_TX_RSVD1_MASK (0xF000U)
37508#define USBPHY_TX_RSVD1_SHIFT (12U)
37509#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK)
37510#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
37511#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
37512#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
37513#define USBPHY_TX_RSVD2_MASK (0x3F00000U)
37514#define USBPHY_TX_RSVD2_SHIFT (20U)
37515#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK)
37516#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
37517#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
37518#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
37519#define USBPHY_TX_RSVD5_MASK (0xE0000000U)
37520#define USBPHY_TX_RSVD5_SHIFT (29U)
37521#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK)
37522/* @} */
37523
37524/* @name TX_SET - USB PHY Transmitter Control Register */
37525/* @{ */
37526#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
37527#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
37528#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
37529#define USBPHY_TX_SET_RSVD0_MASK (0xF0U)
37530#define USBPHY_TX_SET_RSVD0_SHIFT (4U)
37531#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK)
37532#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
37533#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
37534#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
37535#define USBPHY_TX_SET_RSVD1_MASK (0xF000U)
37536#define USBPHY_TX_SET_RSVD1_SHIFT (12U)
37537#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK)
37538#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
37539#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
37540#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
37541#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U)
37542#define USBPHY_TX_SET_RSVD2_SHIFT (20U)
37543#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK)
37544#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
37545#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
37546#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
37547#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U)
37548#define USBPHY_TX_SET_RSVD5_SHIFT (29U)
37549#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK)
37550/* @} */
37551
37552/* @name TX_CLR - USB PHY Transmitter Control Register */
37553/* @{ */
37554#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
37555#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
37556#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
37557#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U)
37558#define USBPHY_TX_CLR_RSVD0_SHIFT (4U)
37559#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK)
37560#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
37561#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
37562#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
37563#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U)
37564#define USBPHY_TX_CLR_RSVD1_SHIFT (12U)
37565#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK)
37566#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
37567#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
37568#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
37569#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U)
37570#define USBPHY_TX_CLR_RSVD2_SHIFT (20U)
37571#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK)
37572#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
37573#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
37574#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
37575#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U)
37576#define USBPHY_TX_CLR_RSVD5_SHIFT (29U)
37577#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK)
37578/* @} */
37579
37580/* @name TX_TOG - USB PHY Transmitter Control Register */
37581/* @{ */
37582#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
37583#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
37584#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
37585#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U)
37586#define USBPHY_TX_TOG_RSVD0_SHIFT (4U)
37587#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK)
37588#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
37589#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
37590#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
37591#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U)
37592#define USBPHY_TX_TOG_RSVD1_SHIFT (12U)
37593#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK)
37594#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
37595#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
37596#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
37597#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U)
37598#define USBPHY_TX_TOG_RSVD2_SHIFT (20U)
37599#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK)
37600#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
37601#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
37602#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
37603#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U)
37604#define USBPHY_TX_TOG_RSVD5_SHIFT (29U)
37605#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK)
37606/* @} */
37607
37608/* @name RX - USB PHY Receiver Control Register */
37609/* @{ */
37610#define USBPHY_RX_ENVADJ_MASK (0x7U)
37611#define USBPHY_RX_ENVADJ_SHIFT (0U)
37612#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
37613#define USBPHY_RX_RSVD0_MASK (0x8U)
37614#define USBPHY_RX_RSVD0_SHIFT (3U)
37615#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK)
37616#define USBPHY_RX_DISCONADJ_MASK (0x70U)
37617#define USBPHY_RX_DISCONADJ_SHIFT (4U)
37618#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
37619#define USBPHY_RX_RSVD1_MASK (0x3FFF80U)
37620#define USBPHY_RX_RSVD1_SHIFT (7U)
37621#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK)
37622#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
37623#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
37624#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
37625#define USBPHY_RX_RSVD2_MASK (0xFF800000U)
37626#define USBPHY_RX_RSVD2_SHIFT (23U)
37627#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK)
37628/* @} */
37629
37630/* @name RX_SET - USB PHY Receiver Control Register */
37631/* @{ */
37632#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
37633#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
37634#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
37635#define USBPHY_RX_SET_RSVD0_MASK (0x8U)
37636#define USBPHY_RX_SET_RSVD0_SHIFT (3U)
37637#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK)
37638#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
37639#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
37640#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
37641#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U)
37642#define USBPHY_RX_SET_RSVD1_SHIFT (7U)
37643#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK)
37644#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
37645#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
37646#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
37647#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U)
37648#define USBPHY_RX_SET_RSVD2_SHIFT (23U)
37649#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK)
37650/* @} */
37651
37652/* @name RX_CLR - USB PHY Receiver Control Register */
37653/* @{ */
37654#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
37655#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
37656#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
37657#define USBPHY_RX_CLR_RSVD0_MASK (0x8U)
37658#define USBPHY_RX_CLR_RSVD0_SHIFT (3U)
37659#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK)
37660#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
37661#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
37662#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
37663#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U)
37664#define USBPHY_RX_CLR_RSVD1_SHIFT (7U)
37665#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK)
37666#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
37667#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
37668#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
37669#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U)
37670#define USBPHY_RX_CLR_RSVD2_SHIFT (23U)
37671#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK)
37672/* @} */
37673
37674/* @name RX_TOG - USB PHY Receiver Control Register */
37675/* @{ */
37676#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
37677#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
37678#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
37679#define USBPHY_RX_TOG_RSVD0_MASK (0x8U)
37680#define USBPHY_RX_TOG_RSVD0_SHIFT (3U)
37681#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK)
37682#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
37683#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
37684#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
37685#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U)
37686#define USBPHY_RX_TOG_RSVD1_SHIFT (7U)
37687#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK)
37688#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
37689#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
37690#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
37691#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U)
37692#define USBPHY_RX_TOG_RSVD2_SHIFT (23U)
37693#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK)
37694/* @} */
37695
37696/* @name CTRL - USB PHY General Control Register */
37697/* @{ */
37698#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
37699#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
37700#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
37701#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
37702#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
37703#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
37704#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
37705#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
37706#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
37707#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
37708#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
37709#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
37710#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
37711#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
37712#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
37713#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
37714#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
37715#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
37716#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
37717#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
37718#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
37719#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
37720#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
37721#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
37722#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
37723#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
37724#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
37725#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
37726#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
37727#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
37728#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
37729#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
37730#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
37731#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
37732#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
37733#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
37734#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
37735#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
37736#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
37737#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)
37738#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)
37739#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)
37740#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
37741#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
37742#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
37743#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
37744#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
37745#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
37746#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
37747#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
37748#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
37749#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
37750#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
37751#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
37752#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U)
37753#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U)
37754#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK)
37755#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
37756#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
37757#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
37758#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
37759#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
37760#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
37761#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
37762#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
37763#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
37764#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
37765#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
37766#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
37767#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
37768#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
37769#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
37770#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
37771#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
37772#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
37773#define USBPHY_CTRL_RSVD1_MASK (0x6000000U)
37774#define USBPHY_CTRL_RSVD1_SHIFT (25U)
37775#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK)
37776#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
37777#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
37778#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
37779#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
37780#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
37781#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
37782#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
37783#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
37784#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
37785#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
37786#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
37787#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
37788#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
37789#define USBPHY_CTRL_SFTRST_SHIFT (31U)
37790#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
37791/* @} */
37792
37793/* @name CTRL_SET - USB PHY General Control Register */
37794/* @{ */
37795#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
37796#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
37797#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
37798#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
37799#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
37800#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
37801#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
37802#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
37803#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
37804#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
37805#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
37806#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
37807#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
37808#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
37809#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
37810#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
37811#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
37812#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
37813#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
37814#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
37815#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
37816#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
37817#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
37818#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
37819#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
37820#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
37821#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
37822#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
37823#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
37824#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
37825#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
37826#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
37827#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
37828#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
37829#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
37830#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
37831#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
37832#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
37833#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
37834#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U)
37835#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U)
37836#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK)
37837#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
37838#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
37839#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
37840#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
37841#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
37842#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
37843#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
37844#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
37845#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
37846#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
37847#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
37848#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
37849#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U)
37850#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U)
37851#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK)
37852#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
37853#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
37854#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
37855#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
37856#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
37857#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
37858#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
37859#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
37860#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
37861#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
37862#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
37863#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
37864#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
37865#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
37866#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
37867#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
37868#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
37869#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
37870#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U)
37871#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U)
37872#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK)
37873#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
37874#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
37875#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
37876#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
37877#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
37878#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
37879#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
37880#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
37881#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
37882#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
37883#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
37884#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
37885#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
37886#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
37887#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
37888/* @} */
37889
37890/* @name CTRL_CLR - USB PHY General Control Register */
37891/* @{ */
37892#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
37893#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
37894#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
37895#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
37896#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
37897#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
37898#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
37899#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
37900#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
37901#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
37902#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
37903#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
37904#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
37905#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
37906#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
37907#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
37908#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
37909#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
37910#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
37911#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
37912#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
37913#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
37914#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
37915#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
37916#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
37917#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
37918#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
37919#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
37920#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
37921#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
37922#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
37923#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
37924#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
37925#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
37926#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
37927#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
37928#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
37929#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
37930#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
37931#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U)
37932#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U)
37933#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK)
37934#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
37935#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
37936#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
37937#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
37938#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
37939#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
37940#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
37941#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
37942#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
37943#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
37944#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
37945#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
37946#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U)
37947#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U)
37948#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK)
37949#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
37950#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
37951#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
37952#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
37953#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
37954#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
37955#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
37956#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
37957#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
37958#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
37959#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
37960#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
37961#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
37962#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
37963#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
37964#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
37965#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
37966#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
37967#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U)
37968#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U)
37969#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK)
37970#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
37971#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
37972#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
37973#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
37974#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
37975#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
37976#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
37977#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
37978#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
37979#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
37980#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
37981#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
37982#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
37983#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
37984#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
37985/* @} */
37986
37987/* @name CTRL_TOG - USB PHY General Control Register */
37988/* @{ */
37989#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
37990#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
37991#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
37992#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
37993#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
37994#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
37995#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
37996#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
37997#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
37998#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
37999#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
38000#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
38001#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
38002#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
38003#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
38004#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
38005#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
38006#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
38007#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
38008#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
38009#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
38010#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
38011#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
38012#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
38013#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
38014#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
38015#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
38016#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
38017#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
38018#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
38019#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
38020#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
38021#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
38022#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
38023#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
38024#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
38025#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
38026#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
38027#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
38028#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U)
38029#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U)
38030#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK)
38031#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
38032#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
38033#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
38034#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
38035#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
38036#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
38037#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
38038#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
38039#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
38040#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
38041#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
38042#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
38043#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U)
38044#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U)
38045#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK)
38046#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
38047#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
38048#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
38049#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
38050#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
38051#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
38052#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
38053#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
38054#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
38055#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
38056#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
38057#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
38058#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
38059#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
38060#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
38061#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
38062#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
38063#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
38064#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U)
38065#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U)
38066#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK)
38067#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
38068#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
38069#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
38070#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
38071#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
38072#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
38073#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
38074#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
38075#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
38076#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
38077#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
38078#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
38079#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
38080#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
38081#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
38082/* @} */
38083
38084/* @name STATUS - USB PHY Status Register */
38085/* @{ */
38086#define USBPHY_STATUS_RSVD0_MASK (0x7U)
38087#define USBPHY_STATUS_RSVD0_SHIFT (0U)
38088#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK)
38089#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
38090#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
38091#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
38092#define USBPHY_STATUS_RSVD1_MASK (0x30U)
38093#define USBPHY_STATUS_RSVD1_SHIFT (4U)
38094#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK)
38095#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
38096#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
38097#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
38098#define USBPHY_STATUS_RSVD2_MASK (0x80U)
38099#define USBPHY_STATUS_RSVD2_SHIFT (7U)
38100#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK)
38101#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
38102#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
38103#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
38104#define USBPHY_STATUS_RSVD3_MASK (0x200U)
38105#define USBPHY_STATUS_RSVD3_SHIFT (9U)
38106#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK)
38107#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
38108#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
38109#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
38110#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U)
38111#define USBPHY_STATUS_RSVD4_SHIFT (11U)
38112#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK)
38113/* @} */
38114
38115/* @name DEBUG - USB PHY Debug Register */
38116/* @{ */
38117#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
38118#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
38119#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
38120#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
38121#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
38122#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
38123#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
38124#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
38125#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
38126#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
38127#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
38128#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
38129#define USBPHY_DEBUG_RSVD0_MASK (0xC0U)
38130#define USBPHY_DEBUG_RSVD0_SHIFT (6U)
38131#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
38132#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
38133#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
38134#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
38135#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
38136#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
38137#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
38138#define USBPHY_DEBUG_RSVD1_MASK (0xE000U)
38139#define USBPHY_DEBUG_RSVD1_SHIFT (13U)
38140#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK)
38141#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
38142#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
38143#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
38144#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U)
38145#define USBPHY_DEBUG_RSVD2_SHIFT (21U)
38146#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK)
38147#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
38148#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
38149#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
38150#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
38151#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
38152#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
38153#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
38154#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
38155#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
38156#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
38157#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
38158#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
38159#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U)
38160#define USBPHY_DEBUG_RSVD3_SHIFT (31U)
38161#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK)
38162/* @} */
38163
38164/* @name DEBUG_SET - USB PHY Debug Register */
38165/* @{ */
38166#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
38167#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
38168#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
38169#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
38170#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
38171#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
38172#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
38173#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
38174#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
38175#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
38176#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
38177#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
38178#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U)
38179#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U)
38180#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK)
38181#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
38182#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
38183#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
38184#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
38185#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
38186#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
38187#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U)
38188#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U)
38189#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK)
38190#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
38191#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
38192#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
38193#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U)
38194#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U)
38195#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK)
38196#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
38197#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
38198#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
38199#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
38200#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
38201#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
38202#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
38203#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
38204#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
38205#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
38206#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
38207#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
38208#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U)
38209#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U)
38210#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK)
38211/* @} */
38212
38213/* @name DEBUG_CLR - USB PHY Debug Register */
38214/* @{ */
38215#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
38216#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
38217#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
38218#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
38219#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
38220#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
38221#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
38222#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
38223#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
38224#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
38225#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
38226#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
38227#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U)
38228#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U)
38229#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK)
38230#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
38231#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
38232#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
38233#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
38234#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
38235#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
38236#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U)
38237#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U)
38238#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK)
38239#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
38240#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
38241#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
38242#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U)
38243#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U)
38244#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK)
38245#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
38246#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
38247#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
38248#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
38249#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
38250#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
38251#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
38252#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
38253#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
38254#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
38255#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
38256#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
38257#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U)
38258#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U)
38259#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK)
38260/* @} */
38261
38262/* @name DEBUG_TOG - USB PHY Debug Register */
38263/* @{ */
38264#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
38265#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
38266#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
38267#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
38268#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
38269#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
38270#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
38271#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
38272#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
38273#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
38274#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
38275#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
38276#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U)
38277#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U)
38278#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK)
38279#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
38280#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
38281#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
38282#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
38283#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
38284#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
38285#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U)
38286#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U)
38287#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK)
38288#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
38289#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
38290#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
38291#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U)
38292#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U)
38293#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK)
38294#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
38295#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
38296#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
38297#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
38298#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
38299#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
38300#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
38301#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
38302#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
38303#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
38304#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
38305#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
38306#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U)
38307#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U)
38308#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK)
38309/* @} */
38310
38311/* @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
38312/* @{ */
38313#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
38314#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
38315#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
38316#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
38317#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
38318#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
38319#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
38320#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
38321#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
38322/* @} */
38323
38324/* @name DEBUG1 - UTMI Debug Status Register 1 */
38325/* @{ */
38326#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU)
38327#define USBPHY_DEBUG1_RSVD0_SHIFT (0U)
38328#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK)
38329#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
38330#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
38331#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
38332#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U)
38333#define USBPHY_DEBUG1_RSVD1_SHIFT (15U)
38334#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK)
38335/* @} */
38336
38337/* @name DEBUG1_SET - UTMI Debug Status Register 1 */
38338/* @{ */
38339#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU)
38340#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U)
38341#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK)
38342#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
38343#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
38344#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
38345#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U)
38346#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U)
38347#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK)
38348/* @} */
38349
38350/* @name DEBUG1_CLR - UTMI Debug Status Register 1 */
38351/* @{ */
38352#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU)
38353#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U)
38354#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK)
38355#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
38356#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
38357#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
38358#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U)
38359#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U)
38360#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK)
38361/* @} */
38362
38363/* @name DEBUG1_TOG - UTMI Debug Status Register 1 */
38364/* @{ */
38365#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU)
38366#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U)
38367#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK)
38368#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
38369#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
38370#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
38371#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U)
38372#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U)
38373#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK)
38374/* @} */
38375
38376/* @name VERSION - UTMI RTL Version */
38377/* @{ */
38378#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
38379#define USBPHY_VERSION_STEP_SHIFT (0U)
38380#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
38381#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
38382#define USBPHY_VERSION_MINOR_SHIFT (16U)
38383#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
38384#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
38385#define USBPHY_VERSION_MAJOR_SHIFT (24U)
38386#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
38387/* @} */
38388
38389
38390/*
38391 * @}
38392 */ /* end of group USBPHY_Register_Masks */
38393
38394
38395/* USBPHY - Peripheral instance base addresses */
38396/* Peripheral USBPHY1 base address */
38397#define USBPHY1_BASE (0x400D9000u)
38398/* Peripheral USBPHY1 base pointer */
38399#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
38400/* Peripheral USBPHY2 base address */
38401#define USBPHY2_BASE (0x400DA000u)
38402/* Peripheral USBPHY2 base pointer */
38403#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
38404/* Array initializer of USBPHY peripheral base addresses */
38405#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
38406/* Array initializer of USBPHY peripheral base pointers */
38407#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
38408/* Interrupt vectors for the USBPHY peripheral type */
38409#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
38410/* Backward compatibility */
38411#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
38412#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
38413#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
38414#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
38415#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
38416#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
38417
38418
38419/*
38420 * @}
38421 */ /* end of group USBPHY_Peripheral_Access_Layer */
38422
38423
38424/* ----------------------------------------------------------------------------
38425 -- USB_ANALOG Peripheral Access Layer
38426 ---------------------------------------------------------------------------- */
38427
38428/*
38429 * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer
38430 * @{
38431 */
38432
38433/* USB_ANALOG - Register Layout Typedef */
38434typedef struct {
38435 uint8_t RESERVED_0[416];
38436 struct { /* offset: 0x1A0, array step: 0x60 */
38437 __IO uint32_t VBUS_DETECT;
38438 __IO uint32_t VBUS_DETECT_SET;
38439 __IO uint32_t VBUS_DETECT_CLR;
38440 __IO uint32_t VBUS_DETECT_TOG;
38441 __IO uint32_t CHRG_DETECT;
38442 __IO uint32_t CHRG_DETECT_SET;
38443 __IO uint32_t CHRG_DETECT_CLR;
38444 __IO uint32_t CHRG_DETECT_TOG;
38445 __I uint32_t VBUS_DETECT_STAT;
38446 uint8_t RESERVED_0[12];
38447 __I uint32_t CHRG_DETECT_STAT;
38448 uint8_t RESERVED_1[28];
38449 __IO uint32_t MISC;
38450 __IO uint32_t MISC_SET;
38451 __IO uint32_t MISC_CLR;
38452 __IO uint32_t MISC_TOG;
38453 } INSTANCE[2];
38454 __I uint32_t DIGPROG;
38455} USB_ANALOG_Type;
38456
38457/* ----------------------------------------------------------------------------
38458 -- USB_ANALOG Register Masks
38459 ---------------------------------------------------------------------------- */
38460
38461/*
38462 * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks
38463 * @{
38464 */
38465
38466/* @name VBUS_DETECT - USB VBUS Detect Register */
38467/* @{ */
38468#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
38469#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
38470/* VBUSVALID_THRESH
38471 * 0b000..4.0V
38472 * 0b001..4.1V
38473 * 0b010..4.2V
38474 * 0b011..4.3V
38475 * 0b100..4.4V (default)
38476 * 0b101..4.5V
38477 * 0b110..4.6V
38478 * 0b111..4.7V
38479 */
38480#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK)
38481#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
38482#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
38483#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK)
38484#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
38485#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
38486#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK)
38487#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U)
38488#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U)
38489#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK)
38490/* @} */
38491
38492/* The count of USB_ANALOG_VBUS_DETECT */
38493#define USB_ANALOG_VBUS_DETECT_COUNT (2U)
38494
38495/* @name VBUS_DETECT_SET - USB VBUS Detect Register */
38496/* @{ */
38497#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
38498#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
38499/* VBUSVALID_THRESH
38500 * 0b000..4.0V
38501 * 0b001..4.1V
38502 * 0b010..4.2V
38503 * 0b011..4.3V
38504 * 0b100..4.4V (default)
38505 * 0b101..4.5V
38506 * 0b110..4.6V
38507 * 0b111..4.7V
38508 */
38509#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
38510#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
38511#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
38512#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK)
38513#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
38514#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
38515#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
38516#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U)
38517#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U)
38518#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK)
38519/* @} */
38520
38521/* The count of USB_ANALOG_VBUS_DETECT_SET */
38522#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U)
38523
38524/* @name VBUS_DETECT_CLR - USB VBUS Detect Register */
38525/* @{ */
38526#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
38527#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
38528/* VBUSVALID_THRESH
38529 * 0b000..4.0V
38530 * 0b001..4.1V
38531 * 0b010..4.2V
38532 * 0b011..4.3V
38533 * 0b100..4.4V (default)
38534 * 0b101..4.5V
38535 * 0b110..4.6V
38536 * 0b111..4.7V
38537 */
38538#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
38539#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
38540#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
38541#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK)
38542#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
38543#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
38544#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
38545#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U)
38546#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U)
38547#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK)
38548/* @} */
38549
38550/* The count of USB_ANALOG_VBUS_DETECT_CLR */
38551#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U)
38552
38553/* @name VBUS_DETECT_TOG - USB VBUS Detect Register */
38554/* @{ */
38555#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
38556#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
38557/* VBUSVALID_THRESH
38558 * 0b000..4.0V
38559 * 0b001..4.1V
38560 * 0b010..4.2V
38561 * 0b011..4.3V
38562 * 0b100..4.4V (default)
38563 * 0b101..4.5V
38564 * 0b110..4.6V
38565 * 0b111..4.7V
38566 */
38567#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
38568#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U)
38569#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U)
38570#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK)
38571#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
38572#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
38573#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
38574#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U)
38575#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U)
38576#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK)
38577/* @} */
38578
38579/* The count of USB_ANALOG_VBUS_DETECT_TOG */
38580#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U)
38581
38582/* @name CHRG_DETECT - USB Charger Detect Register */
38583/* @{ */
38584#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U)
38585#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U)
38586/* CHK_CONTACT - Check the contact of USB plug
38587 * 0b0..Do not check the contact of USB plug.
38588 * 0b1..Check whether the USB plug has been in contact with each other
38589 */
38590#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK)
38591#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U)
38592#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U)
38593/* CHK_CHRG_B - Check the charger connection
38594 * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
38595 * 0b1..Do not check whether a charger is connected to the USB port.
38596 */
38597#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK)
38598#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U)
38599#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U)
38600/* EN_B
38601 * 0b0..Enable the charger detector.
38602 * 0b1..Disable the charger detector.
38603 */
38604#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK)
38605/* @} */
38606
38607/* The count of USB_ANALOG_CHRG_DETECT */
38608#define USB_ANALOG_CHRG_DETECT_COUNT (2U)
38609
38610/* @name CHRG_DETECT_SET - USB Charger Detect Register */
38611/* @{ */
38612#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U)
38613#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U)
38614/* CHK_CONTACT - Check the contact of USB plug
38615 * 0b0..Do not check the contact of USB plug.
38616 * 0b1..Check whether the USB plug has been in contact with each other
38617 */
38618#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK)
38619#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U)
38620#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U)
38621/* CHK_CHRG_B - Check the charger connection
38622 * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
38623 * 0b1..Do not check whether a charger is connected to the USB port.
38624 */
38625#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK)
38626#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U)
38627#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U)
38628/* EN_B
38629 * 0b0..Enable the charger detector.
38630 * 0b1..Disable the charger detector.
38631 */
38632#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK)
38633/* @} */
38634
38635/* The count of USB_ANALOG_CHRG_DETECT_SET */
38636#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U)
38637
38638/* @name CHRG_DETECT_CLR - USB Charger Detect Register */
38639/* @{ */
38640#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U)
38641#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U)
38642/* CHK_CONTACT - Check the contact of USB plug
38643 * 0b0..Do not check the contact of USB plug.
38644 * 0b1..Check whether the USB plug has been in contact with each other
38645 */
38646#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK)
38647#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U)
38648#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U)
38649/* CHK_CHRG_B - Check the charger connection
38650 * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
38651 * 0b1..Do not check whether a charger is connected to the USB port.
38652 */
38653#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK)
38654#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U)
38655#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U)
38656/* EN_B
38657 * 0b0..Enable the charger detector.
38658 * 0b1..Disable the charger detector.
38659 */
38660#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK)
38661/* @} */
38662
38663/* The count of USB_ANALOG_CHRG_DETECT_CLR */
38664#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U)
38665
38666/* @name CHRG_DETECT_TOG - USB Charger Detect Register */
38667/* @{ */
38668#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U)
38669#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U)
38670/* CHK_CONTACT - Check the contact of USB plug
38671 * 0b0..Do not check the contact of USB plug.
38672 * 0b1..Check whether the USB plug has been in contact with each other
38673 */
38674#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK)
38675#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U)
38676#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U)
38677/* CHK_CHRG_B - Check the charger connection
38678 * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port.
38679 * 0b1..Do not check whether a charger is connected to the USB port.
38680 */
38681#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK)
38682#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U)
38683#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U)
38684/* EN_B
38685 * 0b0..Enable the charger detector.
38686 * 0b1..Disable the charger detector.
38687 */
38688#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK)
38689/* @} */
38690
38691/* The count of USB_ANALOG_CHRG_DETECT_TOG */
38692#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U)
38693
38694/* @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */
38695/* @{ */
38696#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U)
38697#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U)
38698#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK)
38699#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U)
38700#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U)
38701#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK)
38702#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U)
38703#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U)
38704#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK)
38705#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U)
38706#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U)
38707#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK)
38708/* @} */
38709
38710/* The count of USB_ANALOG_VBUS_DETECT_STAT */
38711#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U)
38712
38713/* @name CHRG_DETECT_STAT - USB Charger Detect Status Register */
38714/* @{ */
38715#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U)
38716#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U)
38717/* PLUG_CONTACT
38718 * 0b0..The USB plug has not made contact.
38719 * 0b1..The USB plug has made good contact.
38720 */
38721#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK)
38722#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U)
38723#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U)
38724/* CHRG_DETECTED
38725 * 0b0..The USB port is not connected to a charger.
38726 * 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port.
38727 */
38728#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK)
38729#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U)
38730#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U)
38731#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK)
38732#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U)
38733#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U)
38734#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK)
38735/* @} */
38736
38737/* The count of USB_ANALOG_CHRG_DETECT_STAT */
38738#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U)
38739
38740/* @name MISC - USB Misc Register */
38741/* @{ */
38742#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U)
38743#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U)
38744#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK)
38745#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U)
38746#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U)
38747#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK)
38748#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U)
38749#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U)
38750#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK)
38751/* @} */
38752
38753/* The count of USB_ANALOG_MISC */
38754#define USB_ANALOG_MISC_COUNT (2U)
38755
38756/* @name MISC_SET - USB Misc Register */
38757/* @{ */
38758#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U)
38759#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U)
38760#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK)
38761#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U)
38762#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U)
38763#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK)
38764#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U)
38765#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U)
38766#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK)
38767/* @} */
38768
38769/* The count of USB_ANALOG_MISC_SET */
38770#define USB_ANALOG_MISC_SET_COUNT (2U)
38771
38772/* @name MISC_CLR - USB Misc Register */
38773/* @{ */
38774#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U)
38775#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U)
38776#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK)
38777#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U)
38778#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U)
38779#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK)
38780#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U)
38781#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U)
38782#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK)
38783/* @} */
38784
38785/* The count of USB_ANALOG_MISC_CLR */
38786#define USB_ANALOG_MISC_CLR_COUNT (2U)
38787
38788/* @name MISC_TOG - USB Misc Register */
38789/* @{ */
38790#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U)
38791#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U)
38792#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK)
38793#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U)
38794#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U)
38795#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK)
38796#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U)
38797#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U)
38798#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK)
38799/* @} */
38800
38801/* The count of USB_ANALOG_MISC_TOG */
38802#define USB_ANALOG_MISC_TOG_COUNT (2U)
38803
38804/* @name DIGPROG - Chip Silicon Version */
38805/* @{ */
38806#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU)
38807#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U)
38808/* SILICON_REVISION
38809 * 0b00000000011011000000000000000000..Silicon revision 1.0
38810 */
38811#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK)
38812/* @} */
38813
38814
38815/*
38816 * @}
38817 */ /* end of group USB_ANALOG_Register_Masks */
38818
38819
38820/* USB_ANALOG - Peripheral instance base addresses */
38821/* Peripheral USB_ANALOG base address */
38822#define USB_ANALOG_BASE (0x400D8000u)
38823/* Peripheral USB_ANALOG base pointer */
38824#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE)
38825/* Array initializer of USB_ANALOG peripheral base addresses */
38826#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE }
38827/* Array initializer of USB_ANALOG peripheral base pointers */
38828#define USB_ANALOG_BASE_PTRS { USB_ANALOG }
38829
38830/*
38831 * @}
38832 */ /* end of group USB_ANALOG_Peripheral_Access_Layer */
38833
38834
38835/* ----------------------------------------------------------------------------
38836 -- USDHC Peripheral Access Layer
38837 ---------------------------------------------------------------------------- */
38838
38839/*
38840 * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
38841 * @{
38842 */
38843
38844/* USDHC - Register Layout Typedef */
38845typedef struct {
38846 __IO uint32_t DS_ADDR;
38847 __IO uint32_t BLK_ATT;
38848 __IO uint32_t CMD_ARG;
38849 __IO uint32_t CMD_XFR_TYP;
38850 __I uint32_t CMD_RSP0;
38851 __I uint32_t CMD_RSP1;
38852 __I uint32_t CMD_RSP2;
38853 __I uint32_t CMD_RSP3;
38854 __IO uint32_t DATA_BUFF_ACC_PORT;
38855 __I uint32_t PRES_STATE;
38856 __IO uint32_t PROT_CTRL;
38857 __IO uint32_t SYS_CTRL;
38858 __IO uint32_t INT_STATUS;
38859 __IO uint32_t INT_STATUS_EN;
38860 __IO uint32_t INT_SIGNAL_EN;
38861 __IO uint32_t AUTOCMD12_ERR_STATUS;
38862 __IO uint32_t HOST_CTRL_CAP;
38863 __IO uint32_t WTMK_LVL;
38864 __IO uint32_t MIX_CTRL;
38865 uint8_t RESERVED_0[4];
38866 __O uint32_t FORCE_EVENT;
38867 __I uint32_t ADMA_ERR_STATUS;
38868 __IO uint32_t ADMA_SYS_ADDR;
38869 uint8_t RESERVED_1[4];
38870 __IO uint32_t DLL_CTRL;
38871 __I uint32_t DLL_STATUS;
38872 __IO uint32_t CLK_TUNE_CTRL_STATUS;
38873 uint8_t RESERVED_2[84];
38874 __IO uint32_t VEND_SPEC;
38875 __IO uint32_t MMC_BOOT;
38876 __IO uint32_t VEND_SPEC2;
38877 __IO uint32_t TUNING_CTRL;
38878} USDHC_Type;
38879
38880/* ----------------------------------------------------------------------------
38881 -- USDHC Register Masks
38882 ---------------------------------------------------------------------------- */
38883
38884/*
38885 * @addtogroup USDHC_Register_Masks USDHC Register Masks
38886 * @{
38887 */
38888
38889/* @name DS_ADDR - DMA System Address */
38890/* @{ */
38891#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
38892#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
38893#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
38894/* @} */
38895
38896/* @name BLK_ATT - Block Attributes */
38897/* @{ */
38898#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
38899#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
38900/* BLKSIZE - Block Size
38901 * 0b1000000000000..4096 Bytes
38902 * 0b0100000000000..2048 Bytes
38903 * 0b0001000000000..512 Bytes
38904 * 0b0000111111111..511 Bytes
38905 * 0b0000000000100..4 Bytes
38906 * 0b0000000000011..3 Bytes
38907 * 0b0000000000010..2 Bytes
38908 * 0b0000000000001..1 Byte
38909 * 0b0000000000000..No data transfer
38910 */
38911#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
38912#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
38913#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
38914/* BLKCNT - Block Count
38915 * 0b1111111111111111..65535 blocks
38916 * 0b0000000000000010..2 blocks
38917 * 0b0000000000000001..1 block
38918 * 0b0000000000000000..Stop Count
38919 */
38920#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
38921/* @} */
38922
38923/* @name CMD_ARG - Command Argument */
38924/* @{ */
38925#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
38926#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
38927#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
38928/* @} */
38929
38930/* @name CMD_XFR_TYP - Command Transfer Type */
38931/* @{ */
38932#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
38933#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
38934/* RSPTYP - Response Type Select
38935 * 0b00..No Response
38936 * 0b01..Response Length 136
38937 * 0b10..Response Length 48
38938 * 0b11..Response Length 48, check Busy after response
38939 */
38940#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
38941#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
38942#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
38943/* CCCEN - Command CRC Check Enable
38944 * 0b1..Enable
38945 * 0b0..Disable
38946 */
38947#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
38948#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
38949#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
38950/* CICEN - Command Index Check Enable
38951 * 0b1..Enable
38952 * 0b0..Disable
38953 */
38954#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
38955#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
38956#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
38957/* DPSEL - Data Present Select
38958 * 0b1..Data Present
38959 * 0b0..No Data Present
38960 */
38961#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
38962#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
38963#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
38964/* CMDTYP - Command Type
38965 * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
38966 * 0b10..Resume CMD52 for writing Function Select in CCCR
38967 * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR
38968 * 0b00..Normal Other commands
38969 */
38970#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
38971#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
38972#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
38973#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
38974/* @} */
38975
38976/* @name CMD_RSP0 - Command Response0 */
38977/* @{ */
38978#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
38979#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
38980#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
38981/* @} */
38982
38983/* @name CMD_RSP1 - Command Response1 */
38984/* @{ */
38985#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
38986#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
38987#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
38988/* @} */
38989
38990/* @name CMD_RSP2 - Command Response2 */
38991/* @{ */
38992#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
38993#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
38994#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
38995/* @} */
38996
38997/* @name CMD_RSP3 - Command Response3 */
38998/* @{ */
38999#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
39000#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
39001#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
39002/* @} */
39003
39004/* @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
39005/* @{ */
39006#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
39007#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
39008#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
39009/* @} */
39010
39011/* @name PRES_STATE - Present State */
39012/* @{ */
39013#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
39014#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
39015/* CIHB - Command Inhibit (CMD)
39016 * 0b1..Cannot issue command
39017 * 0b0..Can issue command using only CMD line
39018 */
39019#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
39020#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
39021#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
39022/* CDIHB - Command Inhibit (DATA)
39023 * 0b1..Cannot issue command which uses the DATA line
39024 * 0b0..Can issue command which uses the DATA line
39025 */
39026#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
39027#define USDHC_PRES_STATE_DLA_MASK (0x4U)
39028#define USDHC_PRES_STATE_DLA_SHIFT (2U)
39029/* DLA - Data Line Active
39030 * 0b1..DATA Line Active
39031 * 0b0..DATA Line Inactive
39032 */
39033#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
39034#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
39035#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
39036/* SDSTB - SD Clock Stable
39037 * 0b1..Clock is stable.
39038 * 0b0..Clock is changing frequency and not stable.
39039 */
39040#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
39041#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
39042#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
39043/* IPGOFF - IPG_CLK Gated Off Internally
39044 * 0b1..IPG_CLK is gated off.
39045 * 0b0..IPG_CLK is active.
39046 */
39047#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
39048#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
39049#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
39050/* HCKOFF - HCLK Gated Off Internally
39051 * 0b1..HCLK is gated off.
39052 * 0b0..HCLK is active.
39053 */
39054#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
39055#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
39056#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
39057/* PEROFF - IPG_PERCLK Gated Off Internally
39058 * 0b1..IPG_PERCLK is gated off.
39059 * 0b0..IPG_PERCLK is active.
39060 */
39061#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
39062#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
39063#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
39064/* SDOFF - SD Clock Gated Off Internally
39065 * 0b1..SD Clock is gated off.
39066 * 0b0..SD Clock is active.
39067 */
39068#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
39069#define USDHC_PRES_STATE_WTA_MASK (0x100U)
39070#define USDHC_PRES_STATE_WTA_SHIFT (8U)
39071/* WTA - Write Transfer Active
39072 * 0b1..Transferring data
39073 * 0b0..No valid data
39074 */
39075#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
39076#define USDHC_PRES_STATE_RTA_MASK (0x200U)
39077#define USDHC_PRES_STATE_RTA_SHIFT (9U)
39078/* RTA - Read Transfer Active
39079 * 0b1..Transferring data
39080 * 0b0..No valid data
39081 */
39082#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
39083#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
39084#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
39085/* BWEN - Buffer Write Enable
39086 * 0b1..Write enable
39087 * 0b0..Write disable
39088 */
39089#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
39090#define USDHC_PRES_STATE_BREN_MASK (0x800U)
39091#define USDHC_PRES_STATE_BREN_SHIFT (11U)
39092/* BREN - Buffer Read Enable
39093 * 0b1..Read enable
39094 * 0b0..Read disable
39095 */
39096#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
39097#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
39098#define USDHC_PRES_STATE_RTR_SHIFT (12U)
39099/* RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode)
39100 * 0b1..Sampling clock needs re-tuning
39101 * 0b0..Fixed or well tuned sampling clock
39102 */
39103#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
39104#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
39105#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
39106/* TSCD - Tape Select Change Done
39107 * 0b1..Delay cell select change is finished.
39108 * 0b0..Delay cell select change is not finished.
39109 */
39110#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
39111#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
39112#define USDHC_PRES_STATE_CINST_SHIFT (16U)
39113/* CINST - Card Inserted
39114 * 0b1..Card Inserted
39115 * 0b0..Power on Reset or No Card
39116 */
39117#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
39118#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
39119#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
39120/* CDPL - Card Detect Pin Level
39121 * 0b1..Card present (CD_B = 0)
39122 * 0b0..No card present (CD_B = 1)
39123 */
39124#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
39125#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
39126#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
39127/* WPSPL - Write Protect Switch Pin Level
39128 * 0b1..Write enabled (WP = 0)
39129 * 0b0..Write protected (WP = 1)
39130 */
39131#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
39132#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
39133#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
39134#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
39135#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
39136#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
39137/* DLSL - DATA[7:0] Line Signal Level
39138 * 0b00000111..Data 7 line signal level
39139 * 0b00000110..Data 6 line signal level
39140 * 0b00000101..Data 5 line signal level
39141 * 0b00000100..Data 4 line signal level
39142 * 0b00000011..Data 3 line signal level
39143 * 0b00000010..Data 2 line signal level
39144 * 0b00000001..Data 1 line signal level
39145 * 0b00000000..Data 0 line signal level
39146 */
39147#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
39148/* @} */
39149
39150/* @name PROT_CTRL - Protocol Control */
39151/* @{ */
39152#define USDHC_PROT_CTRL_LCTL_MASK (0x1U)
39153#define USDHC_PROT_CTRL_LCTL_SHIFT (0U)
39154/* LCTL - LED Control
39155 * 0b1..LED on
39156 * 0b0..LED off
39157 */
39158#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
39159#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
39160#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
39161/* DTW - Data Transfer Width
39162 * 0b10..8-bit mode
39163 * 0b01..4-bit mode
39164 * 0b00..1-bit mode
39165 * 0b11..Reserved
39166 */
39167#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
39168#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
39169#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
39170/* D3CD - DATA3 as Card Detection Pin
39171 * 0b1..DATA3 as Card Detection Pin
39172 * 0b0..DATA3 does not monitor Card Insertion
39173 */
39174#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
39175#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
39176#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
39177/* EMODE - Endian Mode
39178 * 0b00..Big Endian Mode
39179 * 0b01..Half Word Big Endian Mode
39180 * 0b10..Little Endian Mode
39181 * 0b11..Reserved
39182 */
39183#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
39184#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
39185#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
39186/* CDTL - Card Detect Test Level
39187 * 0b1..Card Detect Test Level is 1, card inserted
39188 * 0b0..Card Detect Test Level is 0, no card inserted
39189 */
39190#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
39191#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
39192#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
39193/* CDSS - Card Detect Signal Selection
39194 * 0b1..Card Detection Test Level is selected (for test purpose).
39195 * 0b0..Card Detection Level is selected (for normal purpose).
39196 */
39197#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
39198#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
39199#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
39200/* DMASEL - DMA Select
39201 * 0b00..No DMA or Simple DMA is selected
39202 * 0b01..ADMA1 is selected
39203 * 0b10..ADMA2 is selected
39204 * 0b11..reserved
39205 */
39206#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
39207#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
39208#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
39209/* SABGREQ - Stop At Block Gap Request
39210 * 0b1..Stop
39211 * 0b0..Transfer
39212 */
39213#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
39214#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
39215#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
39216/* CREQ - Continue Request
39217 * 0b1..Restart
39218 * 0b0..No effect
39219 */
39220#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
39221#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
39222#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
39223/* RWCTL - Read Wait Control
39224 * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
39225 * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
39226 */
39227#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
39228#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
39229#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
39230/* IABG - Interrupt At Block Gap
39231 * 0b1..Enabled
39232 * 0b0..Disabled
39233 */
39234#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
39235#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
39236#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
39237#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
39238#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
39239#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
39240/* WECINT - Wakeup Event Enable On Card Interrupt
39241 * 0b1..Enable
39242 * 0b0..Disable
39243 */
39244#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
39245#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
39246#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
39247/* WECINS - Wakeup Event Enable On SD Card Insertion
39248 * 0b1..Enable
39249 * 0b0..Disable
39250 */
39251#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
39252#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
39253#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
39254/* WECRM - Wakeup Event Enable On SD Card Removal
39255 * 0b1..Enable
39256 * 0b0..Disable
39257 */
39258#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
39259#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
39260#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
39261/* BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
39262 * 0bxx1..Burst length is enabled for INCR
39263 * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16
39264 * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
39265 */
39266#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
39267#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
39268#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
39269/* NON_EXACT_BLK_RD - NON_EXACT_BLK_RD
39270 * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
39271 * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read.
39272 */
39273#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
39274/* @} */
39275
39276/* @name SYS_CTRL - System Control */
39277/* @{ */
39278#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
39279#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
39280/* DVS - Divisor
39281 * 0b0000..Divide-by-1
39282 * 0b0001..Divide-by-2
39283 * 0b1110..Divide-by-15
39284 * 0b1111..Divide-by-16
39285 */
39286#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
39287#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
39288#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
39289#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
39290#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
39291#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
39292/* DTOCV - Data Timeout Counter Value
39293 * 0b1111..SDCLK x 2 29
39294 * 0b1110..SDCLK x 2 28
39295 * 0b1101..SDCLK x 2 27
39296 * 0b0001..SDCLK x 2 15
39297 * 0b0000..SDCLK x 2 14
39298 */
39299#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
39300#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
39301#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
39302#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
39303#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
39304#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
39305/* RSTA - Software Reset For ALL
39306 * 0b1..Reset
39307 * 0b0..No Reset
39308 */
39309#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
39310#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
39311#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
39312/* RSTC - Software Reset For CMD Line
39313 * 0b1..Reset
39314 * 0b0..No Reset
39315 */
39316#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
39317#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
39318#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
39319/* RSTD - Software Reset For DATA Line
39320 * 0b1..Reset
39321 * 0b0..No Reset
39322 */
39323#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
39324#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
39325#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
39326#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
39327#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
39328#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
39329#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
39330/* @} */
39331
39332/* @name INT_STATUS - Interrupt Status */
39333/* @{ */
39334#define USDHC_INT_STATUS_CC_MASK (0x1U)
39335#define USDHC_INT_STATUS_CC_SHIFT (0U)
39336/* CC - Command Complete
39337 * 0b1..Command complete
39338 * 0b0..Command not complete
39339 */
39340#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
39341#define USDHC_INT_STATUS_TC_MASK (0x2U)
39342#define USDHC_INT_STATUS_TC_SHIFT (1U)
39343/* TC - Transfer Complete
39344 * 0b1..Transfer complete
39345 * 0b0..Transfer not complete
39346 */
39347#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
39348#define USDHC_INT_STATUS_BGE_MASK (0x4U)
39349#define USDHC_INT_STATUS_BGE_SHIFT (2U)
39350/* BGE - Block Gap Event
39351 * 0b1..Transaction stopped at block gap
39352 * 0b0..No block gap event
39353 */
39354#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
39355#define USDHC_INT_STATUS_DINT_MASK (0x8U)
39356#define USDHC_INT_STATUS_DINT_SHIFT (3U)
39357/* DINT - DMA Interrupt
39358 * 0b1..DMA Interrupt is generated
39359 * 0b0..No DMA Interrupt
39360 */
39361#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
39362#define USDHC_INT_STATUS_BWR_MASK (0x10U)
39363#define USDHC_INT_STATUS_BWR_SHIFT (4U)
39364/* BWR - Buffer Write Ready
39365 * 0b1..Ready to write buffer:
39366 * 0b0..Not ready to write buffer
39367 */
39368#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
39369#define USDHC_INT_STATUS_BRR_MASK (0x20U)
39370#define USDHC_INT_STATUS_BRR_SHIFT (5U)
39371/* BRR - Buffer Read Ready
39372 * 0b1..Ready to read buffer
39373 * 0b0..Not ready to read buffer
39374 */
39375#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
39376#define USDHC_INT_STATUS_CINS_MASK (0x40U)
39377#define USDHC_INT_STATUS_CINS_SHIFT (6U)
39378/* CINS - Card Insertion
39379 * 0b1..Card inserted
39380 * 0b0..Card state unstable or removed
39381 */
39382#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
39383#define USDHC_INT_STATUS_CRM_MASK (0x80U)
39384#define USDHC_INT_STATUS_CRM_SHIFT (7U)
39385/* CRM - Card Removal
39386 * 0b1..Card removed
39387 * 0b0..Card state unstable or inserted
39388 */
39389#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
39390#define USDHC_INT_STATUS_CINT_MASK (0x100U)
39391#define USDHC_INT_STATUS_CINT_SHIFT (8U)
39392/* CINT - Card Interrupt
39393 * 0b1..Generate Card Interrupt
39394 * 0b0..No Card Interrupt
39395 */
39396#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
39397#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
39398#define USDHC_INT_STATUS_RTE_SHIFT (12U)
39399/* RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
39400 * 0b1..Re-Tuning should be performed
39401 * 0b0..Re-Tuning is not required
39402 */
39403#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
39404#define USDHC_INT_STATUS_TP_MASK (0x4000U)
39405#define USDHC_INT_STATUS_TP_SHIFT (14U)
39406#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
39407#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
39408#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
39409/* CTOE - Command Timeout Error
39410 * 0b1..Time out
39411 * 0b0..No Error
39412 */
39413#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
39414#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
39415#define USDHC_INT_STATUS_CCE_SHIFT (17U)
39416/* CCE - Command CRC Error
39417 * 0b1..CRC Error Generated.
39418 * 0b0..No Error
39419 */
39420#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
39421#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
39422#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
39423/* CEBE - Command End Bit Error
39424 * 0b1..End Bit Error Generated
39425 * 0b0..No Error
39426 */
39427#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
39428#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
39429#define USDHC_INT_STATUS_CIE_SHIFT (19U)
39430/* CIE - Command Index Error
39431 * 0b1..Error
39432 * 0b0..No Error
39433 */
39434#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
39435#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
39436#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
39437/* DTOE - Data Timeout Error
39438 * 0b1..Time out
39439 * 0b0..No Error
39440 */
39441#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
39442#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
39443#define USDHC_INT_STATUS_DCE_SHIFT (21U)
39444/* DCE - Data CRC Error
39445 * 0b1..Error
39446 * 0b0..No Error
39447 */
39448#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
39449#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
39450#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
39451/* DEBE - Data End Bit Error
39452 * 0b1..Error
39453 * 0b0..No Error
39454 */
39455#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
39456#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
39457#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
39458/* AC12E - Auto CMD12 Error
39459 * 0b1..Error
39460 * 0b0..No Error
39461 */
39462#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
39463#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
39464#define USDHC_INT_STATUS_TNE_SHIFT (26U)
39465#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
39466#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
39467#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
39468/* DMAE - DMA Error
39469 * 0b1..Error
39470 * 0b0..No Error
39471 */
39472#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
39473/* @} */
39474
39475/* @name INT_STATUS_EN - Interrupt Status Enable */
39476/* @{ */
39477#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
39478#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
39479/* CCSEN - Command Complete Status Enable
39480 * 0b1..Enabled
39481 * 0b0..Masked
39482 */
39483#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
39484#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
39485#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
39486/* TCSEN - Transfer Complete Status Enable
39487 * 0b1..Enabled
39488 * 0b0..Masked
39489 */
39490#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
39491#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
39492#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
39493/* BGESEN - Block Gap Event Status Enable
39494 * 0b1..Enabled
39495 * 0b0..Masked
39496 */
39497#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
39498#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
39499#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
39500/* DINTSEN - DMA Interrupt Status Enable
39501 * 0b1..Enabled
39502 * 0b0..Masked
39503 */
39504#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
39505#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
39506#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
39507/* BWRSEN - Buffer Write Ready Status Enable
39508 * 0b1..Enabled
39509 * 0b0..Masked
39510 */
39511#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
39512#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
39513#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
39514/* BRRSEN - Buffer Read Ready Status Enable
39515 * 0b1..Enabled
39516 * 0b0..Masked
39517 */
39518#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
39519#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
39520#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
39521/* CINSSEN - Card Insertion Status Enable
39522 * 0b1..Enabled
39523 * 0b0..Masked
39524 */
39525#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
39526#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
39527#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
39528/* CRMSEN - Card Removal Status Enable
39529 * 0b1..Enabled
39530 * 0b0..Masked
39531 */
39532#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
39533#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
39534#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
39535/* CINTSEN - Card Interrupt Status Enable
39536 * 0b1..Enabled
39537 * 0b0..Masked
39538 */
39539#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
39540#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
39541#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
39542/* RTESEN - Re-Tuning Event Status Enable
39543 * 0b1..Enabled
39544 * 0b0..Masked
39545 */
39546#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
39547#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
39548#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
39549/* TPSEN - Tuning Pass Status Enable
39550 * 0b1..Enabled
39551 * 0b0..Masked
39552 */
39553#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
39554#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
39555#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
39556/* CTOESEN - Command Timeout Error Status Enable
39557 * 0b1..Enabled
39558 * 0b0..Masked
39559 */
39560#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
39561#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
39562#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
39563/* CCESEN - Command CRC Error Status Enable
39564 * 0b1..Enabled
39565 * 0b0..Masked
39566 */
39567#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
39568#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
39569#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
39570/* CEBESEN - Command End Bit Error Status Enable
39571 * 0b1..Enabled
39572 * 0b0..Masked
39573 */
39574#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
39575#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
39576#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
39577/* CIESEN - Command Index Error Status Enable
39578 * 0b1..Enabled
39579 * 0b0..Masked
39580 */
39581#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
39582#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
39583#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
39584/* DTOESEN - Data Timeout Error Status Enable
39585 * 0b1..Enabled
39586 * 0b0..Masked
39587 */
39588#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
39589#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
39590#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
39591/* DCESEN - Data CRC Error Status Enable
39592 * 0b1..Enabled
39593 * 0b0..Masked
39594 */
39595#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
39596#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
39597#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
39598/* DEBESEN - Data End Bit Error Status Enable
39599 * 0b1..Enabled
39600 * 0b0..Masked
39601 */
39602#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
39603#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
39604#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
39605/* AC12ESEN - Auto CMD12 Error Status Enable
39606 * 0b1..Enabled
39607 * 0b0..Masked
39608 */
39609#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
39610#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
39611#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
39612/* TNESEN - Tuning Error Status Enable
39613 * 0b1..Enabled
39614 * 0b0..Masked
39615 */
39616#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
39617#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
39618#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
39619/* DMAESEN - DMA Error Status Enable
39620 * 0b1..Enabled
39621 * 0b0..Masked
39622 */
39623#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
39624/* @} */
39625
39626/* @name INT_SIGNAL_EN - Interrupt Signal Enable */
39627/* @{ */
39628#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
39629#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
39630/* CCIEN - Command Complete Interrupt Enable
39631 * 0b1..Enabled
39632 * 0b0..Masked
39633 */
39634#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
39635#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
39636#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
39637/* TCIEN - Transfer Complete Interrupt Enable
39638 * 0b1..Enabled
39639 * 0b0..Masked
39640 */
39641#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
39642#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
39643#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
39644/* BGEIEN - Block Gap Event Interrupt Enable
39645 * 0b1..Enabled
39646 * 0b0..Masked
39647 */
39648#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
39649#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
39650#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
39651/* DINTIEN - DMA Interrupt Enable
39652 * 0b1..Enabled
39653 * 0b0..Masked
39654 */
39655#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
39656#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
39657#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
39658/* BWRIEN - Buffer Write Ready Interrupt Enable
39659 * 0b1..Enabled
39660 * 0b0..Masked
39661 */
39662#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
39663#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
39664#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
39665/* BRRIEN - Buffer Read Ready Interrupt Enable
39666 * 0b1..Enabled
39667 * 0b0..Masked
39668 */
39669#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
39670#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
39671#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
39672/* CINSIEN - Card Insertion Interrupt Enable
39673 * 0b1..Enabled
39674 * 0b0..Masked
39675 */
39676#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
39677#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
39678#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
39679/* CRMIEN - Card Removal Interrupt Enable
39680 * 0b1..Enabled
39681 * 0b0..Masked
39682 */
39683#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
39684#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
39685#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
39686/* CINTIEN - Card Interrupt Interrupt Enable
39687 * 0b1..Enabled
39688 * 0b0..Masked
39689 */
39690#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
39691#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
39692#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
39693/* RTEIEN - Re-Tuning Event Interrupt Enable
39694 * 0b1..Enabled
39695 * 0b0..Masked
39696 */
39697#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
39698#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
39699#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
39700/* TPIEN - Tuning Pass Interrupt Enable
39701 * 0b1..Enabled
39702 * 0b0..Masked
39703 */
39704#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
39705#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
39706#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
39707/* CTOEIEN - Command Timeout Error Interrupt Enable
39708 * 0b1..Enabled
39709 * 0b0..Masked
39710 */
39711#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
39712#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
39713#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
39714/* CCEIEN - Command CRC Error Interrupt Enable
39715 * 0b1..Enabled
39716 * 0b0..Masked
39717 */
39718#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
39719#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
39720#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
39721/* CEBEIEN - Command End Bit Error Interrupt Enable
39722 * 0b1..Enabled
39723 * 0b0..Masked
39724 */
39725#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
39726#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
39727#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
39728/* CIEIEN - Command Index Error Interrupt Enable
39729 * 0b1..Enabled
39730 * 0b0..Masked
39731 */
39732#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
39733#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
39734#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
39735/* DTOEIEN - Data Timeout Error Interrupt Enable
39736 * 0b1..Enabled
39737 * 0b0..Masked
39738 */
39739#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
39740#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
39741#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
39742/* DCEIEN - Data CRC Error Interrupt Enable
39743 * 0b1..Enabled
39744 * 0b0..Masked
39745 */
39746#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
39747#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
39748#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
39749/* DEBEIEN - Data End Bit Error Interrupt Enable
39750 * 0b1..Enabled
39751 * 0b0..Masked
39752 */
39753#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
39754#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
39755#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
39756/* AC12EIEN - Auto CMD12 Error Interrupt Enable
39757 * 0b1..Enabled
39758 * 0b0..Masked
39759 */
39760#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
39761#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
39762#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
39763/* TNEIEN - Tuning Error Interrupt Enable
39764 * 0b1..Enabled
39765 * 0b0..Masked
39766 */
39767#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
39768#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
39769#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
39770/* DMAEIEN - DMA Error Interrupt Enable
39771 * 0b1..Enable
39772 * 0b0..Masked
39773 */
39774#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
39775/* @} */
39776
39777/* @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
39778/* @{ */
39779#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
39780#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
39781/* AC12NE - Auto CMD12 Not Executed
39782 * 0b1..Not executed
39783 * 0b0..Executed
39784 */
39785#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
39786#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
39787#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
39788/* AC12TOE - Auto CMD12 / 23 Timeout Error
39789 * 0b1..Time out
39790 * 0b0..No error
39791 */
39792#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
39793#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
39794#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
39795/* AC12EBE - Auto CMD12 / 23 End Bit Error
39796 * 0b1..End Bit Error Generated
39797 * 0b0..No error
39798 */
39799#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
39800#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
39801#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
39802/* AC12CE - Auto CMD12 / 23 CRC Error
39803 * 0b1..CRC Error Met in Auto CMD12/23 Response
39804 * 0b0..No CRC error
39805 */
39806#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
39807#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
39808#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
39809/* AC12IE - Auto CMD12 / 23 Index Error
39810 * 0b1..Error, the CMD index in response is not CMD12/23
39811 * 0b0..No error
39812 */
39813#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
39814#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
39815#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
39816/* CNIBAC12E - Command Not Issued By Auto CMD12 Error
39817 * 0b1..Not Issued
39818 * 0b0..No error
39819 */
39820#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
39821#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
39822#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
39823#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
39824#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
39825#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
39826/* SMP_CLK_SEL - Sample Clock Select
39827 * 0b1..Tuned clock is used to sample data
39828 * 0b0..Fixed clock is used to sample data
39829 */
39830#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
39831/* @} */
39832
39833/* @name HOST_CTRL_CAP - Host Controller Capabilities */
39834/* @{ */
39835#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
39836#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
39837#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
39838#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
39839#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
39840#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
39841#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
39842#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
39843#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
39844#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
39845#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
39846#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
39847#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
39848#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
39849/* USE_TUNING_SDR50 - Use Tuning for SDR50
39850 * 0b1..SDR50 requires tuning
39851 * 0b0..SDR does not require tuning
39852 */
39853#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
39854#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
39855#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
39856/* RETUNING_MODE - Retuning Mode
39857 * 0b00..Mode 1
39858 * 0b01..Mode 2
39859 * 0b10..Mode 3
39860 * 0b11..Reserved
39861 */
39862#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
39863#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
39864#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
39865/* MBL - Max Block Length
39866 * 0b000..512 bytes
39867 * 0b001..1024 bytes
39868 * 0b010..2048 bytes
39869 * 0b011..4096 bytes
39870 */
39871#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
39872#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
39873#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
39874/* ADMAS - ADMA Support
39875 * 0b1..Advanced DMA Supported
39876 * 0b0..Advanced DMA Not supported
39877 */
39878#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
39879#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
39880#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
39881/* HSS - High Speed Support
39882 * 0b1..High Speed Supported
39883 * 0b0..High Speed Not Supported
39884 */
39885#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
39886#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
39887#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
39888/* DMAS - DMA Support
39889 * 0b1..DMA Supported
39890 * 0b0..DMA not supported
39891 */
39892#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
39893#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
39894#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
39895/* SRS - Suspend / Resume Support
39896 * 0b1..Supported
39897 * 0b0..Not supported
39898 */
39899#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
39900#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
39901#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
39902/* VS33 - Voltage Support 3.3V
39903 * 0b1..3.3V supported
39904 * 0b0..3.3V not supported
39905 */
39906#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
39907#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
39908#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
39909/* VS30 - Voltage Support 3.0 V
39910 * 0b1..3.0V supported
39911 * 0b0..3.0V not supported
39912 */
39913#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
39914#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
39915#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
39916/* VS18 - Voltage Support 1.8 V
39917 * 0b1..1.8V supported
39918 * 0b0..1.8V not supported
39919 */
39920#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
39921/* @} */
39922
39923/* @name WTMK_LVL - Watermark Level */
39924/* @{ */
39925#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
39926#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
39927#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
39928#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
39929#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
39930#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
39931#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
39932#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
39933#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
39934#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
39935#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
39936#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
39937/* @} */
39938
39939/* @name MIX_CTRL - Mixer Control */
39940/* @{ */
39941#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
39942#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
39943/* DMAEN - DMA Enable
39944 * 0b1..Enable
39945 * 0b0..Disable
39946 */
39947#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
39948#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
39949#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
39950/* BCEN - Block Count Enable
39951 * 0b1..Enable
39952 * 0b0..Disable
39953 */
39954#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
39955#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
39956#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
39957/* AC12EN - Auto CMD12 Enable
39958 * 0b1..Enable
39959 * 0b0..Disable
39960 */
39961#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
39962#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
39963#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
39964#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
39965#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
39966#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
39967/* DTDSEL - Data Transfer Direction Select
39968 * 0b1..Read (Card to Host)
39969 * 0b0..Write (Host to Card)
39970 */
39971#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
39972#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
39973#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
39974/* MSBSEL - Multi / Single Block Select
39975 * 0b1..Multiple Blocks
39976 * 0b0..Single Block
39977 */
39978#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
39979#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
39980#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
39981#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
39982#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
39983#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
39984#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
39985#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
39986#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
39987/* EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
39988 * 0b1..Execute Tuning
39989 * 0b0..Not Tuned or Tuning Completed
39990 */
39991#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
39992#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
39993#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
39994/* SMP_CLK_SEL - SMP_CLK_SEL
39995 * 0b1..Tuned clock is used to sample data / cmd
39996 * 0b0..Fixed clock is used to sample data / cmd
39997 */
39998#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
39999#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
40000#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
40001/* AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
40002 * 0b1..Enable auto tuning
40003 * 0b0..Disable auto tuning
40004 */
40005#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
40006#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
40007#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
40008/* FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
40009 * 0b1..Feedback clock comes from the ipp_card_clk_out
40010 * 0b0..Feedback clock comes from the loopback CLK
40011 */
40012#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
40013/* @} */
40014
40015/* @name FORCE_EVENT - Force Event */
40016/* @{ */
40017#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
40018#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
40019#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
40020#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
40021#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
40022#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
40023#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
40024#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
40025#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
40026#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
40027#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
40028#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
40029#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
40030#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
40031#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
40032#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
40033#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
40034#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
40035#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
40036#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
40037#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
40038#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
40039#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
40040#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
40041#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
40042#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
40043#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
40044#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
40045#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
40046#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
40047#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
40048#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
40049#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
40050#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
40051#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
40052#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
40053#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
40054#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
40055#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
40056#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
40057#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
40058#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
40059#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
40060#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
40061#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
40062#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
40063#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
40064#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
40065#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
40066#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
40067#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
40068/* @} */
40069
40070/* @name ADMA_ERR_STATUS - ADMA Error Status Register */
40071/* @{ */
40072#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
40073#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
40074#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
40075#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
40076#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
40077/* ADMALME - ADMA Length Mismatch Error
40078 * 0b1..Error
40079 * 0b0..No Error
40080 */
40081#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
40082#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
40083#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
40084/* ADMADCE - ADMA Descriptor Error
40085 * 0b1..Error
40086 * 0b0..No Error
40087 */
40088#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
40089/* @} */
40090
40091/* @name ADMA_SYS_ADDR - ADMA System Address */
40092/* @{ */
40093#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
40094#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
40095#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
40096/* @} */
40097
40098/* @name DLL_CTRL - DLL (Delay Line) Control */
40099/* @{ */
40100#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
40101#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
40102#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
40103#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
40104#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
40105#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
40106#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
40107#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
40108#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
40109#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
40110#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
40111#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
40112#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
40113#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
40114#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
40115#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
40116#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
40117#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
40118#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
40119#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
40120#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
40121#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
40122#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
40123#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
40124#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
40125#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
40126#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
40127#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
40128#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
40129#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
40130/* @} */
40131
40132/* @name DLL_STATUS - DLL Status */
40133/* @{ */
40134#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
40135#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
40136#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
40137#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
40138#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
40139#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
40140#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
40141#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
40142#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
40143#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
40144#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
40145#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
40146/* @} */
40147
40148/* @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
40149/* @{ */
40150#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
40151#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
40152#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
40153#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
40154#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
40155#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
40156#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
40157#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
40158#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
40159#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
40160#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
40161#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
40162#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
40163#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
40164#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
40165#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
40166#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
40167#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
40168#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
40169#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
40170#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
40171#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
40172#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
40173#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
40174/* @} */
40175
40176/* @name VEND_SPEC - Vendor Specific Register */
40177/* @{ */
40178#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
40179#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
40180/* VSELECT - Voltage Selection
40181 * 0b1..Change the voltage to low voltage range, around 1.8 V
40182 * 0b0..Change the voltage to high voltage range, around 3.0 V
40183 */
40184#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
40185#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
40186#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
40187/* CONFLICT_CHK_EN - Conflict check enable.
40188 * 0b0..Conflict check disable
40189 * 0b1..Conflict check enable
40190 */
40191#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
40192#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
40193#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
40194/* AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN
40195 * 0b0..Do not check busy after auto CMD12 for write data packet
40196 * 0b1..Check busy after auto CMD12 for write data packet
40197 */
40198#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
40199#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
40200#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
40201/* FRC_SDCLK_ON - FRC_SDCLK_ON
40202 * 0b0..CLK active or inactive is fully controlled by the hardware.
40203 * 0b1..Force CLK active.
40204 */
40205#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
40206#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
40207#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
40208/* CRC_CHK_DIS - CRC Check Disable
40209 * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet
40210 * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
40211 */
40212#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
40213#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
40214#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
40215/* CMD_BYTE_EN - CMD_BYTE_EN
40216 * 0b0..Disable
40217 * 0b1..Enable
40218 */
40219#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
40220/* @} */
40221
40222/* @name MMC_BOOT - MMC Boot Register */
40223/* @{ */
40224#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
40225#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
40226/* DTOCV_ACK - DTOCV_ACK
40227 * 0b0000..SDCLK x 2^14
40228 * 0b0001..SDCLK x 2^15
40229 * 0b0010..SDCLK x 2^16
40230 * 0b0011..SDCLK x 2^17
40231 * 0b0100..SDCLK x 2^18
40232 * 0b0101..SDCLK x 2^19
40233 * 0b0110..SDCLK x 2^20
40234 * 0b0111..SDCLK x 2^21
40235 * 0b1110..SDCLK x 2^28
40236 * 0b1111..SDCLK x 2^29
40237 */
40238#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
40239#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
40240#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
40241/* BOOT_ACK - BOOT_ACK
40242 * 0b0..No ack
40243 * 0b1..Ack
40244 */
40245#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
40246#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
40247#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
40248/* BOOT_MODE - BOOT_MODE
40249 * 0b0..Normal boot
40250 * 0b1..Alternative boot
40251 */
40252#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
40253#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
40254#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
40255/* BOOT_EN - BOOT_EN
40256 * 0b0..Fast boot disable
40257 * 0b1..Fast boot enable
40258 */
40259#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
40260#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
40261#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
40262#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
40263#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
40264#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
40265/* DISABLE_TIME_OUT - Disable Time Out
40266 * 0b0..Enable time out
40267 * 0b1..Disable time out
40268 */
40269#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
40270#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
40271#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
40272#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
40273/* @} */
40274
40275/* @name VEND_SPEC2 - Vendor Specific 2 Register */
40276/* @{ */
40277#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
40278#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
40279/* CARD_INT_D3_TEST - Card Interrupt Detection Test
40280 * 0b0..Check the card interrupt only when DATA3 is high.
40281 * 0b1..Check the card interrupt by ignoring the status of DATA3.
40282 */
40283#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
40284#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
40285#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
40286#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
40287#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
40288#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
40289#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
40290#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
40291#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
40292/* TUNING_CMD_EN - TUNING_CMD_EN
40293 * 0b0..Auto tuning circuit does not check the CMD line.
40294 * 0b1..Auto tuning circuit checks the CMD line.
40295 */
40296#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
40297#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
40298#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
40299/* ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
40300 * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable.
40301 * 0b0..Disable
40302 */
40303#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
40304#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U)
40305#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U)
40306#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK)
40307#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U)
40308#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U)
40309#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK)
40310/* @} */
40311
40312/* @name TUNING_CTRL - Tuning Control Register */
40313/* @{ */
40314#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
40315#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
40316#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
40317#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
40318#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
40319#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
40320#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
40321#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
40322#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
40323#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
40324#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
40325#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
40326#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
40327#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
40328#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
40329/* @} */
40330
40331
40332/*
40333 * @}
40334 */ /* end of group USDHC_Register_Masks */
40335
40336
40337/* USDHC - Peripheral instance base addresses */
40338/* Peripheral USDHC1 base address */
40339#define USDHC1_BASE (0x402C0000u)
40340/* Peripheral USDHC1 base pointer */
40341#define USDHC1 ((USDHC_Type *)USDHC1_BASE)
40342/* Peripheral USDHC2 base address */
40343#define USDHC2_BASE (0x402C4000u)
40344/* Peripheral USDHC2 base pointer */
40345#define USDHC2 ((USDHC_Type *)USDHC2_BASE)
40346/* Array initializer of USDHC peripheral base addresses */
40347#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
40348/* Array initializer of USDHC peripheral base pointers */
40349#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
40350/* Interrupt vectors for the USDHC peripheral type */
40351#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
40352
40353/*
40354 * @}
40355 */ /* end of group USDHC_Peripheral_Access_Layer */
40356
40357
40358/* ----------------------------------------------------------------------------
40359 -- WDOG Peripheral Access Layer
40360 ---------------------------------------------------------------------------- */
40361
40362/*
40363 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
40364 * @{
40365 */
40366
40367/* WDOG - Register Layout Typedef */
40368typedef struct {
40369 __IO uint16_t WCR;
40370 __IO uint16_t WSR;
40371 __I uint16_t WRSR;
40372 __IO uint16_t WICR;
40373 __IO uint16_t WMCR;
40374} WDOG_Type;
40375
40376/* ----------------------------------------------------------------------------
40377 -- WDOG Register Masks
40378 ---------------------------------------------------------------------------- */
40379
40380/*
40381 * @addtogroup WDOG_Register_Masks WDOG Register Masks
40382 * @{
40383 */
40384
40385/* @name WCR - Watchdog Control Register */
40386/* @{ */
40387#define WDOG_WCR_WDZST_MASK (0x1U)
40388#define WDOG_WCR_WDZST_SHIFT (0U)
40389/* WDZST - WDZST
40390 * 0b0..Continue timer operation (Default).
40391 * 0b1..Suspend the watchdog timer.
40392 */
40393#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
40394#define WDOG_WCR_WDBG_MASK (0x2U)
40395#define WDOG_WCR_WDBG_SHIFT (1U)
40396/* WDBG - WDBG
40397 * 0b0..Continue WDOG timer operation (Default).
40398 * 0b1..Suspend the watchdog timer.
40399 */
40400#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
40401#define WDOG_WCR_WDE_MASK (0x4U)
40402#define WDOG_WCR_WDE_SHIFT (2U)
40403/* WDE - WDE
40404 * 0b0..Disable the Watchdog (Default).
40405 * 0b1..Enable the Watchdog.
40406 */
40407#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
40408#define WDOG_WCR_WDT_MASK (0x8U)
40409#define WDOG_WCR_WDT_SHIFT (3U)
40410/* WDT - WDT
40411 * 0b0..No effect on WDOG_B (Default).
40412 * 0b1..Assert WDOG_B upon a Watchdog Time-out event.
40413 */
40414#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
40415#define WDOG_WCR_SRS_MASK (0x10U)
40416#define WDOG_WCR_SRS_SHIFT (4U)
40417/* SRS - SRS
40418 * 0b0..Assert system reset signal.
40419 * 0b1..No effect on the system (Default).
40420 */
40421#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
40422#define WDOG_WCR_WDA_MASK (0x20U)
40423#define WDOG_WCR_WDA_SHIFT (5U)
40424/* WDA - WDA
40425 * 0b0..Assert WDOG_B output.
40426 * 0b1..No effect on system (Default).
40427 */
40428#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
40429#define WDOG_WCR_SRE_MASK (0x40U)
40430#define WDOG_WCR_SRE_SHIFT (6U)
40431/* SRE - software reset extension, an option way to generate software reset
40432 * 0b0..using original way to generate software reset (default)
40433 * 0b1..using new way to generate software reset.
40434 */
40435#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
40436#define WDOG_WCR_WDW_MASK (0x80U)
40437#define WDOG_WCR_WDW_SHIFT (7U)
40438/* WDW - WDW
40439 * 0b0..Continue WDOG timer operation (Default).
40440 * 0b1..Suspend WDOG timer operation.
40441 */
40442#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
40443#define WDOG_WCR_WT_MASK (0xFF00U)
40444#define WDOG_WCR_WT_SHIFT (8U)
40445/* WT - WT
40446 * 0b00000000..- 0.5 Seconds (Default).
40447 * 0b00000001..- 1.0 Seconds.
40448 * 0b00000010..- 1.5 Seconds.
40449 * 0b00000011..- 2.0 Seconds.
40450 * 0b11111111..- 128 Seconds.
40451 */
40452#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
40453/* @} */
40454
40455/* @name WSR - Watchdog Service Register */
40456/* @{ */
40457#define WDOG_WSR_WSR_MASK (0xFFFFU)
40458#define WDOG_WSR_WSR_SHIFT (0U)
40459/* WSR - WSR
40460 * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
40461 * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
40462 */
40463#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
40464/* @} */
40465
40466/* @name WRSR - Watchdog Reset Status Register */
40467/* @{ */
40468#define WDOG_WRSR_SFTW_MASK (0x1U)
40469#define WDOG_WRSR_SFTW_SHIFT (0U)
40470/* SFTW - SFTW
40471 * 0b0..Reset is not the result of a software reset.
40472 * 0b1..Reset is the result of a software reset.
40473 */
40474#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
40475#define WDOG_WRSR_TOUT_MASK (0x2U)
40476#define WDOG_WRSR_TOUT_SHIFT (1U)
40477/* TOUT - TOUT
40478 * 0b0..Reset is not the result of a WDOG timeout.
40479 * 0b1..Reset is the result of a WDOG timeout.
40480 */
40481#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
40482#define WDOG_WRSR_POR_MASK (0x10U)
40483#define WDOG_WRSR_POR_SHIFT (4U)
40484/* POR - POR
40485 * 0b0..Reset is not the result of a power on reset.
40486 * 0b1..Reset is the result of a power on reset.
40487 */
40488#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
40489/* @} */
40490
40491/* @name WICR - Watchdog Interrupt Control Register */
40492/* @{ */
40493#define WDOG_WICR_WICT_MASK (0xFFU)
40494#define WDOG_WICR_WICT_SHIFT (0U)
40495/* WICT - WICT
40496 * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
40497 * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
40498 * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
40499 * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
40500 */
40501#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
40502#define WDOG_WICR_WTIS_MASK (0x4000U)
40503#define WDOG_WICR_WTIS_SHIFT (14U)
40504/* WTIS - WTIS
40505 * 0b0..No interrupt has occurred (Default).
40506 * 0b1..Interrupt has occurred
40507 */
40508#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
40509#define WDOG_WICR_WIE_MASK (0x8000U)
40510#define WDOG_WICR_WIE_SHIFT (15U)
40511/* WIE - WIE
40512 * 0b0..Disable Interrupt (Default).
40513 * 0b1..Enable Interrupt.
40514 */
40515#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
40516/* @} */
40517
40518/* @name WMCR - Watchdog Miscellaneous Control Register */
40519/* @{ */
40520#define WDOG_WMCR_PDE_MASK (0x1U)
40521#define WDOG_WMCR_PDE_SHIFT (0U)
40522/* PDE - PDE
40523 * 0b0..Power Down Counter of WDOG is disabled.
40524 * 0b1..Power Down Counter of WDOG is enabled (Default).
40525 */
40526#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
40527/* @} */
40528
40529
40530/*
40531 * @}
40532 */ /* end of group WDOG_Register_Masks */
40533
40534
40535/* WDOG - Peripheral instance base addresses */
40536/* Peripheral WDOG1 base address */
40537#define WDOG1_BASE (0x400B8000u)
40538/* Peripheral WDOG1 base pointer */
40539#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
40540/* Peripheral WDOG2 base address */
40541#define WDOG2_BASE (0x400D0000u)
40542/* Peripheral WDOG2 base pointer */
40543#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
40544/* Array initializer of WDOG peripheral base addresses */
40545#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
40546/* Array initializer of WDOG peripheral base pointers */
40547#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
40548/* Interrupt vectors for the WDOG peripheral type */
40549#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
40550
40551/*
40552 * @}
40553 */ /* end of group WDOG_Peripheral_Access_Layer */
40554
40555
40556/* ----------------------------------------------------------------------------
40557 -- XBARA Peripheral Access Layer
40558 ---------------------------------------------------------------------------- */
40559
40560/*
40561 * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer
40562 * @{
40563 */
40564
40565/* XBARA - Register Layout Typedef */
40566typedef struct {
40567 union {
40568 struct {
40569 __IO uint16_t SEL0;
40570 __IO uint16_t SEL1;
40571 __IO uint16_t SEL2;
40572 __IO uint16_t SEL3;
40573 __IO uint16_t SEL4;
40574 __IO uint16_t SEL5;
40575 __IO uint16_t SEL6;
40576 __IO uint16_t SEL7;
40577 __IO uint16_t SEL8;
40578 __IO uint16_t SEL9;
40579 __IO uint16_t SEL10;
40580 __IO uint16_t SEL11;
40581 __IO uint16_t SEL12;
40582 __IO uint16_t SEL13;
40583 __IO uint16_t SEL14;
40584 __IO uint16_t SEL15;
40585 __IO uint16_t SEL16;
40586 __IO uint16_t SEL17;
40587 __IO uint16_t SEL18;
40588 __IO uint16_t SEL19;
40589 __IO uint16_t SEL20;
40590 __IO uint16_t SEL21;
40591 __IO uint16_t SEL22;
40592 __IO uint16_t SEL23;
40593 __IO uint16_t SEL24;
40594 __IO uint16_t SEL25;
40595 __IO uint16_t SEL26;
40596 __IO uint16_t SEL27;
40597 __IO uint16_t SEL28;
40598 __IO uint16_t SEL29;
40599 __IO uint16_t SEL30;
40600 __IO uint16_t SEL31;
40601 __IO uint16_t SEL32;
40602 __IO uint16_t SEL33;
40603 __IO uint16_t SEL34;
40604 __IO uint16_t SEL35;
40605 __IO uint16_t SEL36;
40606 __IO uint16_t SEL37;
40607 __IO uint16_t SEL38;
40608 __IO uint16_t SEL39;
40609 __IO uint16_t SEL40;
40610 __IO uint16_t SEL41;
40611 __IO uint16_t SEL42;
40612 __IO uint16_t SEL43;
40613 __IO uint16_t SEL44;
40614 __IO uint16_t SEL45;
40615 __IO uint16_t SEL46;
40616 __IO uint16_t SEL47;
40617 __IO uint16_t SEL48;
40618 __IO uint16_t SEL49;
40619 __IO uint16_t SEL50;
40620 __IO uint16_t SEL51;
40621 __IO uint16_t SEL52;
40622 __IO uint16_t SEL53;
40623 __IO uint16_t SEL54;
40624 __IO uint16_t SEL55;
40625 __IO uint16_t SEL56;
40626 __IO uint16_t SEL57;
40627 __IO uint16_t SEL58;
40628 __IO uint16_t SEL59;
40629 __IO uint16_t SEL60;
40630 __IO uint16_t SEL61;
40631 __IO uint16_t SEL62;
40632 __IO uint16_t SEL63;
40633 __IO uint16_t SEL64;
40634 __IO uint16_t SEL65;
40635 };
40636 __IO uint16_t SEL[66];
40637 };
40638 __IO uint16_t CTRL0;
40639 __IO uint16_t CTRL1;
40640} XBARA_Type;
40641
40642/* ----------------------------------------------------------------------------
40643 -- XBARA Register Masks
40644 ---------------------------------------------------------------------------- */
40645
40646/*
40647 * @addtogroup XBARA_Register_Masks XBARA Register Masks
40648 * @{
40649 */
40650
40651/* @name SEL0 - Crossbar A Select Register 0 */
40652/* @{ */
40653#define XBARA_SEL0_SEL0_MASK (0x7FU)
40654#define XBARA_SEL0_SEL0_SHIFT (0U)
40655#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
40656#define XBARA_SEL0_SEL1_MASK (0x7F00U)
40657#define XBARA_SEL0_SEL1_SHIFT (8U)
40658#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
40659/* @} */
40660
40661/* @name SEL1 - Crossbar A Select Register 1 */
40662/* @{ */
40663#define XBARA_SEL1_SEL2_MASK (0x7FU)
40664#define XBARA_SEL1_SEL2_SHIFT (0U)
40665#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
40666#define XBARA_SEL1_SEL3_MASK (0x7F00U)
40667#define XBARA_SEL1_SEL3_SHIFT (8U)
40668#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
40669/* @} */
40670
40671/* @name SEL2 - Crossbar A Select Register 2 */
40672/* @{ */
40673#define XBARA_SEL2_SEL4_MASK (0x7FU)
40674#define XBARA_SEL2_SEL4_SHIFT (0U)
40675#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
40676#define XBARA_SEL2_SEL5_MASK (0x7F00U)
40677#define XBARA_SEL2_SEL5_SHIFT (8U)
40678#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
40679/* @} */
40680
40681/* @name SEL3 - Crossbar A Select Register 3 */
40682/* @{ */
40683#define XBARA_SEL3_SEL6_MASK (0x7FU)
40684#define XBARA_SEL3_SEL6_SHIFT (0U)
40685#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
40686#define XBARA_SEL3_SEL7_MASK (0x7F00U)
40687#define XBARA_SEL3_SEL7_SHIFT (8U)
40688#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
40689/* @} */
40690
40691/* @name SEL4 - Crossbar A Select Register 4 */
40692/* @{ */
40693#define XBARA_SEL4_SEL8_MASK (0x7FU)
40694#define XBARA_SEL4_SEL8_SHIFT (0U)
40695#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
40696#define XBARA_SEL4_SEL9_MASK (0x7F00U)
40697#define XBARA_SEL4_SEL9_SHIFT (8U)
40698#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
40699/* @} */
40700
40701/* @name SEL5 - Crossbar A Select Register 5 */
40702/* @{ */
40703#define XBARA_SEL5_SEL10_MASK (0x7FU)
40704#define XBARA_SEL5_SEL10_SHIFT (0U)
40705#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
40706#define XBARA_SEL5_SEL11_MASK (0x7F00U)
40707#define XBARA_SEL5_SEL11_SHIFT (8U)
40708#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
40709/* @} */
40710
40711/* @name SEL6 - Crossbar A Select Register 6 */
40712/* @{ */
40713#define XBARA_SEL6_SEL12_MASK (0x7FU)
40714#define XBARA_SEL6_SEL12_SHIFT (0U)
40715#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
40716#define XBARA_SEL6_SEL13_MASK (0x7F00U)
40717#define XBARA_SEL6_SEL13_SHIFT (8U)
40718#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
40719/* @} */
40720
40721/* @name SEL7 - Crossbar A Select Register 7 */
40722/* @{ */
40723#define XBARA_SEL7_SEL14_MASK (0x7FU)
40724#define XBARA_SEL7_SEL14_SHIFT (0U)
40725#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
40726#define XBARA_SEL7_SEL15_MASK (0x7F00U)
40727#define XBARA_SEL7_SEL15_SHIFT (8U)
40728#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
40729/* @} */
40730
40731/* @name SEL8 - Crossbar A Select Register 8 */
40732/* @{ */
40733#define XBARA_SEL8_SEL16_MASK (0x7FU)
40734#define XBARA_SEL8_SEL16_SHIFT (0U)
40735#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
40736#define XBARA_SEL8_SEL17_MASK (0x7F00U)
40737#define XBARA_SEL8_SEL17_SHIFT (8U)
40738#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
40739/* @} */
40740
40741/* @name SEL9 - Crossbar A Select Register 9 */
40742/* @{ */
40743#define XBARA_SEL9_SEL18_MASK (0x7FU)
40744#define XBARA_SEL9_SEL18_SHIFT (0U)
40745#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
40746#define XBARA_SEL9_SEL19_MASK (0x7F00U)
40747#define XBARA_SEL9_SEL19_SHIFT (8U)
40748#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
40749/* @} */
40750
40751/* @name SEL10 - Crossbar A Select Register 10 */
40752/* @{ */
40753#define XBARA_SEL10_SEL20_MASK (0x7FU)
40754#define XBARA_SEL10_SEL20_SHIFT (0U)
40755#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
40756#define XBARA_SEL10_SEL21_MASK (0x7F00U)
40757#define XBARA_SEL10_SEL21_SHIFT (8U)
40758#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
40759/* @} */
40760
40761/* @name SEL11 - Crossbar A Select Register 11 */
40762/* @{ */
40763#define XBARA_SEL11_SEL22_MASK (0x7FU)
40764#define XBARA_SEL11_SEL22_SHIFT (0U)
40765#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
40766#define XBARA_SEL11_SEL23_MASK (0x7F00U)
40767#define XBARA_SEL11_SEL23_SHIFT (8U)
40768#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
40769/* @} */
40770
40771/* @name SEL12 - Crossbar A Select Register 12 */
40772/* @{ */
40773#define XBARA_SEL12_SEL24_MASK (0x7FU)
40774#define XBARA_SEL12_SEL24_SHIFT (0U)
40775#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
40776#define XBARA_SEL12_SEL25_MASK (0x7F00U)
40777#define XBARA_SEL12_SEL25_SHIFT (8U)
40778#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
40779/* @} */
40780
40781/* @name SEL13 - Crossbar A Select Register 13 */
40782/* @{ */
40783#define XBARA_SEL13_SEL26_MASK (0x7FU)
40784#define XBARA_SEL13_SEL26_SHIFT (0U)
40785#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
40786#define XBARA_SEL13_SEL27_MASK (0x7F00U)
40787#define XBARA_SEL13_SEL27_SHIFT (8U)
40788#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
40789/* @} */
40790
40791/* @name SEL14 - Crossbar A Select Register 14 */
40792/* @{ */
40793#define XBARA_SEL14_SEL28_MASK (0x7FU)
40794#define XBARA_SEL14_SEL28_SHIFT (0U)
40795#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
40796#define XBARA_SEL14_SEL29_MASK (0x7F00U)
40797#define XBARA_SEL14_SEL29_SHIFT (8U)
40798#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
40799/* @} */
40800
40801/* @name SEL15 - Crossbar A Select Register 15 */
40802/* @{ */
40803#define XBARA_SEL15_SEL30_MASK (0x7FU)
40804#define XBARA_SEL15_SEL30_SHIFT (0U)
40805#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
40806#define XBARA_SEL15_SEL31_MASK (0x7F00U)
40807#define XBARA_SEL15_SEL31_SHIFT (8U)
40808#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
40809/* @} */
40810
40811/* @name SEL16 - Crossbar A Select Register 16 */
40812/* @{ */
40813#define XBARA_SEL16_SEL32_MASK (0x7FU)
40814#define XBARA_SEL16_SEL32_SHIFT (0U)
40815#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
40816#define XBARA_SEL16_SEL33_MASK (0x7F00U)
40817#define XBARA_SEL16_SEL33_SHIFT (8U)
40818#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
40819/* @} */
40820
40821/* @name SEL17 - Crossbar A Select Register 17 */
40822/* @{ */
40823#define XBARA_SEL17_SEL34_MASK (0x7FU)
40824#define XBARA_SEL17_SEL34_SHIFT (0U)
40825#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
40826#define XBARA_SEL17_SEL35_MASK (0x7F00U)
40827#define XBARA_SEL17_SEL35_SHIFT (8U)
40828#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
40829/* @} */
40830
40831/* @name SEL18 - Crossbar A Select Register 18 */
40832/* @{ */
40833#define XBARA_SEL18_SEL36_MASK (0x7FU)
40834#define XBARA_SEL18_SEL36_SHIFT (0U)
40835#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
40836#define XBARA_SEL18_SEL37_MASK (0x7F00U)
40837#define XBARA_SEL18_SEL37_SHIFT (8U)
40838#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
40839/* @} */
40840
40841/* @name SEL19 - Crossbar A Select Register 19 */
40842/* @{ */
40843#define XBARA_SEL19_SEL38_MASK (0x7FU)
40844#define XBARA_SEL19_SEL38_SHIFT (0U)
40845#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
40846#define XBARA_SEL19_SEL39_MASK (0x7F00U)
40847#define XBARA_SEL19_SEL39_SHIFT (8U)
40848#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
40849/* @} */
40850
40851/* @name SEL20 - Crossbar A Select Register 20 */
40852/* @{ */
40853#define XBARA_SEL20_SEL40_MASK (0x7FU)
40854#define XBARA_SEL20_SEL40_SHIFT (0U)
40855#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
40856#define XBARA_SEL20_SEL41_MASK (0x7F00U)
40857#define XBARA_SEL20_SEL41_SHIFT (8U)
40858#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
40859/* @} */
40860
40861/* @name SEL21 - Crossbar A Select Register 21 */
40862/* @{ */
40863#define XBARA_SEL21_SEL42_MASK (0x7FU)
40864#define XBARA_SEL21_SEL42_SHIFT (0U)
40865#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
40866#define XBARA_SEL21_SEL43_MASK (0x7F00U)
40867#define XBARA_SEL21_SEL43_SHIFT (8U)
40868#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
40869/* @} */
40870
40871/* @name SEL22 - Crossbar A Select Register 22 */
40872/* @{ */
40873#define XBARA_SEL22_SEL44_MASK (0x7FU)
40874#define XBARA_SEL22_SEL44_SHIFT (0U)
40875#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
40876#define XBARA_SEL22_SEL45_MASK (0x7F00U)
40877#define XBARA_SEL22_SEL45_SHIFT (8U)
40878#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
40879/* @} */
40880
40881/* @name SEL23 - Crossbar A Select Register 23 */
40882/* @{ */
40883#define XBARA_SEL23_SEL46_MASK (0x7FU)
40884#define XBARA_SEL23_SEL46_SHIFT (0U)
40885#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
40886#define XBARA_SEL23_SEL47_MASK (0x7F00U)
40887#define XBARA_SEL23_SEL47_SHIFT (8U)
40888#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
40889/* @} */
40890
40891/* @name SEL24 - Crossbar A Select Register 24 */
40892/* @{ */
40893#define XBARA_SEL24_SEL48_MASK (0x7FU)
40894#define XBARA_SEL24_SEL48_SHIFT (0U)
40895#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
40896#define XBARA_SEL24_SEL49_MASK (0x7F00U)
40897#define XBARA_SEL24_SEL49_SHIFT (8U)
40898#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
40899/* @} */
40900
40901/* @name SEL25 - Crossbar A Select Register 25 */
40902/* @{ */
40903#define XBARA_SEL25_SEL50_MASK (0x7FU)
40904#define XBARA_SEL25_SEL50_SHIFT (0U)
40905#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
40906#define XBARA_SEL25_SEL51_MASK (0x7F00U)
40907#define XBARA_SEL25_SEL51_SHIFT (8U)
40908#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
40909/* @} */
40910
40911/* @name SEL26 - Crossbar A Select Register 26 */
40912/* @{ */
40913#define XBARA_SEL26_SEL52_MASK (0x7FU)
40914#define XBARA_SEL26_SEL52_SHIFT (0U)
40915#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
40916#define XBARA_SEL26_SEL53_MASK (0x7F00U)
40917#define XBARA_SEL26_SEL53_SHIFT (8U)
40918#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
40919/* @} */
40920
40921/* @name SEL27 - Crossbar A Select Register 27 */
40922/* @{ */
40923#define XBARA_SEL27_SEL54_MASK (0x7FU)
40924#define XBARA_SEL27_SEL54_SHIFT (0U)
40925#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
40926#define XBARA_SEL27_SEL55_MASK (0x7F00U)
40927#define XBARA_SEL27_SEL55_SHIFT (8U)
40928#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
40929/* @} */
40930
40931/* @name SEL28 - Crossbar A Select Register 28 */
40932/* @{ */
40933#define XBARA_SEL28_SEL56_MASK (0x7FU)
40934#define XBARA_SEL28_SEL56_SHIFT (0U)
40935#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
40936#define XBARA_SEL28_SEL57_MASK (0x7F00U)
40937#define XBARA_SEL28_SEL57_SHIFT (8U)
40938#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
40939/* @} */
40940
40941/* @name SEL29 - Crossbar A Select Register 29 */
40942/* @{ */
40943#define XBARA_SEL29_SEL58_MASK (0x7FU)
40944#define XBARA_SEL29_SEL58_SHIFT (0U)
40945#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
40946#define XBARA_SEL29_SEL59_MASK (0x7F00U)
40947#define XBARA_SEL29_SEL59_SHIFT (8U)
40948#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
40949/* @} */
40950
40951/* @name SEL30 - Crossbar A Select Register 30 */
40952/* @{ */
40953#define XBARA_SEL30_SEL60_MASK (0x7FU)
40954#define XBARA_SEL30_SEL60_SHIFT (0U)
40955#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
40956#define XBARA_SEL30_SEL61_MASK (0x7F00U)
40957#define XBARA_SEL30_SEL61_SHIFT (8U)
40958#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
40959/* @} */
40960
40961/* @name SEL31 - Crossbar A Select Register 31 */
40962/* @{ */
40963#define XBARA_SEL31_SEL62_MASK (0x7FU)
40964#define XBARA_SEL31_SEL62_SHIFT (0U)
40965#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
40966#define XBARA_SEL31_SEL63_MASK (0x7F00U)
40967#define XBARA_SEL31_SEL63_SHIFT (8U)
40968#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
40969/* @} */
40970
40971/* @name SEL32 - Crossbar A Select Register 32 */
40972/* @{ */
40973#define XBARA_SEL32_SEL64_MASK (0x7FU)
40974#define XBARA_SEL32_SEL64_SHIFT (0U)
40975#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
40976#define XBARA_SEL32_SEL65_MASK (0x7F00U)
40977#define XBARA_SEL32_SEL65_SHIFT (8U)
40978#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
40979/* @} */
40980
40981/* @name SEL33 - Crossbar A Select Register 33 */
40982/* @{ */
40983#define XBARA_SEL33_SEL66_MASK (0x7FU)
40984#define XBARA_SEL33_SEL66_SHIFT (0U)
40985#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
40986#define XBARA_SEL33_SEL67_MASK (0x7F00U)
40987#define XBARA_SEL33_SEL67_SHIFT (8U)
40988#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
40989/* @} */
40990
40991/* @name SEL34 - Crossbar A Select Register 34 */
40992/* @{ */
40993#define XBARA_SEL34_SEL68_MASK (0x7FU)
40994#define XBARA_SEL34_SEL68_SHIFT (0U)
40995#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
40996#define XBARA_SEL34_SEL69_MASK (0x7F00U)
40997#define XBARA_SEL34_SEL69_SHIFT (8U)
40998#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
40999/* @} */
41000
41001/* @name SEL35 - Crossbar A Select Register 35 */
41002/* @{ */
41003#define XBARA_SEL35_SEL70_MASK (0x7FU)
41004#define XBARA_SEL35_SEL70_SHIFT (0U)
41005#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
41006#define XBARA_SEL35_SEL71_MASK (0x7F00U)
41007#define XBARA_SEL35_SEL71_SHIFT (8U)
41008#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
41009/* @} */
41010
41011/* @name SEL36 - Crossbar A Select Register 36 */
41012/* @{ */
41013#define XBARA_SEL36_SEL72_MASK (0x7FU)
41014#define XBARA_SEL36_SEL72_SHIFT (0U)
41015#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
41016#define XBARA_SEL36_SEL73_MASK (0x7F00U)
41017#define XBARA_SEL36_SEL73_SHIFT (8U)
41018#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
41019/* @} */
41020
41021/* @name SEL37 - Crossbar A Select Register 37 */
41022/* @{ */
41023#define XBARA_SEL37_SEL74_MASK (0x7FU)
41024#define XBARA_SEL37_SEL74_SHIFT (0U)
41025#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
41026#define XBARA_SEL37_SEL75_MASK (0x7F00U)
41027#define XBARA_SEL37_SEL75_SHIFT (8U)
41028#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
41029/* @} */
41030
41031/* @name SEL38 - Crossbar A Select Register 38 */
41032/* @{ */
41033#define XBARA_SEL38_SEL76_MASK (0x7FU)
41034#define XBARA_SEL38_SEL76_SHIFT (0U)
41035#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
41036#define XBARA_SEL38_SEL77_MASK (0x7F00U)
41037#define XBARA_SEL38_SEL77_SHIFT (8U)
41038#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
41039/* @} */
41040
41041/* @name SEL39 - Crossbar A Select Register 39 */
41042/* @{ */
41043#define XBARA_SEL39_SEL78_MASK (0x7FU)
41044#define XBARA_SEL39_SEL78_SHIFT (0U)
41045#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
41046#define XBARA_SEL39_SEL79_MASK (0x7F00U)
41047#define XBARA_SEL39_SEL79_SHIFT (8U)
41048#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
41049/* @} */
41050
41051/* @name SEL40 - Crossbar A Select Register 40 */
41052/* @{ */
41053#define XBARA_SEL40_SEL80_MASK (0x7FU)
41054#define XBARA_SEL40_SEL80_SHIFT (0U)
41055#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
41056#define XBARA_SEL40_SEL81_MASK (0x7F00U)
41057#define XBARA_SEL40_SEL81_SHIFT (8U)
41058#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
41059/* @} */
41060
41061/* @name SEL41 - Crossbar A Select Register 41 */
41062/* @{ */
41063#define XBARA_SEL41_SEL82_MASK (0x7FU)
41064#define XBARA_SEL41_SEL82_SHIFT (0U)
41065#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
41066#define XBARA_SEL41_SEL83_MASK (0x7F00U)
41067#define XBARA_SEL41_SEL83_SHIFT (8U)
41068#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
41069/* @} */
41070
41071/* @name SEL42 - Crossbar A Select Register 42 */
41072/* @{ */
41073#define XBARA_SEL42_SEL84_MASK (0x7FU)
41074#define XBARA_SEL42_SEL84_SHIFT (0U)
41075#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
41076#define XBARA_SEL42_SEL85_MASK (0x7F00U)
41077#define XBARA_SEL42_SEL85_SHIFT (8U)
41078#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
41079/* @} */
41080
41081/* @name SEL43 - Crossbar A Select Register 43 */
41082/* @{ */
41083#define XBARA_SEL43_SEL86_MASK (0x7FU)
41084#define XBARA_SEL43_SEL86_SHIFT (0U)
41085#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
41086#define XBARA_SEL43_SEL87_MASK (0x7F00U)
41087#define XBARA_SEL43_SEL87_SHIFT (8U)
41088#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
41089/* @} */
41090
41091/* @name SEL44 - Crossbar A Select Register 44 */
41092/* @{ */
41093#define XBARA_SEL44_SEL88_MASK (0x7FU)
41094#define XBARA_SEL44_SEL88_SHIFT (0U)
41095#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
41096#define XBARA_SEL44_SEL89_MASK (0x7F00U)
41097#define XBARA_SEL44_SEL89_SHIFT (8U)
41098#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
41099/* @} */
41100
41101/* @name SEL45 - Crossbar A Select Register 45 */
41102/* @{ */
41103#define XBARA_SEL45_SEL90_MASK (0x7FU)
41104#define XBARA_SEL45_SEL90_SHIFT (0U)
41105#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
41106#define XBARA_SEL45_SEL91_MASK (0x7F00U)
41107#define XBARA_SEL45_SEL91_SHIFT (8U)
41108#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
41109/* @} */
41110
41111/* @name SEL46 - Crossbar A Select Register 46 */
41112/* @{ */
41113#define XBARA_SEL46_SEL92_MASK (0x7FU)
41114#define XBARA_SEL46_SEL92_SHIFT (0U)
41115#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
41116#define XBARA_SEL46_SEL93_MASK (0x7F00U)
41117#define XBARA_SEL46_SEL93_SHIFT (8U)
41118#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
41119/* @} */
41120
41121/* @name SEL47 - Crossbar A Select Register 47 */
41122/* @{ */
41123#define XBARA_SEL47_SEL94_MASK (0x7FU)
41124#define XBARA_SEL47_SEL94_SHIFT (0U)
41125#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
41126#define XBARA_SEL47_SEL95_MASK (0x7F00U)
41127#define XBARA_SEL47_SEL95_SHIFT (8U)
41128#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
41129/* @} */
41130
41131/* @name SEL48 - Crossbar A Select Register 48 */
41132/* @{ */
41133#define XBARA_SEL48_SEL96_MASK (0x7FU)
41134#define XBARA_SEL48_SEL96_SHIFT (0U)
41135#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
41136#define XBARA_SEL48_SEL97_MASK (0x7F00U)
41137#define XBARA_SEL48_SEL97_SHIFT (8U)
41138#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
41139/* @} */
41140
41141/* @name SEL49 - Crossbar A Select Register 49 */
41142/* @{ */
41143#define XBARA_SEL49_SEL98_MASK (0x7FU)
41144#define XBARA_SEL49_SEL98_SHIFT (0U)
41145#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
41146#define XBARA_SEL49_SEL99_MASK (0x7F00U)
41147#define XBARA_SEL49_SEL99_SHIFT (8U)
41148#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
41149/* @} */
41150
41151/* @name SEL50 - Crossbar A Select Register 50 */
41152/* @{ */
41153#define XBARA_SEL50_SEL100_MASK (0x7FU)
41154#define XBARA_SEL50_SEL100_SHIFT (0U)
41155#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
41156#define XBARA_SEL50_SEL101_MASK (0x7F00U)
41157#define XBARA_SEL50_SEL101_SHIFT (8U)
41158#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
41159/* @} */
41160
41161/* @name SEL51 - Crossbar A Select Register 51 */
41162/* @{ */
41163#define XBARA_SEL51_SEL102_MASK (0x7FU)
41164#define XBARA_SEL51_SEL102_SHIFT (0U)
41165#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
41166#define XBARA_SEL51_SEL103_MASK (0x7F00U)
41167#define XBARA_SEL51_SEL103_SHIFT (8U)
41168#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
41169/* @} */
41170
41171/* @name SEL52 - Crossbar A Select Register 52 */
41172/* @{ */
41173#define XBARA_SEL52_SEL104_MASK (0x7FU)
41174#define XBARA_SEL52_SEL104_SHIFT (0U)
41175#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
41176#define XBARA_SEL52_SEL105_MASK (0x7F00U)
41177#define XBARA_SEL52_SEL105_SHIFT (8U)
41178#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
41179/* @} */
41180
41181/* @name SEL53 - Crossbar A Select Register 53 */
41182/* @{ */
41183#define XBARA_SEL53_SEL106_MASK (0x7FU)
41184#define XBARA_SEL53_SEL106_SHIFT (0U)
41185#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
41186#define XBARA_SEL53_SEL107_MASK (0x7F00U)
41187#define XBARA_SEL53_SEL107_SHIFT (8U)
41188#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
41189/* @} */
41190
41191/* @name SEL54 - Crossbar A Select Register 54 */
41192/* @{ */
41193#define XBARA_SEL54_SEL108_MASK (0x7FU)
41194#define XBARA_SEL54_SEL108_SHIFT (0U)
41195#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
41196#define XBARA_SEL54_SEL109_MASK (0x7F00U)
41197#define XBARA_SEL54_SEL109_SHIFT (8U)
41198#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
41199/* @} */
41200
41201/* @name SEL55 - Crossbar A Select Register 55 */
41202/* @{ */
41203#define XBARA_SEL55_SEL110_MASK (0x7FU)
41204#define XBARA_SEL55_SEL110_SHIFT (0U)
41205#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
41206#define XBARA_SEL55_SEL111_MASK (0x7F00U)
41207#define XBARA_SEL55_SEL111_SHIFT (8U)
41208#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
41209/* @} */
41210
41211/* @name SEL56 - Crossbar A Select Register 56 */
41212/* @{ */
41213#define XBARA_SEL56_SEL112_MASK (0x7FU)
41214#define XBARA_SEL56_SEL112_SHIFT (0U)
41215#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
41216#define XBARA_SEL56_SEL113_MASK (0x7F00U)
41217#define XBARA_SEL56_SEL113_SHIFT (8U)
41218#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
41219/* @} */
41220
41221/* @name SEL57 - Crossbar A Select Register 57 */
41222/* @{ */
41223#define XBARA_SEL57_SEL114_MASK (0x7FU)
41224#define XBARA_SEL57_SEL114_SHIFT (0U)
41225#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
41226#define XBARA_SEL57_SEL115_MASK (0x7F00U)
41227#define XBARA_SEL57_SEL115_SHIFT (8U)
41228#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
41229/* @} */
41230
41231/* @name SEL58 - Crossbar A Select Register 58 */
41232/* @{ */
41233#define XBARA_SEL58_SEL116_MASK (0x7FU)
41234#define XBARA_SEL58_SEL116_SHIFT (0U)
41235#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
41236#define XBARA_SEL58_SEL117_MASK (0x7F00U)
41237#define XBARA_SEL58_SEL117_SHIFT (8U)
41238#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
41239/* @} */
41240
41241/* @name SEL59 - Crossbar A Select Register 59 */
41242/* @{ */
41243#define XBARA_SEL59_SEL118_MASK (0x7FU)
41244#define XBARA_SEL59_SEL118_SHIFT (0U)
41245#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
41246#define XBARA_SEL59_SEL119_MASK (0x7F00U)
41247#define XBARA_SEL59_SEL119_SHIFT (8U)
41248#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
41249/* @} */
41250
41251/* @name SEL60 - Crossbar A Select Register 60 */
41252/* @{ */
41253#define XBARA_SEL60_SEL120_MASK (0x7FU)
41254#define XBARA_SEL60_SEL120_SHIFT (0U)
41255#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
41256#define XBARA_SEL60_SEL121_MASK (0x7F00U)
41257#define XBARA_SEL60_SEL121_SHIFT (8U)
41258#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
41259/* @} */
41260
41261/* @name SEL61 - Crossbar A Select Register 61 */
41262/* @{ */
41263#define XBARA_SEL61_SEL122_MASK (0x7FU)
41264#define XBARA_SEL61_SEL122_SHIFT (0U)
41265#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
41266#define XBARA_SEL61_SEL123_MASK (0x7F00U)
41267#define XBARA_SEL61_SEL123_SHIFT (8U)
41268#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
41269/* @} */
41270
41271/* @name SEL62 - Crossbar A Select Register 62 */
41272/* @{ */
41273#define XBARA_SEL62_SEL124_MASK (0x7FU)
41274#define XBARA_SEL62_SEL124_SHIFT (0U)
41275#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
41276#define XBARA_SEL62_SEL125_MASK (0x7F00U)
41277#define XBARA_SEL62_SEL125_SHIFT (8U)
41278#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
41279/* @} */
41280
41281/* @name SEL63 - Crossbar A Select Register 63 */
41282/* @{ */
41283#define XBARA_SEL63_SEL126_MASK (0x7FU)
41284#define XBARA_SEL63_SEL126_SHIFT (0U)
41285#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
41286#define XBARA_SEL63_SEL127_MASK (0x7F00U)
41287#define XBARA_SEL63_SEL127_SHIFT (8U)
41288#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
41289/* @} */
41290
41291/* @name SEL64 - Crossbar A Select Register 64 */
41292/* @{ */
41293#define XBARA_SEL64_SEL128_MASK (0x7FU)
41294#define XBARA_SEL64_SEL128_SHIFT (0U)
41295#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
41296#define XBARA_SEL64_SEL129_MASK (0x7F00U)
41297#define XBARA_SEL64_SEL129_SHIFT (8U)
41298#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
41299/* @} */
41300
41301/* @name SEL65 - Crossbar A Select Register 65 */
41302/* @{ */
41303#define XBARA_SEL65_SEL130_MASK (0x7FU)
41304#define XBARA_SEL65_SEL130_SHIFT (0U)
41305#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
41306#define XBARA_SEL65_SEL131_MASK (0x7F00U)
41307#define XBARA_SEL65_SEL131_SHIFT (8U)
41308#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
41309/* @} */
41310
41311/* @name CTRL0 - Crossbar A Control Register 0 */
41312/* @{ */
41313#define XBARA_CTRL0_DEN0_MASK (0x1U)
41314#define XBARA_CTRL0_DEN0_SHIFT (0U)
41315/* DEN0 - DMA Enable for XBAR_OUT0
41316 * 0b0..DMA disabled
41317 * 0b1..DMA enabled
41318 */
41319#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
41320#define XBARA_CTRL0_IEN0_MASK (0x2U)
41321#define XBARA_CTRL0_IEN0_SHIFT (1U)
41322/* IEN0 - Interrupt Enable for XBAR_OUT0
41323 * 0b0..Interrupt disabled
41324 * 0b1..Interrupt enabled
41325 */
41326#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
41327#define XBARA_CTRL0_EDGE0_MASK (0xCU)
41328#define XBARA_CTRL0_EDGE0_SHIFT (2U)
41329/* EDGE0 - Active edge for edge detection on XBAR_OUT0
41330 * 0b00..STS0 never asserts
41331 * 0b01..STS0 asserts on rising edges of XBAR_OUT0
41332 * 0b10..STS0 asserts on falling edges of XBAR_OUT0
41333 * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
41334 */
41335#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
41336#define XBARA_CTRL0_STS0_MASK (0x10U)
41337#define XBARA_CTRL0_STS0_SHIFT (4U)
41338/* STS0 - Edge detection status for XBAR_OUT0
41339 * 0b0..Active edge not yet detected on XBAR_OUT0
41340 * 0b1..Active edge detected on XBAR_OUT0
41341 */
41342#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
41343#define XBARA_CTRL0_DEN1_MASK (0x100U)
41344#define XBARA_CTRL0_DEN1_SHIFT (8U)
41345/* DEN1 - DMA Enable for XBAR_OUT1
41346 * 0b0..DMA disabled
41347 * 0b1..DMA enabled
41348 */
41349#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
41350#define XBARA_CTRL0_IEN1_MASK (0x200U)
41351#define XBARA_CTRL0_IEN1_SHIFT (9U)
41352/* IEN1 - Interrupt Enable for XBAR_OUT1
41353 * 0b0..Interrupt disabled
41354 * 0b1..Interrupt enabled
41355 */
41356#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
41357#define XBARA_CTRL0_EDGE1_MASK (0xC00U)
41358#define XBARA_CTRL0_EDGE1_SHIFT (10U)
41359/* EDGE1 - Active edge for edge detection on XBAR_OUT1
41360 * 0b00..STS1 never asserts
41361 * 0b01..STS1 asserts on rising edges of XBAR_OUT1
41362 * 0b10..STS1 asserts on falling edges of XBAR_OUT1
41363 * 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
41364 */
41365#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
41366#define XBARA_CTRL0_STS1_MASK (0x1000U)
41367#define XBARA_CTRL0_STS1_SHIFT (12U)
41368/* STS1 - Edge detection status for XBAR_OUT1
41369 * 0b0..Active edge not yet detected on XBAR_OUT1
41370 * 0b1..Active edge detected on XBAR_OUT1
41371 */
41372#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
41373/* @} */
41374
41375/* @name CTRL1 - Crossbar A Control Register 1 */
41376/* @{ */
41377#define XBARA_CTRL1_DEN2_MASK (0x1U)
41378#define XBARA_CTRL1_DEN2_SHIFT (0U)
41379/* DEN2 - DMA Enable for XBAR_OUT2
41380 * 0b0..DMA disabled
41381 * 0b1..DMA enabled
41382 */
41383#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
41384#define XBARA_CTRL1_IEN2_MASK (0x2U)
41385#define XBARA_CTRL1_IEN2_SHIFT (1U)
41386/* IEN2 - Interrupt Enable for XBAR_OUT2
41387 * 0b0..Interrupt disabled
41388 * 0b1..Interrupt enabled
41389 */
41390#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
41391#define XBARA_CTRL1_EDGE2_MASK (0xCU)
41392#define XBARA_CTRL1_EDGE2_SHIFT (2U)
41393/* EDGE2 - Active edge for edge detection on XBAR_OUT2
41394 * 0b00..STS2 never asserts
41395 * 0b01..STS2 asserts on rising edges of XBAR_OUT2
41396 * 0b10..STS2 asserts on falling edges of XBAR_OUT2
41397 * 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
41398 */
41399#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
41400#define XBARA_CTRL1_STS2_MASK (0x10U)
41401#define XBARA_CTRL1_STS2_SHIFT (4U)
41402/* STS2 - Edge detection status for XBAR_OUT2
41403 * 0b0..Active edge not yet detected on XBAR_OUT2
41404 * 0b1..Active edge detected on XBAR_OUT2
41405 */
41406#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
41407#define XBARA_CTRL1_DEN3_MASK (0x100U)
41408#define XBARA_CTRL1_DEN3_SHIFT (8U)
41409/* DEN3 - DMA Enable for XBAR_OUT3
41410 * 0b0..DMA disabled
41411 * 0b1..DMA enabled
41412 */
41413#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
41414#define XBARA_CTRL1_IEN3_MASK (0x200U)
41415#define XBARA_CTRL1_IEN3_SHIFT (9U)
41416/* IEN3 - Interrupt Enable for XBAR_OUT3
41417 * 0b0..Interrupt disabled
41418 * 0b1..Interrupt enabled
41419 */
41420#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
41421#define XBARA_CTRL1_EDGE3_MASK (0xC00U)
41422#define XBARA_CTRL1_EDGE3_SHIFT (10U)
41423/* EDGE3 - Active edge for edge detection on XBAR_OUT3
41424 * 0b00..STS3 never asserts
41425 * 0b01..STS3 asserts on rising edges of XBAR_OUT3
41426 * 0b10..STS3 asserts on falling edges of XBAR_OUT3
41427 * 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
41428 */
41429#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
41430#define XBARA_CTRL1_STS3_MASK (0x1000U)
41431#define XBARA_CTRL1_STS3_SHIFT (12U)
41432/* STS3 - Edge detection status for XBAR_OUT3
41433 * 0b0..Active edge not yet detected on XBAR_OUT3
41434 * 0b1..Active edge detected on XBAR_OUT3
41435 */
41436#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
41437/* @} */
41438
41439
41440/*
41441 * @}
41442 */ /* end of group XBARA_Register_Masks */
41443
41444
41445/* XBARA - Peripheral instance base addresses */
41446/* Peripheral XBARA1 base address */
41447#define XBARA1_BASE (0x403BC000u)
41448/* Peripheral XBARA1 base pointer */
41449#define XBARA1 ((XBARA_Type *)XBARA1_BASE)
41450/* Array initializer of XBARA peripheral base addresses */
41451#define XBARA_BASE_ADDRS { XBARA1_BASE }
41452/* Array initializer of XBARA peripheral base pointers */
41453#define XBARA_BASE_PTRS { XBARA1 }
41454
41455/*
41456 * @}
41457 */ /* end of group XBARA_Peripheral_Access_Layer */
41458
41459
41460/* ----------------------------------------------------------------------------
41461 -- XBARB Peripheral Access Layer
41462 ---------------------------------------------------------------------------- */
41463
41464/*
41465 * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer
41466 * @{
41467 */
41468
41469/* XBARB - Register Layout Typedef */
41470typedef struct {
41471 __IO uint16_t SEL0;
41472 __IO uint16_t SEL1;
41473 __IO uint16_t SEL2;
41474 __IO uint16_t SEL3;
41475 __IO uint16_t SEL4;
41476 __IO uint16_t SEL5;
41477 __IO uint16_t SEL6;
41478 __IO uint16_t SEL7;
41479} XBARB_Type;
41480
41481/* ----------------------------------------------------------------------------
41482 -- XBARB Register Masks
41483 ---------------------------------------------------------------------------- */
41484
41485/*
41486 * @addtogroup XBARB_Register_Masks XBARB Register Masks
41487 * @{
41488 */
41489
41490/* @name SEL0 - Crossbar B Select Register 0 */
41491/* @{ */
41492#define XBARB_SEL0_SEL0_MASK (0x3FU)
41493#define XBARB_SEL0_SEL0_SHIFT (0U)
41494#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
41495#define XBARB_SEL0_SEL1_MASK (0x3F00U)
41496#define XBARB_SEL0_SEL1_SHIFT (8U)
41497#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
41498/* @} */
41499
41500/* @name SEL1 - Crossbar B Select Register 1 */
41501/* @{ */
41502#define XBARB_SEL1_SEL2_MASK (0x3FU)
41503#define XBARB_SEL1_SEL2_SHIFT (0U)
41504#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
41505#define XBARB_SEL1_SEL3_MASK (0x3F00U)
41506#define XBARB_SEL1_SEL3_SHIFT (8U)
41507#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
41508/* @} */
41509
41510/* @name SEL2 - Crossbar B Select Register 2 */
41511/* @{ */
41512#define XBARB_SEL2_SEL4_MASK (0x3FU)
41513#define XBARB_SEL2_SEL4_SHIFT (0U)
41514#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
41515#define XBARB_SEL2_SEL5_MASK (0x3F00U)
41516#define XBARB_SEL2_SEL5_SHIFT (8U)
41517#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
41518/* @} */
41519
41520/* @name SEL3 - Crossbar B Select Register 3 */
41521/* @{ */
41522#define XBARB_SEL3_SEL6_MASK (0x3FU)
41523#define XBARB_SEL3_SEL6_SHIFT (0U)
41524#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
41525#define XBARB_SEL3_SEL7_MASK (0x3F00U)
41526#define XBARB_SEL3_SEL7_SHIFT (8U)
41527#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
41528/* @} */
41529
41530/* @name SEL4 - Crossbar B Select Register 4 */
41531/* @{ */
41532#define XBARB_SEL4_SEL8_MASK (0x3FU)
41533#define XBARB_SEL4_SEL8_SHIFT (0U)
41534#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
41535#define XBARB_SEL4_SEL9_MASK (0x3F00U)
41536#define XBARB_SEL4_SEL9_SHIFT (8U)
41537#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
41538/* @} */
41539
41540/* @name SEL5 - Crossbar B Select Register 5 */
41541/* @{ */
41542#define XBARB_SEL5_SEL10_MASK (0x3FU)
41543#define XBARB_SEL5_SEL10_SHIFT (0U)
41544#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
41545#define XBARB_SEL5_SEL11_MASK (0x3F00U)
41546#define XBARB_SEL5_SEL11_SHIFT (8U)
41547#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
41548/* @} */
41549
41550/* @name SEL6 - Crossbar B Select Register 6 */
41551/* @{ */
41552#define XBARB_SEL6_SEL12_MASK (0x3FU)
41553#define XBARB_SEL6_SEL12_SHIFT (0U)
41554#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
41555#define XBARB_SEL6_SEL13_MASK (0x3F00U)
41556#define XBARB_SEL6_SEL13_SHIFT (8U)
41557#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
41558/* @} */
41559
41560/* @name SEL7 - Crossbar B Select Register 7 */
41561/* @{ */
41562#define XBARB_SEL7_SEL14_MASK (0x3FU)
41563#define XBARB_SEL7_SEL14_SHIFT (0U)
41564#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
41565#define XBARB_SEL7_SEL15_MASK (0x3F00U)
41566#define XBARB_SEL7_SEL15_SHIFT (8U)
41567#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
41568/* @} */
41569
41570
41571/*
41572 * @}
41573 */ /* end of group XBARB_Register_Masks */
41574
41575
41576/* XBARB - Peripheral instance base addresses */
41577/* Peripheral XBARB2 base address */
41578#define XBARB2_BASE (0x403C0000u)
41579/* Peripheral XBARB2 base pointer */
41580#define XBARB2 ((XBARB_Type *)XBARB2_BASE)
41581/* Peripheral XBARB3 base address */
41582#define XBARB3_BASE (0x403C4000u)
41583/* Peripheral XBARB3 base pointer */
41584#define XBARB3 ((XBARB_Type *)XBARB3_BASE)
41585/* Array initializer of XBARB peripheral base addresses */
41586#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
41587/* Array initializer of XBARB peripheral base pointers */
41588#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
41589
41590/*
41591 * @}
41592 */ /* end of group XBARB_Peripheral_Access_Layer */
41593
41594
41595/* ----------------------------------------------------------------------------
41596 -- XTALOSC24M Peripheral Access Layer
41597 ---------------------------------------------------------------------------- */
41598
41599/*
41600 * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer
41601 * @{
41602 */
41603
41604/* XTALOSC24M - Register Layout Typedef */
41605typedef struct {
41606 uint8_t RESERVED_0[336];
41607 __IO uint32_t MISC0;
41608 __IO uint32_t MISC0_SET;
41609 __IO uint32_t MISC0_CLR;
41610 __IO uint32_t MISC0_TOG;
41611 uint8_t RESERVED_1[272];
41612 __IO uint32_t LOWPWR_CTRL;
41613 __IO uint32_t LOWPWR_CTRL_SET;
41614 __IO uint32_t LOWPWR_CTRL_CLR;
41615 __IO uint32_t LOWPWR_CTRL_TOG;
41616 uint8_t RESERVED_2[32];
41617 __IO uint32_t OSC_CONFIG0;
41618 __IO uint32_t OSC_CONFIG0_SET;
41619 __IO uint32_t OSC_CONFIG0_CLR;
41620 __IO uint32_t OSC_CONFIG0_TOG;
41621 __IO uint32_t OSC_CONFIG1;
41622 __IO uint32_t OSC_CONFIG1_SET;
41623 __IO uint32_t OSC_CONFIG1_CLR;
41624 __IO uint32_t OSC_CONFIG1_TOG;
41625 __IO uint32_t OSC_CONFIG2;
41626 __IO uint32_t OSC_CONFIG2_SET;
41627 __IO uint32_t OSC_CONFIG2_CLR;
41628 __IO uint32_t OSC_CONFIG2_TOG;
41629} XTALOSC24M_Type;
41630
41631/* ----------------------------------------------------------------------------
41632 -- XTALOSC24M Register Masks
41633 ---------------------------------------------------------------------------- */
41634
41635/*
41636 * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks
41637 * @{
41638 */
41639
41640/* @name MISC0 - Miscellaneous Register 0 */
41641/* @{ */
41642#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U)
41643#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U)
41644#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK)
41645#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
41646#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
41647/* REFTOP_SELFBIASOFF
41648 * 0b0..Uses coarse bias currents for startup
41649 * 0b1..Uses bandgap-based bias currents for best performance.
41650 */
41651#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK)
41652#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U)
41653#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U)
41654/* REFTOP_VBGADJ
41655 * 0b000..Nominal VBG
41656 * 0b001..VBG+0.78%
41657 * 0b010..VBG+1.56%
41658 * 0b011..VBG+2.34%
41659 * 0b100..VBG-0.78%
41660 * 0b101..VBG-1.56%
41661 * 0b110..VBG-2.34%
41662 * 0b111..VBG-3.12%
41663 */
41664#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK)
41665#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U)
41666#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U)
41667#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK)
41668#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
41669#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
41670/* STOP_MODE_CONFIG
41671 * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
41672 * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
41673 * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
41674 * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
41675 */
41676#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK)
41677#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
41678#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
41679/* DISCON_HIGH_SNVS
41680 * 0b0..Turn on the switch
41681 * 0b1..Turn off the switch
41682 */
41683#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK)
41684#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U)
41685#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U)
41686/* OSC_I
41687 * 0b00..Nominal
41688 * 0b01..Decrease current by 12.5%
41689 * 0b10..Decrease current by 25.0%
41690 * 0b11..Decrease current by 37.5%
41691 */
41692#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK)
41693#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U)
41694#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U)
41695#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK)
41696#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
41697#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U)
41698#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK)
41699#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
41700#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U)
41701/* CLKGATE_CTRL
41702 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
41703 * 0b1..Prevent the logic from ever gating off the clock.
41704 */
41705#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK)
41706#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
41707#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U)
41708/* CLKGATE_DELAY
41709 * 0b000..0.5ms
41710 * 0b001..1.0ms
41711 * 0b010..2.0ms
41712 * 0b011..3.0ms
41713 * 0b100..4.0ms
41714 * 0b101..5.0ms
41715 * 0b110..6.0ms
41716 * 0b111..7.0ms
41717 */
41718#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK)
41719#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
41720#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
41721/* RTC_XTAL_SOURCE
41722 * 0b0..Internal ring oscillator
41723 * 0b1..RTC_XTAL
41724 */
41725#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK)
41726#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
41727#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U)
41728#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK)
41729#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U)
41730#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U)
41731/* VID_PLL_PREDIV
41732 * 0b0..Divide by 1
41733 * 0b1..Divide by 2
41734 */
41735#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK)
41736/* @} */
41737
41738/* @name MISC0_SET - Miscellaneous Register 0 */
41739/* @{ */
41740#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U)
41741#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U)
41742#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK)
41743#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
41744#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
41745/* REFTOP_SELFBIASOFF
41746 * 0b0..Uses coarse bias currents for startup
41747 * 0b1..Uses bandgap-based bias currents for best performance.
41748 */
41749#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
41750#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
41751#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
41752/* REFTOP_VBGADJ
41753 * 0b000..Nominal VBG
41754 * 0b001..VBG+0.78%
41755 * 0b010..VBG+1.56%
41756 * 0b011..VBG+2.34%
41757 * 0b100..VBG-0.78%
41758 * 0b101..VBG-1.56%
41759 * 0b110..VBG-2.34%
41760 * 0b111..VBG-3.12%
41761 */
41762#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK)
41763#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
41764#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
41765#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK)
41766#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
41767#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
41768/* STOP_MODE_CONFIG
41769 * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
41770 * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
41771 * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
41772 * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
41773 */
41774#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK)
41775#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
41776#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
41777/* DISCON_HIGH_SNVS
41778 * 0b0..Turn on the switch
41779 * 0b1..Turn off the switch
41780 */
41781#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK)
41782#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U)
41783#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U)
41784/* OSC_I
41785 * 0b00..Nominal
41786 * 0b01..Decrease current by 12.5%
41787 * 0b10..Decrease current by 25.0%
41788 * 0b11..Decrease current by 37.5%
41789 */
41790#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK)
41791#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
41792#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U)
41793#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK)
41794#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
41795#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
41796#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK)
41797#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
41798#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
41799/* CLKGATE_CTRL
41800 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
41801 * 0b1..Prevent the logic from ever gating off the clock.
41802 */
41803#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK)
41804#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
41805#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
41806/* CLKGATE_DELAY
41807 * 0b000..0.5ms
41808 * 0b001..1.0ms
41809 * 0b010..2.0ms
41810 * 0b011..3.0ms
41811 * 0b100..4.0ms
41812 * 0b101..5.0ms
41813 * 0b110..6.0ms
41814 * 0b111..7.0ms
41815 */
41816#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK)
41817#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
41818#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
41819/* RTC_XTAL_SOURCE
41820 * 0b0..Internal ring oscillator
41821 * 0b1..RTC_XTAL
41822 */
41823#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK)
41824#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
41825#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
41826#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK)
41827#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U)
41828#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U)
41829/* VID_PLL_PREDIV
41830 * 0b0..Divide by 1
41831 * 0b1..Divide by 2
41832 */
41833#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK)
41834/* @} */
41835
41836/* @name MISC0_CLR - Miscellaneous Register 0 */
41837/* @{ */
41838#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
41839#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
41840#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK)
41841#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
41842#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
41843/* REFTOP_SELFBIASOFF
41844 * 0b0..Uses coarse bias currents for startup
41845 * 0b1..Uses bandgap-based bias currents for best performance.
41846 */
41847#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
41848#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
41849#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
41850/* REFTOP_VBGADJ
41851 * 0b000..Nominal VBG
41852 * 0b001..VBG+0.78%
41853 * 0b010..VBG+1.56%
41854 * 0b011..VBG+2.34%
41855 * 0b100..VBG-0.78%
41856 * 0b101..VBG-1.56%
41857 * 0b110..VBG-2.34%
41858 * 0b111..VBG-3.12%
41859 */
41860#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK)
41861#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
41862#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
41863#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK)
41864#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
41865#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
41866/* STOP_MODE_CONFIG
41867 * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
41868 * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
41869 * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
41870 * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
41871 */
41872#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK)
41873#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
41874#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
41875/* DISCON_HIGH_SNVS
41876 * 0b0..Turn on the switch
41877 * 0b1..Turn off the switch
41878 */
41879#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
41880#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U)
41881#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U)
41882/* OSC_I
41883 * 0b00..Nominal
41884 * 0b01..Decrease current by 12.5%
41885 * 0b10..Decrease current by 25.0%
41886 * 0b11..Decrease current by 37.5%
41887 */
41888#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK)
41889#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
41890#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
41891#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK)
41892#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
41893#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
41894#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK)
41895#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
41896#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
41897/* CLKGATE_CTRL
41898 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
41899 * 0b1..Prevent the logic from ever gating off the clock.
41900 */
41901#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK)
41902#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
41903#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
41904/* CLKGATE_DELAY
41905 * 0b000..0.5ms
41906 * 0b001..1.0ms
41907 * 0b010..2.0ms
41908 * 0b011..3.0ms
41909 * 0b100..4.0ms
41910 * 0b101..5.0ms
41911 * 0b110..6.0ms
41912 * 0b111..7.0ms
41913 */
41914#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK)
41915#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
41916#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
41917/* RTC_XTAL_SOURCE
41918 * 0b0..Internal ring oscillator
41919 * 0b1..RTC_XTAL
41920 */
41921#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
41922#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
41923#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
41924#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK)
41925#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U)
41926#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U)
41927/* VID_PLL_PREDIV
41928 * 0b0..Divide by 1
41929 * 0b1..Divide by 2
41930 */
41931#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK)
41932/* @} */
41933
41934/* @name MISC0_TOG - Miscellaneous Register 0 */
41935/* @{ */
41936#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
41937#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
41938#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK)
41939#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
41940#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
41941/* REFTOP_SELFBIASOFF
41942 * 0b0..Uses coarse bias currents for startup
41943 * 0b1..Uses bandgap-based bias currents for best performance.
41944 */
41945#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
41946#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
41947#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
41948/* REFTOP_VBGADJ
41949 * 0b000..Nominal VBG
41950 * 0b001..VBG+0.78%
41951 * 0b010..VBG+1.56%
41952 * 0b011..VBG+2.34%
41953 * 0b100..VBG-0.78%
41954 * 0b101..VBG-1.56%
41955 * 0b110..VBG-2.34%
41956 * 0b111..VBG-3.12%
41957 */
41958#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK)
41959#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
41960#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
41961#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK)
41962#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
41963#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
41964/* STOP_MODE_CONFIG
41965 * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
41966 * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
41967 * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
41968 * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
41969 */
41970#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK)
41971#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
41972#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
41973/* DISCON_HIGH_SNVS
41974 * 0b0..Turn on the switch
41975 * 0b1..Turn off the switch
41976 */
41977#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
41978#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U)
41979#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U)
41980/* OSC_I
41981 * 0b00..Nominal
41982 * 0b01..Decrease current by 12.5%
41983 * 0b10..Decrease current by 25.0%
41984 * 0b11..Decrease current by 37.5%
41985 */
41986#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK)
41987#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
41988#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
41989#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK)
41990#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
41991#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
41992#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK)
41993#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
41994#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
41995/* CLKGATE_CTRL
41996 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
41997 * 0b1..Prevent the logic from ever gating off the clock.
41998 */
41999#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK)
42000#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
42001#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
42002/* CLKGATE_DELAY
42003 * 0b000..0.5ms
42004 * 0b001..1.0ms
42005 * 0b010..2.0ms
42006 * 0b011..3.0ms
42007 * 0b100..4.0ms
42008 * 0b101..5.0ms
42009 * 0b110..6.0ms
42010 * 0b111..7.0ms
42011 */
42012#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK)
42013#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
42014#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
42015/* RTC_XTAL_SOURCE
42016 * 0b0..Internal ring oscillator
42017 * 0b1..RTC_XTAL
42018 */
42019#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
42020#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
42021#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
42022#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK)
42023#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U)
42024#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U)
42025/* VID_PLL_PREDIV
42026 * 0b0..Divide by 1
42027 * 0b1..Divide by 2
42028 */
42029#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK)
42030/* @} */
42031
42032/* @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */
42033/* @{ */
42034#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U)
42035#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U)
42036/* RC_OSC_EN
42037 * 0b0..Use XTAL OSC to source the 24MHz clock
42038 * 0b1..Use RC OSC
42039 */
42040#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK)
42041#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U)
42042#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U)
42043/* OSC_SEL
42044 * 0b0..XTAL OSC
42045 * 0b1..RC OSC
42046 */
42047#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK)
42048#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U)
42049#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U)
42050/* LPBG_SEL
42051 * 0b0..Normal power bandgap
42052 * 0b1..Low power bandgap
42053 */
42054#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
42055#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U)
42056#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U)
42057#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK)
42058#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U)
42059#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U)
42060#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK)
42061#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U)
42062#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U)
42063#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK)
42064#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U)
42065#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U)
42066#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK)
42067#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U)
42068#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U)
42069#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK)
42070#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U)
42071#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U)
42072#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK)
42073#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U)
42074#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U)
42075#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK)
42076#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
42077#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U)
42078/* XTALOSC_PWRUP_DELAY
42079 * 0b00..0.25ms
42080 * 0b01..0.5ms
42081 * 0b10..1ms
42082 * 0b11..2ms
42083 */
42084#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK)
42085#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U)
42086#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U)
42087/* XTALOSC_PWRUP_STAT
42088 * 0b0..Not stable
42089 * 0b1..Stable and ready to use
42090 */
42091#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK)
42092#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U)
42093#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U)
42094#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK)
42095#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U)
42096#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U)
42097#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK)
42098/* @} */
42099
42100/* @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */
42101/* @{ */
42102#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U)
42103#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U)
42104/* RC_OSC_EN
42105 * 0b0..Use XTAL OSC to source the 24MHz clock
42106 * 0b1..Use RC OSC
42107 */
42108#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK)
42109#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U)
42110#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U)
42111/* OSC_SEL
42112 * 0b0..XTAL OSC
42113 * 0b1..RC OSC
42114 */
42115#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK)
42116#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U)
42117#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U)
42118/* LPBG_SEL
42119 * 0b0..Normal power bandgap
42120 * 0b1..Low power bandgap
42121 */
42122#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK)
42123#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U)
42124#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U)
42125#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK)
42126#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U)
42127#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U)
42128#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK)
42129#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U)
42130#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U)
42131#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK)
42132#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U)
42133#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U)
42134#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK)
42135#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U)
42136#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U)
42137#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
42138#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U)
42139#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U)
42140#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK)
42141#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U)
42142#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U)
42143#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK)
42144#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
42145#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U)
42146/* XTALOSC_PWRUP_DELAY
42147 * 0b00..0.25ms
42148 * 0b01..0.5ms
42149 * 0b10..1ms
42150 * 0b11..2ms
42151 */
42152#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK)
42153#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U)
42154#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U)
42155/* XTALOSC_PWRUP_STAT
42156 * 0b0..Not stable
42157 * 0b1..Stable and ready to use
42158 */
42159#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK)
42160#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U)
42161#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U)
42162#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK)
42163#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U)
42164#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U)
42165#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK)
42166/* @} */
42167
42168/* @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */
42169/* @{ */
42170#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U)
42171#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U)
42172/* RC_OSC_EN
42173 * 0b0..Use XTAL OSC to source the 24MHz clock
42174 * 0b1..Use RC OSC
42175 */
42176#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK)
42177#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U)
42178#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U)
42179/* OSC_SEL
42180 * 0b0..XTAL OSC
42181 * 0b1..RC OSC
42182 */
42183#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK)
42184#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U)
42185#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U)
42186/* LPBG_SEL
42187 * 0b0..Normal power bandgap
42188 * 0b1..Low power bandgap
42189 */
42190#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK)
42191#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U)
42192#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U)
42193#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK)
42194#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U)
42195#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U)
42196#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK)
42197#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U)
42198#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U)
42199#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK)
42200#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U)
42201#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U)
42202#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK)
42203#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U)
42204#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U)
42205#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
42206#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U)
42207#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U)
42208#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK)
42209#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U)
42210#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U)
42211#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK)
42212#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
42213#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U)
42214/* XTALOSC_PWRUP_DELAY
42215 * 0b00..0.25ms
42216 * 0b01..0.5ms
42217 * 0b10..1ms
42218 * 0b11..2ms
42219 */
42220#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK)
42221#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U)
42222#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U)
42223/* XTALOSC_PWRUP_STAT
42224 * 0b0..Not stable
42225 * 0b1..Stable and ready to use
42226 */
42227#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK)
42228#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U)
42229#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U)
42230#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK)
42231#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U)
42232#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U)
42233#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK)
42234/* @} */
42235
42236/* @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */
42237/* @{ */
42238#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U)
42239#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U)
42240/* RC_OSC_EN
42241 * 0b0..Use XTAL OSC to source the 24MHz clock
42242 * 0b1..Use RC OSC
42243 */
42244#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK)
42245#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U)
42246#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U)
42247/* OSC_SEL
42248 * 0b0..XTAL OSC
42249 * 0b1..RC OSC
42250 */
42251#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK)
42252#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U)
42253#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U)
42254/* LPBG_SEL
42255 * 0b0..Normal power bandgap
42256 * 0b1..Low power bandgap
42257 */
42258#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK)
42259#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U)
42260#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U)
42261#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK)
42262#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U)
42263#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U)
42264#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK)
42265#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U)
42266#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U)
42267#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK)
42268#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U)
42269#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U)
42270#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK)
42271#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U)
42272#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U)
42273#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK)
42274#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U)
42275#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U)
42276#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK)
42277#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U)
42278#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U)
42279#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK)
42280#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U)
42281#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U)
42282/* XTALOSC_PWRUP_DELAY
42283 * 0b00..0.25ms
42284 * 0b01..0.5ms
42285 * 0b10..1ms
42286 * 0b11..2ms
42287 */
42288#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK)
42289#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U)
42290#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U)
42291/* XTALOSC_PWRUP_STAT
42292 * 0b0..Not stable
42293 * 0b1..Stable and ready to use
42294 */
42295#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK)
42296#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U)
42297#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U)
42298#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK)
42299#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U)
42300#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U)
42301#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK)
42302/* @} */
42303
42304/* @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */
42305/* @{ */
42306#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U)
42307#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U)
42308#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK)
42309#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U)
42310#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U)
42311#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK)
42312#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U)
42313#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U)
42314#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK)
42315#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U)
42316#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U)
42317#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK)
42318#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U)
42319#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U)
42320#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK)
42321#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U)
42322#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U)
42323#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK)
42324#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U)
42325#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U)
42326#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK)
42327#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U)
42328#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U)
42329#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK)
42330/* @} */
42331
42332/* @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */
42333/* @{ */
42334#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U)
42335#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U)
42336#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK)
42337#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U)
42338#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U)
42339#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK)
42340#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U)
42341#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U)
42342#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK)
42343#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U)
42344#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U)
42345#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK)
42346#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U)
42347#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U)
42348#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK)
42349#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U)
42350#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U)
42351#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK)
42352#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U)
42353#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U)
42354#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK)
42355#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U)
42356#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U)
42357#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK)
42358/* @} */
42359
42360/* @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */
42361/* @{ */
42362#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U)
42363#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U)
42364#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK)
42365#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U)
42366#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U)
42367#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK)
42368#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U)
42369#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U)
42370#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK)
42371#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U)
42372#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U)
42373#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK)
42374#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U)
42375#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U)
42376#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK)
42377#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U)
42378#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U)
42379#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK)
42380#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U)
42381#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U)
42382#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK)
42383#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U)
42384#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U)
42385#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK)
42386/* @} */
42387
42388/* @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */
42389/* @{ */
42390#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U)
42391#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U)
42392#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK)
42393#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U)
42394#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U)
42395#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK)
42396#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U)
42397#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U)
42398#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK)
42399#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U)
42400#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U)
42401#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK)
42402#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U)
42403#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U)
42404#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK)
42405#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U)
42406#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U)
42407#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK)
42408#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U)
42409#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U)
42410#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK)
42411#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U)
42412#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U)
42413#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK)
42414/* @} */
42415
42416/* @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */
42417/* @{ */
42418#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU)
42419#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U)
42420#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK)
42421#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U)
42422#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U)
42423#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK)
42424/* @} */
42425
42426/* @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */
42427/* @{ */
42428#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU)
42429#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U)
42430#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK)
42431#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U)
42432#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U)
42433#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK)
42434/* @} */
42435
42436/* @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */
42437/* @{ */
42438#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU)
42439#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U)
42440#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK)
42441#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U)
42442#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U)
42443#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK)
42444/* @} */
42445
42446/* @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */
42447/* @{ */
42448#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU)
42449#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U)
42450#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK)
42451#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U)
42452#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U)
42453#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK)
42454/* @} */
42455
42456/* @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */
42457/* @{ */
42458#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU)
42459#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U)
42460#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK)
42461#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U)
42462#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U)
42463#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
42464#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U)
42465#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U)
42466#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK)
42467#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U)
42468#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U)
42469#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK)
42470/* @} */
42471
42472/* @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */
42473/* @{ */
42474#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU)
42475#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U)
42476#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK)
42477#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U)
42478#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U)
42479#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK)
42480#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U)
42481#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U)
42482#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK)
42483#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U)
42484#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U)
42485#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK)
42486/* @} */
42487
42488/* @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */
42489/* @{ */
42490#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU)
42491#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U)
42492#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK)
42493#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U)
42494#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U)
42495#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK)
42496#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U)
42497#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U)
42498#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK)
42499#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U)
42500#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U)
42501#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK)
42502/* @} */
42503
42504/* @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */
42505/* @{ */
42506#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU)
42507#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U)
42508#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK)
42509#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U)
42510#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U)
42511#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK)
42512#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U)
42513#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U)
42514#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK)
42515#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U)
42516#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U)
42517#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK)
42518/* @} */
42519
42520
42521/*
42522 * @}
42523 */ /* end of group XTALOSC24M_Register_Masks */
42524
42525
42526/* XTALOSC24M - Peripheral instance base addresses */
42527/* Peripheral XTALOSC24M base address */
42528#define XTALOSC24M_BASE (0x400D8000u)
42529/* Peripheral XTALOSC24M base pointer */
42530#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE)
42531/* Array initializer of XTALOSC24M peripheral base addresses */
42532#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE }
42533/* Array initializer of XTALOSC24M peripheral base pointers */
42534#define XTALOSC24M_BASE_PTRS { XTALOSC24M }
42535
42536/*
42537 * @}
42538 */ /* end of group XTALOSC24M_Peripheral_Access_Layer */
42539
42540
42541/*
42542** End of section using anonymous unions
42543*/
42544
42545#if defined(__ARMCC_VERSION)
42546 #if (__ARMCC_VERSION >= 6010050)
42547 #pragma clang diagnostic pop
42548 #else
42549 #pragma pop
42550 #endif
42551#elif defined(__CWCC__)
42552 #pragma pop
42553#elif defined(__GNUC__)
42554 /* leave anonymous unions enabled */
42555#elif defined(__IAR_SYSTEMS_ICC__)
42556 #pragma language=default
42557#else
42558 #error Not supported compiler type
42559#endif
42560
42561/*
42562 * @}
42563 */ /* end of group Peripheral_access_layer */
42564
42565
42566/* ----------------------------------------------------------------------------
42567 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
42568 ---------------------------------------------------------------------------- */
42569
42570/*
42571 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
42572 * @{
42573 */
42574
42575#if defined(__ARMCC_VERSION)
42576 #if (__ARMCC_VERSION >= 6010050)
42577 #pragma clang system_header
42578 #endif
42579#elif defined(__IAR_SYSTEMS_ICC__)
42580 #pragma system_include
42581#endif
42582
42589#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
42596#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
42597
42598/*
42599 * @}
42600 */ /* end of group Bit_Field_Generic_Macros */
42601
42602
42603/* ----------------------------------------------------------------------------
42604 -- SDK Compatibility
42605 ---------------------------------------------------------------------------- */
42606
42607/*
42608 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
42609 * @{
42610 */
42611
42612/* No SDK compatibility issues. */
42613
42614/*
42615 * @}
42616 */ /* end of group SDK_Compatibility_Symbols */
42617
42618
42619#endif /* _MIMXRT1061_H_ */
42620